2026-05-15 16:42:37

Author: mohanson

src/apu.rs

@@ -851,18 +851,8 @@ impl Apu {
         f32::from(self.nr50 & 0x07) / 7.0 / 15.0 * 0.25
     }
 
-    // ─── Helpers ───────────────────────────────────────────────────────────
-
-    fn xtra_clock(&self) -> bool {
-        // "First half" of the length period (Pan Docs obscure behaviour): the
-        // FS step just past an even step. step%2==0 means the *next* clock will
-        // be a length clock, i.e. we are in the half that triggers extras.
-        self.fs.s & 1 == 0
-    }
-
-    /// Compute the live wave sample index based on elapsed T-cycles since the
-    /// last trigger. The wave timer fires once every period T-cycles after an
-    /// initial `period_at_trigger + 6` T-cycle warm-up.
+    // Compute the live wave sample index based on elapsed T-cycles since the last trigger. The wave timer fires once
+    // every period T-cycles after an initial period_at_trigger + 6 T-cycle warm-up.
     fn live_wave(&self) -> u64 {
         let p_now = u64::from(self.ch3.tmr.p);
         let p_trg = u64::from(self.ch3.p1);
@@ -888,9 +878,8 @@ impl Apu {
         elapsed - t_last < 2
     }
 
-    fn power_off(&mut self) {
-        // Zero every channel register except wave RAM and (on DMG) length
-        // counters.
+    fn power_no(&mut self) {
+        // Zero every channel register except wave RAM and (on DMG) length counters.
         for i in 0..5 {
             self.ch1.reg.n[i] = 0;
         }
@@ -918,9 +907,8 @@ impl Apu {
     }
 
     fn power_on(&mut self) {
-        // Phase-align the frame sequencer with DIV: the next FS clock occurs at
-        // the next falling edge of sdiv bit 12. If that bit is already high at
-        // power-on, the very first FS event is skipped (hardware glitch).
+        // Phase-align the frame sequencer with DIV: the next FS clock occurs at the next falling edge of sdiv bit 12.
+        // If that bit is already high at power-on, the very first FS event is skipped (hardware glitch).
         self.fs.s = 7;
         self.ft.n = u32::from(self.sdiv) % (CLOCK_FREQUENCY / 512);
         self.fs_skip = self.sdiv & 0x1000 != 0;
@@ -935,10 +923,6 @@ impl Apu {
     }
 }
 
-// ────────────────────────────────────────────────────────────────────────────
-// Memory bus.
-// ────────────────────────────────────────────────────────────────────────────
-
 impl Memory for Apu {
     fn lb(&self, a: u16) -> u8 {
         let v = match a {
@@ -974,9 +958,8 @@ impl Memory for Apu {
     }
 
     fn sb(&mut self, a: u16, v: u8) {
-        // Power gating: all channel/NR50/NR51 writes are blocked while the APU
-        // is off, except wave RAM and NR52 itself. On DMG, length-counter
-        // pre-loads via NRx1 remain writable.
+        // Power gating: all channel/NR50/NR51 writes are blocked while the APU is off, except wave RAM and NR52
+        // itself. On DMG, length-counter pre-loads via NRx1 remain writable.
         if !self.pwr && a != 0xff26 && !(0xff30..=0xff3f).contains(&a) {
             if self.glo.borrow().term == Term::DMG {
                 match a {
@@ -1002,7 +985,9 @@ impl Memory for Apu {
             return;
         }
 
-        let xtra = self.xtra_clock();
+        // First half of the length period (Pan Docs obscure behaviour): the FS step just past an even step. step%2==0
+        // means the next clock will be a length clock, i.e. we are in the half that triggers extras.
+        let xtra = self.fs.s & 1 == 0;
         match a {
             0xff10 => {
                 if self.ch1.fs.nr10di(&self.ch1.reg, v) {
@@ -1034,13 +1019,28 @@ impl Memory for Apu {
                 let was = self.pwr;
                 self.pwr = v & 0x80 != 0;
                 if was && !self.pwr {
-                    self.power_off();
+                    self.power_no();
                 } else if !was && self.pwr {
                     self.power_on();
                 }
             }
             0xff27..=0xff2f => {}
-            0xff30..=0xff3f => self.write_wave_ram(a, v),
+            0xff30..=0xff3f => {
+                if self.ch3.on && self.ch3.reg.dac_wv() {
+                    let fires = self.live_wave();
+                    let addr = self.wave_addr(fires);
+                    match self.glo.borrow().term {
+                        Term::CGB => self.ch3.ram[addr] = v,
+                        Term::DMG => {
+                            if self.dmg_wave_window(fires) {
+                                self.ch3.ram[addr] = v;
+                            }
+                        }
+                    }
+                } else {
+                    self.ch3.ram[(a - 0xff30) as usize] = v;
+                }
+            }
             _ => unreachable!(),
         }
     }
@@ -1061,46 +1061,22 @@ impl Apu {
         };
 
         if trig {
-            // Record live-wave snapshot before sb_nrx4 reloads the timer.
             self.ch3.t_s_div = sdiv;
             self.ch3.d1 = 0;
             self.ch3.t_apu_n = self.ft.n;
             self.ch3.t_frame = self.fc;
         }
         self.ch3.nrx4sb(v, xtra, dmg_off);
         if trig {
-            // p1 takes the *new* period (post-NR34 high-bits).
             self.ch3.p1 = self.ch3.tmr.p;
         }
     }
-
-    fn write_wave_ram(&mut self, a: u16, v: u8) {
-        if self.ch3.on && self.ch3.reg.dac_wv() {
-            let fires = self.live_wave();
-            let addr = self.wave_addr(fires);
-            match self.glo.borrow().term {
-                Term::CGB => self.ch3.ram[addr] = v,
-                Term::DMG => {
-                    if self.dmg_wave_window(fires) {
-                        self.ch3.ram[addr] = v;
-                    }
-                }
-            }
-        } else {
-            self.ch3.ram[(a - 0xff30) as usize] = v;
-        }
-    }
 }
 
-// ────────────────────────────────────────────────────────────────────────────
-// Clocking.
-// ────────────────────────────────────────────────────────────────────────────
-
 impl Ticker for Apu {
     fn tick(&mut self, cycles: u16) {
         // The DIV-APU 512 Hz counter runs regardless of power state.
         let n = self.ft.step(u32::from(cycles));
-
         if !self.pwr {
             for _ in 0..n {
                 if self.fs_skip {
@@ -1112,20 +1088,17 @@ impl Ticker for Apu {
             }
             return;
         }
-
         for _ in 0..n {
             if self.fs_skip {
                 self.fs_skip = false;
                 self.fc = self.fc.wrapping_add(1);
                 continue;
             }
-
             let p = self.ft.p;
             self.ch1.step(p);
             self.ch2.step(p);
             self.ch3.step(p);
             self.ch4.step(p);
-
             let s = self.fs.step();
             if Fseq::len(s) {
                 if self.ch1.lc.step(&self.ch1.reg) {
@@ -1158,7 +1131,6 @@ impl Ticker for Apu {
                 }
                 self.ch1.tmr.p = self.ch1.reg.per_sq();
             }
-
             self.ch1.buf.end(p);
             self.ch2.buf.end(p);
             self.ch3.buf.end(p);
@@ -1169,30 +1141,25 @@ impl Ticker for Apu {
     }
 }
 
-// ────────────────────────────────────────────────────────────────────────────
 // DMG wave-RAM corruption timing model (SameBoy-compatible).
 //
-// The internal sample-countdown is loaded with `p1/2 + 2` 2-MHz cycles after
-// the first trigger and reset to `p/2 − 1` on every fire (where p is the
-// current period in T-cycles). Re-triggering while `sample_countdown == 0`
-// corrupts wave RAM at byte offset `((csi + 1) >> 1) & 0xF`.
+// The internal sample-countdown is loaded with p1/2 + 2 2-MHz cycles after the first trigger and reset to p/2 − 1
+// on every fire (where p is the current period in T-cycles). Re-triggering while sample_countdown == 0. Corrupts wave
+// RAM at byte offset ((csi + 1) >> 1) & 0xF.
 //
-//   p1_h  P1/2 (2-MHz cycles) at first trigger
-//   d1    2-MHz cycles between the first trigger and the last NR33 write
-//   d2    2-MHz cycles between that NR33 write and the re-trigger
-//   p2_h  P2/2 (2-MHz cycles) — the current period
-// ────────────────────────────────────────────────────────────────────────────
+// p1_h  P1/2 (2-MHz cycles) at first trigger
+// d1    2-MHz cycles between the first trigger and the last NR33 write
+// d2    2-MHz cycles between that NR33 write and the re-trigger
+// p2_h  P2/2 (2-MHz cycles) — the current period
 
 fn dmg_corrupt_offset(p1_h: u32, d1: u32, d2: u32, p2_h: u32) -> Option<usize> {
     if p1_h == 0 || p2_h == 0 {
         return None;
     }
     let c1 = p1_h - 1;
     let c2 = p2_h - 1;
-
     let mut sc: u32 = c1 + 3;
     let mut csi: u32 = 0;
-
     // Phase 1.
     if sc >= d1 {
         sc -= d1;
@@ -1211,6 +1178,5 @@ fn dmg_corrupt_offset(p1_h: u32, d1: u32, d2: u32, p2_h: u32) -> Option<usize> {
         csi = csi.wrapping_add(rem / (c2 + 1)) & 0x1f;
         sc = c2.saturating_sub(rem % (c2 + 1));
     }
-
     if sc == 0 { Some(((csi as usize + 1) >> 1) & 0xf) } else { None }
 }