Skip to content

Commit 8d2dd3e

Browse files
mohansonmohanson
committed
2026-05-15 15:53:45
1 parent 8ee265b commit 8d2dd3e

2 files changed

Lines changed: 49 additions & 48 deletions

File tree

‎src/apu.rs‎

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use crate::convention::{CLOCK_FREQUENCY, Global, Memory, Term, Ticker, hi, lo};
1+
use crate::convention::{CLOCK_FREQUENCY, Global, Memory, SAMPLE_RATE, Term, Ticker, hi, lo};
22
use blip_buf::BlipBuf;
33
use std::cell::RefCell;
44
use std::rc::Rc;
@@ -334,44 +334,44 @@ const DUTY: [u8; 4] = [0b0000_0001, 0b1000_0001, 0b1000_0111, 0b0111_1110];
334334

335335
// CH1: square wave with sweep.
336336
struct Sq1 {
337-
r: Reg,
338-
on: bool,
337+
buf: Blip,
338+
idx: u8,
339+
reg: Reg,
339340
tmr: Tmr,
341+
fs: Swp,
340342
lc: Lc,
341-
env: Env,
342-
swp: Swp,
343-
blip: Blip,
344-
idx: u8,
343+
on: bool,
344+
ve: Env,
345345
}
346346

347347
impl Sq1 {
348-
fn new(sr: u32) -> Self {
348+
fn power_up() -> Self {
349349
let mut r = Reg::power_up();
350350
r.n[1] = 0x40;
351351
Self {
352-
r,
353-
on: false,
352+
buf: Blip::power_up(SAMPLE_RATE),
353+
idx: 1,
354+
reg: r,
354355
tmr: Tmr::power_up(8192),
356+
fs: Swp::power_up(),
355357
lc: Lc::power_up(),
356-
env: Env::power_up(),
357-
swp: Swp::power_up(),
358-
blip: Blip::power_up(sr),
359-
idx: 1,
358+
on: false,
359+
ve: Env::power_up(),
360360
}
361361
}
362362

363363
fn tick(&mut self, c: u32) {
364-
let pat = DUTY[self.r.duty() as usize];
365-
let v = i32::from(self.env.v);
364+
let pat = DUTY[self.reg.duty() as usize];
365+
let v = i32::from(self.ve.v);
366366
for _ in 0..self.tmr.step(c) {
367-
let a = if !self.on || self.env.v == 0 {
367+
let a = if !self.on || self.ve.v == 0 {
368368
0
369369
} else if (pat >> self.idx) & 1 != 0 {
370370
v
371371
} else {
372372
-v
373373
};
374-
self.blip.put(self.blip.t.wrapping_add(self.tmr.p), a);
374+
self.buf.put(self.buf.t.wrapping_add(self.tmr.p), a);
375375
self.idx = (self.idx + 1) & 7;
376376
}
377377
}
@@ -382,26 +382,26 @@ impl Sq1 {
382382
if self.lc.n == 0 {
383383
self.lc.n = 64;
384384
}
385-
self.tmr.p = self.r.per_sq();
386-
self.env.reload(&self.r);
387-
if self.swp.reload(&self.r) {
385+
self.tmr.p = self.reg.per_sq();
386+
self.ve.reload(&self.reg);
387+
if self.fs.reload(&self.reg) {
388388
self.on = false;
389389
}
390390
// Extra-length-clock obscure: if length was 0 and the FS just clocked
391391
// length on the previous step, the reloaded counter is decremented.
392-
if xtra && self.r.len_en() && len0 && self.lc.n != 0 {
392+
if xtra && self.reg.len_en() && len0 && self.lc.n != 0 {
393393
self.lc.n -= 1;
394394
}
395-
if !self.r.dac_sq() {
395+
if !self.reg.dac_sq() {
396396
self.on = false;
397397
}
398398
}
399399

400400
fn write_nrx4(&mut self, v: u8, xtra: bool) {
401-
let old_en = self.r.len_en();
402-
self.r.n[4] = v;
403-
self.tmr.p = self.r.per_sq();
404-
if xtra && !old_en && self.lc.step(&self.r) {
401+
let old_en = self.reg.len_en();
402+
self.reg.n[4] = v;
403+
self.tmr.p = self.reg.per_sq();
404+
if xtra && !old_en && self.lc.step(&self.reg) {
405405
self.on = false;
406406
}
407407
if v & 0x80 != 0 {
@@ -412,24 +412,24 @@ impl Sq1 {
412412

413413
impl Memory for Sq1 {
414414
fn lb(&self, a: u16) -> u8 {
415-
self.r.n[(a - 0xff10) as usize]
415+
self.reg.n[(a - 0xff10) as usize]
416416
}
417417
fn sb(&mut self, a: u16, v: u8) {
418418
match a {
419-
0xff10 => self.r.n[0] = v | 0x80,
419+
0xff10 => self.reg.n[0] = v | 0x80,
420420
0xff11 => {
421-
self.r.n[1] = v;
422-
self.lc.n = self.r.len_load_sq();
421+
self.reg.n[1] = v;
422+
self.lc.n = self.reg.len_load_sq();
423423
}
424424
0xff12 => {
425-
self.r.n[2] = v;
426-
if !self.r.dac_sq() {
425+
self.reg.n[2] = v;
426+
if !self.reg.dac_sq() {
427427
self.on = false;
428428
}
429429
}
430430
0xff13 => {
431-
self.r.n[3] = v;
432-
self.tmr.p = self.r.per_sq();
431+
self.reg.n[3] = v;
432+
self.tmr.p = self.reg.per_sq();
433433
}
434434
0xff14 => self.write_nrx4(v, false),
435435
_ => unreachable!(),
@@ -813,7 +813,7 @@ impl Apu {
813813
nr50: 0,
814814
nr51: 0,
815815
pwr: false,
816-
ch1: Sq1::new(sr),
816+
ch1: Sq1::power_up(),
817817
ch2: Sq2::new(sr),
818818
ch3: Wv::new(sr),
819819
ch4: Ns::new(sr),
@@ -835,7 +835,7 @@ impl Apu {
835835
}
836836

837837
fn mix(&mut self) {
838-
let n = self.ch1.blip.d.samples_avail() as usize;
838+
let n = self.ch1.buf.d.samples_avail() as usize;
839839
debug_assert_eq!(n, self.ch2.blip.d.samples_avail() as usize);
840840
debug_assert_eq!(n, self.ch3.blip.d.samples_avail() as usize);
841841
debug_assert_eq!(n, self.ch4.blip.d.samples_avail() as usize);
@@ -862,7 +862,7 @@ impl Apu {
862862
}
863863
};
864864

865-
let c1 = read(&mut self.ch1.blip, &mut t);
865+
let c1 = read(&mut self.ch1.buf, &mut t);
866866
mix_into(&t[..c1], &mut l, &mut r, pan & 0x10 != 0, pan & 0x01 != 0);
867867
let c2 = read(&mut self.ch2.blip, &mut t);
868868
mix_into(&t[..c2], &mut l, &mut r, pan & 0x20 != 0, pan & 0x02 != 0);
@@ -928,7 +928,7 @@ impl Apu {
928928
// Zero every channel register except wave RAM and (on DMG) length
929929
// counters.
930930
for i in 0..5 {
931-
self.ch1.r.n[i] = 0;
931+
self.ch1.reg.n[i] = 0;
932932
}
933933
for i in 0..5 {
934934
self.ch2.r.n[i] = 0;
@@ -1017,8 +1017,8 @@ impl Memory for Apu {
10171017
if self.glo.borrow().term == Term::DMG {
10181018
match a {
10191019
0xff11 => {
1020-
self.ch1.r.n[1] = v & 0x3f;
1021-
self.ch1.lc.n = self.ch1.r.len_load_sq();
1020+
self.ch1.reg.n[1] = v & 0x3f;
1021+
self.ch1.lc.n = self.ch1.reg.len_load_sq();
10221022
}
10231023
0xff16 => {
10241024
self.ch2.r.n[1] = v & 0x3f;
@@ -1041,10 +1041,10 @@ impl Memory for Apu {
10411041
let xtra = self.xtra_clock();
10421042
match a {
10431043
0xff10 => {
1044-
if self.ch1.swp.nr10di(&self.ch1.r, v) {
1044+
if self.ch1.fs.nr10di(&self.ch1.reg, v) {
10451045
self.ch1.on = false;
10461046
}
1047-
self.ch1.r.n[0] = v | 0x80;
1047+
self.ch1.reg.n[0] = v | 0x80;
10481048
}
10491049
0xff11..=0xff13 => self.ch1.sb(a, v),
10501050
0xff14 => self.ch1.write_nrx4(v, xtra),
@@ -1166,7 +1166,7 @@ impl Ticker for Apu {
11661166

11671167
let s = self.fs.step();
11681168
if Fseq::len(s) {
1169-
if self.ch1.lc.step(&self.ch1.r) {
1169+
if self.ch1.lc.step(&self.ch1.reg) {
11701170
self.ch1.on = false;
11711171
}
11721172
if self.ch2.lc.step(&self.ch2.r) {
@@ -1181,7 +1181,7 @@ impl Ticker for Apu {
11811181
}
11821182
if Fseq::env(s) {
11831183
if self.ch1.on {
1184-
self.ch1.env.step(&self.ch1.r);
1184+
self.ch1.ve.step(&self.ch1.reg);
11851185
}
11861186
if self.ch2.on {
11871187
self.ch2.env.step(&self.ch2.r);
@@ -1191,13 +1191,13 @@ impl Ticker for Apu {
11911191
}
11921192
}
11931193
if Fseq::swp(s) && self.ch1.on {
1194-
if self.ch1.swp.step(&mut self.ch1.r) {
1194+
if self.ch1.fs.step(&mut self.ch1.reg) {
11951195
self.ch1.on = false;
11961196
}
1197-
self.ch1.tmr.p = self.ch1.r.per_sq();
1197+
self.ch1.tmr.p = self.ch1.reg.per_sq();
11981198
}
11991199

1200-
self.ch1.blip.end(p);
1200+
self.ch1.buf.end(p);
12011201
self.ch2.blip.end(p);
12021202
self.ch3.blip.end(p);
12031203
self.ch4.blip.end(p);

‎src/convention.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ pub enum OamBug {
2525
}
2626

2727
pub const CLOCK_FREQUENCY: u32 = 4_194_304;
28+
pub const SAMPLE_RATE: u32 = 48_000;
2829
pub const SCREEN_W: usize = 160;
2930
pub const SCREEN_H: usize = 144;
3031
pub const STEP_TIME: u32 = 16;

0 commit comments

Comments
 (0)