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While we didn't make any API-breaking changes, previously the widest
native vector width was 256 bits, and downstream code could implicitly
depend on it. #261 demonstrates this failure mode. So I think calling it
0.6.0 is prudent.
Copy file name to clipboardExpand all lines: CHANGELOG.md
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@@ -6,20 +6,30 @@ Subheadings to categorize changes are `added, changed, deprecated, removed, fixe
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The latest published Fearless SIMD release is [0.5.0](#050-2026-06-18) which was released on 2026-06-18.
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You can find its changes [documented below](#050-2026-06-18).
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The latest published Fearless SIMD release is [0.6.0](#060-2026-07-10) which was released on 2026-07-10.
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You can find its changes [documented below](#060-2026-07-10).
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## [Unreleased]
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## [0.6.0][] (2026-07-10)
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This release has an [MSRV][] of 1.89.
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### Added
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- Added Ice Lake-class AVX-512 support with a generated `Avx512` level and 512-bit native-width vector types.
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- Added Ice Lake-class AVX-512 support with a generated `Avx512` level and 512-bit native-width vector types. ([#231][] by [@Shnatsel][])
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- Added controls for x86 automatic multiversioning using `cfg` flags, letting final binary builds decide which levels `dispatch!` uses. ([#258][], [#264][] by [@Shnatsel][])
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- Added the `swizzle_dyn_within_blocks` method on SIMD vector types for dynamic byte-indexed swizzles within each native-width block. ([#266][] by [@Shnatsel][])
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### Changed
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- The MSRV is now Rust 1.89.
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- The MSRV is now Rust 1.89. ([#231][] by [@Shnatsel][])
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- Documentation and examples have been expanded and cleaned up to show autovectorization, use of intrinsics, x86 multiversioning, and AVX-512-width inputs. ([#252][], [#258][], [#261][], [#264][] by [@Shnatsel][])
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-`Level::Fallback` and x86 `Level::Sse4_2` variants now remain available whenever their token types exist. ([#264][] by [@Shnatsel][])
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### Fixed
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-`dispatch!` and `Level::dispatch` now correctly omit AVX2 code paths when the Ice Lake/AVX-512 feature set is available. ([#263][] by [@Shnatsel][])
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## [0.5.0][] (2026-06-18)
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