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cristibirsancristibirsan
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Merge tag 'tags/fpga-spi-260609' into linux-6.18-mchp
FPGA spi updates for 260609 * spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations (Conor Dooley 2026-03-30) * spi: microchip-core-qspi: remove some inline markings (Conor Dooley 2026-02-24) * spi: microchip-core-qspi: report device on which timeout occured instead of which controller (Conor Dooley 2026-02-24) * spi: microchip-core-qspi: remove an unused define (Conor Dooley 2026-02-24) * spi: microchip-core-qspi: control built-in cs manually (Conor Dooley 2026-02-24) Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2 parents dc57604 + 0edfa4d commit 505aa76

1 file changed

Lines changed: 83 additions & 22 deletions

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‎drivers/spi/spi-microchip-core-qspi.c‎

Lines changed: 83 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,13 @@
7474
#define STATUS_FLAGSX4 BIT(8)
7575
#define STATUS_MASK GENMASK(8, 0)
7676

77+
/*
78+
* QSPI Direct Access register defines
79+
*/
80+
#define DIRECT_ACCESS_EN_SSEL BIT(0)
81+
#define DIRECT_ACCESS_OP_SSEL BIT(1)
82+
#define DIRECT_ACCESS_OP_SSEL_SHIFT 1
83+
7784
#define BYTESUPPER_MASK GENMASK(31, 16)
7885
#define BYTESLOWER_MASK GENMASK(15, 0)
7986

@@ -92,7 +99,6 @@
9299
#define REG_IEN (0x0c)
93100
#define REG_STATUS (0x10)
94101
#define REG_DIRECT_ACCESS (0x14)
95-
#define REG_UPPER_ACCESS (0x18)
96102
#define REG_RX_DATA (0x40)
97103
#define REG_TX_DATA (0x44)
98104
#define REG_X4_RX_DATA (0x48)
@@ -158,7 +164,42 @@ static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_m
158164
return 0;
159165
}
160166

161-
static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
167+
static void mchp_coreqspi_set_cs(struct spi_device *spi, bool enable)
168+
{
169+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(spi->controller);
170+
u32 val;
171+
172+
val = readl(qspi->regs + REG_DIRECT_ACCESS);
173+
174+
val &= ~BIT(1);
175+
if (spi->mode & SPI_CS_HIGH)
176+
val |= enable << DIRECT_ACCESS_OP_SSEL_SHIFT;
177+
else
178+
val |= !enable << DIRECT_ACCESS_OP_SSEL_SHIFT;
179+
180+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
181+
}
182+
183+
static int mchp_coreqspi_setup(struct spi_device *spi)
184+
{
185+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(spi->controller);
186+
u32 val;
187+
188+
/*
189+
* Active low devices need to be specifically set to their inactive
190+
* states during probe.
191+
*/
192+
if (spi->mode & SPI_CS_HIGH)
193+
return 0;
194+
195+
val = readl(qspi->regs + REG_DIRECT_ACCESS);
196+
val |= DIRECT_ACCESS_OP_SSEL;
197+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
198+
199+
return 0;
200+
}
201+
202+
static void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
162203
{
163204
u32 control, data;
164205

@@ -194,7 +235,7 @@ static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
194235
}
195236
}
196237

197-
static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
238+
static void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
198239
{
199240
u32 control, data;
200241

@@ -222,7 +263,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
222263
}
223264
}
224265

225-
static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi)
266+
static void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi)
226267
{
227268
u32 control, data;
228269

@@ -380,20 +421,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devi
380421
return 0;
381422
}
382423

383-
static int mchp_coreqspi_setup_op(struct spi_device *spi_dev)
384-
{
385-
struct spi_controller *ctlr = spi_dev->controller;
386-
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
387-
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
388-
389-
control |= (CONTROL_MASTER | CONTROL_ENABLE);
390-
control &= ~CONTROL_CLKIDLE;
391-
writel_relaxed(control, qspi->regs + REG_CONTROL);
392-
393-
return 0;
394-
}
395-
396-
static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
424+
static void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
397425
{
398426
u32 idle_cycles = 0;
399427
int total_bytes, cmd_bytes, frames, ctrl;
@@ -483,6 +511,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
483511

484512
reinit_completion(&qspi->data_completion);
485513
mchp_coreqspi_config_op(qspi, op);
514+
mchp_coreqspi_set_cs(mem->spi, true);
486515
if (op->cmd.opcode) {
487516
qspi->txbuf = &opcode;
488517
qspi->rxbuf = NULL;
@@ -523,6 +552,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
523552
err = -ETIMEDOUT;
524553

525554
error:
555+
mchp_coreqspi_set_cs(mem->spi, false);
526556
mutex_unlock(&qspi->op_lock);
527557
mchp_coreqspi_disable_ints(qspi);
528558

@@ -604,7 +634,7 @@ static int mchp_coreqspi_prepare_message(struct spi_controller *ctlr, struct spi
604634
ret = mchp_coreqspi_wait_for_ready(qspi);
605635
if (ret) {
606636
mutex_unlock(&qspi->op_lock);
607-
dev_err(&ctlr->dev, "Timeout waiting on QSPI ready.\n");
637+
dev_err(&m->spi->dev, "Timeout waiting on QSPI ready.\n");
608638
return ret;
609639
}
610640

@@ -662,18 +692,28 @@ static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_de
662692
struct spi_transfer *t)
663693
{
664694
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
695+
bool dual_quad = false;
665696

666697
qspi->tx_len = t->len;
667698

699+
if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD ||
700+
t->tx_nbits == SPI_NBITS_DUAL ||
701+
t->rx_nbits == SPI_NBITS_DUAL)
702+
dual_quad = true;
703+
668704
if (t->tx_buf)
669705
qspi->txbuf = (u8 *)t->tx_buf;
670706

671707
if (!t->rx_buf) {
672708
mchp_coreqspi_write_op(qspi);
673-
} else {
709+
} else if (!dual_quad) {
674710
qspi->rxbuf = (u8 *)t->rx_buf;
675711
qspi->rx_len = t->len;
676712
mchp_coreqspi_write_read_op(qspi);
713+
} else {
714+
qspi->rxbuf = (u8 *)t->rx_buf;
715+
qspi->rx_len = t->len;
716+
mchp_coreqspi_read_op(qspi);
677717
}
678718

679719
return 0;
@@ -686,6 +726,7 @@ static int mchp_coreqspi_probe(struct platform_device *pdev)
686726
struct device *dev = &pdev->dev;
687727
struct device_node *np = dev->of_node;
688728
int ret;
729+
u32 num_cs, val;
689730

690731
ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi));
691732
if (!ctlr)
@@ -718,20 +759,40 @@ static int mchp_coreqspi_probe(struct platform_device *pdev)
718759
return ret;
719760
}
720761

762+
/*
763+
* The IP core only has a single CS, any more have to be provided via
764+
* gpios
765+
*/
766+
if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
767+
num_cs = 1;
768+
769+
ctlr->num_chipselect = num_cs;
770+
721771
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
722772
ctlr->mem_ops = &mchp_coreqspi_mem_ops;
723773
ctlr->mem_caps = &mchp_coreqspi_mem_caps;
724-
ctlr->setup = mchp_coreqspi_setup_op;
725774
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
726775
SPI_TX_DUAL | SPI_TX_QUAD;
727776
ctlr->dev.of_node = np;
728777
ctlr->min_speed_hz = clk_get_rate(qspi->clk) / 30;
729778
ctlr->prepare_message = mchp_coreqspi_prepare_message;
730779
ctlr->unprepare_message = mchp_coreqspi_unprepare_message;
731780
ctlr->transfer_one = mchp_coreqspi_transfer_one;
732-
ctlr->num_chipselect = 2;
781+
ctlr->setup = mchp_coreqspi_setup;
782+
ctlr->set_cs = mchp_coreqspi_set_cs;
733783
ctlr->use_gpio_descriptors = true;
734784

785+
val = readl_relaxed(qspi->regs + REG_CONTROL);
786+
val |= (CONTROL_MASTER | CONTROL_ENABLE);
787+
writel_relaxed(val, qspi->regs + REG_CONTROL);
788+
789+
/*
790+
* Put cs into software controlled mode
791+
*/
792+
val = readl_relaxed(qspi->regs + REG_DIRECT_ACCESS);
793+
val |= DIRECT_ACCESS_EN_SSEL;
794+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
795+
735796
ret = devm_spi_register_controller(&pdev->dev, ctlr);
736797
if (ret)
737798
return dev_err_probe(&pdev->dev, ret,

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