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liuqdev/8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu

fsm

verilog

risc

• Verilog
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• 166
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• Updated
  on Jan 20, 2019

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