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[Sim] Implement the lowering logic from sim.proc.print to the SV dialect.
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1 parent 9ed5229 commit 712394b

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‎lib/Conversion/SimToSV/SimToSV.cpp‎

Lines changed: 228 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
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#include "mlir/IR/Threading.h"
2727
#include "mlir/Pass/Pass.h"
2828
#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/RegionUtils.h"
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#define DEBUG_TYPE "lower-sim-to-sv"
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@@ -465,6 +466,229 @@ static bool moveOpsIntoIfdefGuardsAndProcesses(Operation *rootOp) {
465466
}
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467468
namespace {
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static LogicalResult emitLoweringError(Location loc, const Twine &reason) {
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mlir::emitError(loc) << "cannot lower 'sim.proc.print' to sv.write: "
472+
<< reason;
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return failure();
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}
475+
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static void appendLiteralToFWriteFormat(SmallString<128> &formatString,
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StringRef literal) {
478+
for (char ch : literal) {
479+
if (ch == '%')
480+
formatString += "%%";
481+
else
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formatString.push_back(ch);
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}
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}
485+
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static LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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uint8_t paddingChar,
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std::optional<int32_t> width,
490+
char spec) {
491+
formatString.push_back('%');
492+
if (isLeftAligned)
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formatString.push_back('-');
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// SystemVerilog formatting only has built-in support for '0' and ' '. Keep
496+
// this lowering strict to avoid silently changing formatting semantics.
497+
if (paddingChar == '0')
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formatString.push_back('0');
499+
else if (paddingChar != ' ')
500+
return failure();
501+
502+
if (width.has_value())
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formatString += std::to_string(width.value());
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formatString.push_back(spec);
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return success();
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}
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static void appendFloatSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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std::optional<int32_t> fieldWidth,
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int32_t fracDigits, char spec) {
513+
formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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if (fieldWidth.has_value())
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formatString += std::to_string(fieldWidth.value());
518+
formatString.push_back('.');
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formatString += std::to_string(fracDigits);
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formatString.push_back(spec);
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}
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static LogicalResult
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getFlattenedFormatFragments(Value input, SmallVectorImpl<Value> &fragments) {
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if (auto concat = input.getDefiningOp<FormatStringConcatOp>()) {
526+
if (failed(concat.getFlattenedInputs(fragments)))
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return emitLoweringError(input.getLoc(),
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"cyclic sim.fmt.concat is unsupported");
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return success();
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}
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fragments.push_back(input);
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return success();
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}
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static LogicalResult
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appendFormatFragmentToFWrite(Value fragment, SmallString<128> &formatString,
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SmallVectorImpl<Value> &args, OpBuilder &builder) {
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Operation *fragmentOp = fragment.getDefiningOp();
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if (!fragmentOp)
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return emitLoweringError(fragment.getLoc(),
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"block argument format strings are unsupported as "
543+
"sim.proc.print input");
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return TypeSwitch<Operation *, LogicalResult>(fragmentOp)
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.Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
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appendLiteralToFWriteFormat(formatString, literal.getLiteral());
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return success();
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})
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.Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
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formatString += hierPath.getUseEscapes() ? "%M" : "%m";
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return success();
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})
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.Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
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formatString += "%c";
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'd'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.dec only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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// Match sim.fmt.dec signedness semantics explicitly in SV.
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if (fmt.getIsSigned()) {
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auto signedValue = sv::SystemFunctionOp::create(
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builder, fmt.getLoc(), fmt.getValue().getType(), "signed",
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ValueRange{fmt.getValue()});
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args.push_back(signedValue);
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} else {
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auto unsignedValue = sv::SystemFunctionOp::create(
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builder, fmt.getLoc(), fmt.getValue().getType(), "unsigned",
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ValueRange{fmt.getValue()});
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args.push_back(unsignedValue);
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}
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return success();
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})
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.Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(
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formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
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fmt.getSpecifierWidth(),
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fmt.getIsHexUppercase() ? 'X' : 'x'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.hex only supports paddingChar 32 (' ') "
588+
"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'o'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.oct only supports paddingChar 32 (' ') "
599+
"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'b'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.bin only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
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args.push_back(fmt.getValue());
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return success();
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})
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.Default([&](auto unsupportedOp) {
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return emitLoweringError(unsupportedOp->getLoc(),
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Twine("unsupported format fragment '") +
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unsupportedOp->getName().getStringRef() +
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"'");
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});
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}
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static LogicalResult foldFormatStringToFWrite(Value input,
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SmallString<128> &formatString,
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SmallVectorImpl<Value> &args,
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OpBuilder &builder) {
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SmallVector<Value, 8> fragments;
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if (failed(getFlattenedFormatFragments(input, fragments)))
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return failure();
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for (auto fragment : fragments)
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if (failed(appendFormatFragmentToFWrite(fragment, formatString, args,
650+
builder)))
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return failure();
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return success();
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}
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LogicalResult lowerPrintFormattedProcToSV(hw::HWModuleOp module) {
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SmallVector<PrintFormattedProcOp> printOps;
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module.walk([&](PrintFormattedProcOp op) { printOps.push_back(op); });
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llvm::SmallPtrSet<Operation *, 8> dceRoots;
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for (auto printOp : printOps) {
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OpBuilder builder(printOp);
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SmallString<128> formatString;
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SmallVector<Value> args;
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if (failed(foldFormatStringToFWrite(printOp.getInput(), formatString, args,
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builder))) {
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return failure();
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}
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auto stream = printOp.getStream();
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if (!stream) {
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// no stream is specified, emit sv.write.
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sv::WriteOp::create(builder, printOp.getLoc(), formatString, args);
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} else {
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// Stream-based printing is not supported yet.
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return printOp->emitError(
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"lowering 'sim.proc.print' with a stream is not supported yet");
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}
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auto *procRoot =
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printOp->getParentWithTrait<mlir::OpTrait::IsIsolatedFromAbove>();
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if (procRoot)
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dceRoots.insert(procRoot);
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printOp.erase();
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}
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mlir::IRRewriter rewriter(module);
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for (Operation *dceRoot : dceRoots)
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(void)mlir::runRegionDCE(rewriter, dceRoot->getRegions());
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return success();
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}
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struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
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void runOnOperation() override {
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auto circuit = getOperation();
@@ -478,6 +702,10 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
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479703
std::atomic<bool> usedSynthesisMacro = false;
480704
auto lowerModule = [&](hw::HWModuleOp module) {
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if (failed(lowerPrintFormattedProcToSV(module))) {
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return failure();
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}
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481709
if (moveOpsIntoIfdefGuardsAndProcesses(module))
482710
usedSynthesisMacro = true;
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‎test/Conversion/SimToSV/lower-print-formatted-proc-to-sv-errors.mlir‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
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// RUN: circt-opt --lower-sim-to-sv --split-input-file --verify-diagnostics %s
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hw.module @unsupported_padding_char(in %clk : i1, in %arg : i8) {
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hw.triggered posedge %clk (%arg) : i8 {
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^bb0(%arg_in : i8):
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%lit = sim.fmt.literal "bad="
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.write: sim.fmt.dec only supports paddingChar 32 (' ') or 48 ('0') for SystemVerilog lowering}}
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%bad = sim.fmt.dec %arg_in paddingChar 42 specifierWidth 2 : i8
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%msg = sim.fmt.concat (%lit, %bad)
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sim.proc.print %msg
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}
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}
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// -----
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hw.module @unsupported_input_block_argument(in %clk : i1, in %arg : !sim.fstring) {
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hw.triggered posedge %clk (%arg) : !sim.fstring {
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.write: block argument format strings are unsupported as sim.proc.print input}}
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^bb0(%arg_in : !sim.fstring):
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sim.proc.print %arg_in
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}
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}
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// -----
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hw.module @unsupported_stream_block_argument(
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in %clk : i1, in %stream : !sim.output_stream) {
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hw.triggered posedge %clk (%stream) : !sim.output_stream {
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^bb0(%stream_in : !sim.output_stream):
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%fmt = sim.fmt.literal "x"
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// expected-error @below {{lowering 'sim.proc.print' with a stream is not supported yet}}
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sim.proc.print %fmt to %stream_in
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}
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}
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// -----
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hw.module @unsupported_stream_from_get_file() {
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%literal = sim.fmt.literal "stream.log"
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// expected-error @below {{'sim.proc.print' op must not be in a non-procedural region}}
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sim.proc.print %literal
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}

‎test/Conversion/SimToSV/lower-print-formatted-proc-to-sv.mlir‎

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
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// RUN: circt-opt --lower-sim-to-sv %s | FileCheck %s
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// This pass assumes sim.proc.print is already in some procedural region.
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// It lowers both SV and non-SV procedural containers (e.g. hw.triggered).
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// CHECK-LABEL: hw.module @proc_print
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hw.module @proc_print(in %clk : i1, in %arg: i8) {
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// CHECK: hw.triggered posedge %clk
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hw.triggered posedge %clk (%arg) : i8 {
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^bb0(%arg_in : i8):
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%l0 = sim.fmt.literal "err: "
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%f0 = sim.fmt.hex %arg_in, isUpper true specifierWidth 2 : i8
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%l1 = sim.fmt.literal " 100%"
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%msg = sim.fmt.concat (%l0, %f0, %l1)
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// CHECK: sv.write "err: %02X 100%%"
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sim.proc.print %msg
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}
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}
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// CHECK-LABEL: hw.module @all_format_fragments
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hw.module @all_format_fragments(
24+
in %clk : i1, in %ival : i16, in %ch : i8, in %fval : f64) {
25+
hw.triggered posedge %clk (%ival, %ch, %fval) : i16, i8, f64 {
26+
^bb0(%ival_in : i16, %ch_in : i8, %fval_in : f64):
27+
%i0 = sim.fmt.literal "dec="
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%f0 = sim.fmt.dec %ival_in specifierWidth 6 signed : i16
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%i1 = sim.fmt.literal " hex="
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%f1 = sim.fmt.hex %ival_in, isUpper true paddingChar 48 specifierWidth 4 : i16
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%i2 = sim.fmt.literal " oct="
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%f2 = sim.fmt.oct %ival_in isLeftAligned true specifierWidth 6 : i16
33+
%i3 = sim.fmt.literal " bin="
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%f3 = sim.fmt.bin %ival_in paddingChar 32 specifierWidth 8 : i16
35+
%i4 = sim.fmt.literal " char="
36+
%f4 = sim.fmt.char %ch_in : i8
37+
%i5 = sim.fmt.literal " exp="
38+
%f5 = sim.fmt.exp %fval_in fieldWidth 10 fracDigits 3 : f64
39+
%i6 = sim.fmt.literal " flt="
40+
%f6 = sim.fmt.flt %fval_in isLeftAligned true fieldWidth 8 fracDigits 2 : f64
41+
%i7 = sim.fmt.literal " gen="
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%f7 = sim.fmt.gen %fval_in fracDigits 4 : f64
43+
%i8 = sim.fmt.literal " path="
44+
%f8 = sim.fmt.hier_path
45+
%i9 = sim.fmt.literal " esc="
46+
%f9 = sim.fmt.hier_path escaped
47+
%i10 = sim.fmt.literal " pct=%"
48+
%msg = sim.fmt.concat (%i0, %f0, %i1, %f1, %i2, %f2, %i3, %f3, %i4, %f4, %i5, %f5, %i6, %f6, %i7, %f7, %i8, %f8, %i9, %f9, %i10)
49+
50+
// CHECK: ^bb0(%[[IVAL:.+]]: i16, %[[CH:.+]]: i8, %[[FVAL:.+]]: f64):
51+
// CHECK-NEXT: %[[SIGNED:.+]] = sv.system "signed"(%[[IVAL]]) : (i16) -> i16
52+
// CHECK-NEXT: sv.write "dec=%6d hex=%04X oct=%-06o bin=%8b char=%c exp=%10.3e flt=%-8.2f gen=%.4g path=%m esc=%M pct=%%"(%[[SIGNED]], %[[IVAL]], %[[IVAL]], %[[IVAL]], %[[CH]], %[[FVAL]], %[[FVAL]], %[[FVAL]]) : i16, i16, i16, i16, i8, f64, f64, f64
53+
sim.proc.print %msg
54+
}
55+
}
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57+
// CHECK-LABEL: hw.module @nested_concat_order
58+
hw.module @nested_concat_order(in %clk : i1, in %lhs : i8, in %rhs : i8) {
59+
hw.triggered posedge %clk (%lhs, %rhs) : i8, i8 {
60+
^bb0(%lhs_in : i8, %rhs_in : i8):
61+
%l0 = sim.fmt.literal "L="
62+
%l1 = sim.fmt.literal ", R="
63+
%d0 = sim.fmt.dec %lhs_in specifierWidth 3 : i8
64+
%h0 = sim.fmt.hex %rhs_in, isUpper false specifierWidth 2 : i8
65+
66+
%c0 = sim.fmt.concat (%l0, %d0)
67+
%c1 = sim.fmt.concat (%c0, %l1)
68+
%c2 = sim.fmt.concat (%c1, %h0)
69+
70+
// CHECK: ^bb0(%[[LHS:.+]]: i8, %[[RHS:.+]]: i8):
71+
// CHECK-NEXT: %[[UNSIGNED:.+]] = sv.system "unsigned"(%[[LHS]]) : (i8) -> i8
72+
// CHECK-NEXT: sv.write "L=%3d, R=%02x"(%[[UNSIGNED]], %[[RHS]]) : i8, i8
73+
sim.proc.print %c2
74+
}
75+
}
76+
77+
// CHECK-LABEL: hw.module @dce_uses_outer_procedural_root
78+
hw.module @dce_uses_outer_procedural_root(
79+
in %clk : i1, in %cond : i1, in %val : i8) {
80+
// CHECK: hw.triggered posedge %clk
81+
hw.triggered posedge %clk (%cond, %val) : i1, i8 {
82+
^bb0(%cond_in : i1, %val_in : i8):
83+
%lit = sim.fmt.literal "v="
84+
%fmt = sim.fmt.dec %val_in : i8
85+
%msg = sim.fmt.concat (%lit, %fmt)
86+
// CHECK: ^bb0(%[[COND:.+]]: i1, %[[VAL:.+]]: i8):
87+
// CHECK: scf.if %[[COND]] {
88+
// CHECK: %[[UNSIGNED:.+]] = sv.system "unsigned"(%[[VAL]]) : (i8) -> i8
89+
// CHECK-NEXT: sv.write "v=%d"(%[[UNSIGNED]]) : i8
90+
scf.if %cond_in {
91+
sim.proc.print %msg
92+
}
93+
}
94+
}
95+
96+
hw.module @triggered_print(in %clk : i1) {
97+
// CHECK-LABEL: hw.module @triggered_print
98+
hw.triggered posedge %clk {
99+
%lit = sim.fmt.literal "hello"
100+
// CHECK: sv.write "hello"
101+
sim.proc.print %lit
102+
}
103+
}

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