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[Sim] Implement the lowering logic from sim.proc.print to the SV dialect.
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‎lib/Conversion/SimToSV/CMakeLists.txt‎

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add_circt_conversion_library(CIRCTSimToSV
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SimToSV.cpp
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LowerPrintFormattedProcToSV.cpp
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DEPENDS
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CIRCTConversionPassIncGen

‎lib/Conversion/SimToSV/LowerPrintFormattedProcToSV.cpp‎

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//===- LowerPrintFormattedProcToSV.cpp - Lower proc.print to sv.write ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass lowers sim.proc.print to sv.write.
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//
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// Precondition: sim.proc.print must already be in some procedural region.
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// This pass lowers sim.proc.print in both SV and non-SV procedural containers
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// (e.g. sv.initial/sv.always/sv.alwayscomb/sv.alwaysff/hw.triggered).
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//
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//===----------------------------------------------------------------------===//
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#include "SimToSVInternal.h"
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/SV/SVOps.h"
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#include "circt/Dialect/Sim/SimOps.h"
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#include "circt/Support/ProceduralRegionTrait.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Transforms/RegionUtils.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#define DEBUG_TYPE "sim-lower-print-formatted-proc-to-sv"
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namespace circt {
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#define GEN_PASS_DEF_LOWERPRINTFORMATTEDPROCTOSV
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#include "circt/Conversion/Passes.h.inc"
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} // namespace circt
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using namespace circt;
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using namespace sim;
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namespace {
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static LogicalResult emitLoweringError(Location loc, const Twine &reason) {
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mlir::emitError(loc) << "cannot lower 'sim.proc.print' to sv.write: "
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<< reason;
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return failure();
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}
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static void appendLiteralToFWriteFormat(SmallString<128> &formatString,
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StringRef literal) {
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for (char ch : literal) {
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if (ch == '%')
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formatString += "%%";
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else
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formatString.push_back(ch);
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}
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}
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static LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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uint8_t paddingChar,
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std::optional<int32_t> width,
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char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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// SystemVerilog formatting only has built-in support for '0' and ' '. Keep
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// this lowering strict to avoid silently changing formatting semantics.
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if (paddingChar == '0') {
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formatString.push_back('0');
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} else if (paddingChar != ' ') {
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return failure();
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}
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if (width.has_value())
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formatString += std::to_string(width.value());
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formatString.push_back(spec);
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return success();
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}
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static void appendFloatSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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std::optional<int32_t> fieldWidth,
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int32_t fracDigits, char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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if (fieldWidth.has_value())
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formatString += std::to_string(fieldWidth.value());
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formatString.push_back('.');
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formatString += std::to_string(fracDigits);
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formatString.push_back(spec);
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}
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static LogicalResult
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getFlattenedFormatFragments(Value input, SmallVectorImpl<Value> &fragments) {
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if (auto concat = input.getDefiningOp<FormatStringConcatOp>()) {
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if (failed(concat.getFlattenedInputs(fragments)))
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return emitLoweringError(input.getLoc(),
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"cyclic sim.fmt.concat is unsupported");
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return success();
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}
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fragments.push_back(input);
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return success();
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}
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static LogicalResult
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appendFormatFragmentToFWrite(Value fragment, SmallString<128> &formatString,
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SmallVectorImpl<Value> &args, OpBuilder &builder) {
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Operation *fragmentOp = fragment.getDefiningOp();
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if (!fragmentOp)
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return emitLoweringError(fragment.getLoc(),
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"block argument format strings are unsupported as "
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"sim.proc.print input");
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return TypeSwitch<Operation *, LogicalResult>(fragmentOp)
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.Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
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appendLiteralToFWriteFormat(formatString, literal.getLiteral());
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return success();
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})
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.Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
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formatString += hierPath.getUseEscapes() ? "%M" : "%m";
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return success();
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})
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.Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
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formatString += "%c";
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'd'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.dec only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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// Match sim.fmt.dec signedness semantics explicitly in SV.
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if (fmt.getIsSigned()) {
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auto signedValue = sv::SystemFunctionOp::create(
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builder, fmt.getLoc(), fmt.getValue().getType(), "signed",
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ValueRange{fmt.getValue()});
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args.push_back(signedValue);
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} else {
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args.push_back(fmt.getValue());
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}
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return success();
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})
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.Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(
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formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
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fmt.getSpecifierWidth(),
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fmt.getIsHexUppercase() ? 'X' : 'x'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.hex only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'o'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.oct only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'b'))) {
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return emitLoweringError(
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fmt.getLoc(), "sim.fmt.bin only supports paddingChar 32 (' ') "
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"or 48 ('0') for SystemVerilog lowering");
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
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args.push_back(fmt.getValue());
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return success();
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})
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.Default([&](auto unsupportedOp) {
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return emitLoweringError(unsupportedOp->getLoc(),
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Twine("unsupported format fragment '") +
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unsupportedOp->getName().getStringRef() +
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"'");
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});
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}
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static LogicalResult foldFormatStringToFWrite(Value input,
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SmallString<128> &formatString,
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SmallVectorImpl<Value> &args,
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OpBuilder &builder) {
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SmallVector<Value, 8> fragments;
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if (failed(getFlattenedFormatFragments(input, fragments)))
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return failure();
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for (auto fragment : fragments)
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if (failed(appendFormatFragmentToFWrite(fragment, formatString, args,
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builder)))
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return failure();
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return success();
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}
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static Operation *findProceduralRoot(Operation *op) {
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Operation *procRoot = nullptr;
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for (Operation *ancestor = op->getParentOp(); ancestor;
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ancestor = ancestor->getParentOp()) {
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if (ancestor->hasTrait<ProceduralRegion>())
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procRoot = ancestor;
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}
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return procRoot;
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}
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} // namespace
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LogicalResult circt::sim::lowerPrintFormattedProcToSV(hw::HWModuleOp module) {
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SmallVector<PrintFormattedProcOp> printOps;
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module.walk([&](PrintFormattedProcOp op) { printOps.push_back(op); });
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llvm::SmallPtrSet<Operation *, 8> dceRoots;
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for (auto printOp : printOps) {
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OpBuilder builder(printOp);
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SmallString<128> formatString;
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SmallVector<Value> args;
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if (failed(foldFormatStringToFWrite(printOp.getInput(), formatString, args,
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builder))) {
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return failure();
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}
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auto stream = printOp.getStream();
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if (!stream) {
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// no stream is specified, emit sv.write.
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sv::WriteOp::create(builder, printOp.getLoc(), formatString, args);
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} else {
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// Stream-based printing is not supported yet.
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return printOp->emitError(
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"lowering 'sim.proc.print' with a stream is not supported yet");
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}
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auto *procRoot = findProceduralRoot(printOp);
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if (procRoot)
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dceRoots.insert(procRoot);
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printOp.erase();
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}
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mlir::IRRewriter rewriter(module);
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for (Operation *dceRoot : dceRoots)
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(void)mlir::runRegionDCE(rewriter, dceRoot->getRegions());
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return success();
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}

‎lib/Conversion/SimToSV/SimToSV.cpp‎

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//===----------------------------------------------------------------------===//
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#include "circt/Conversion/SimToSV.h"
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#include "SimToSVInternal.h"
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#include "circt/Dialect/Comb/CombOps.h"
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#include "circt/Dialect/Emit/EmitOps.h"
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#include "circt/Dialect/HW/HWOps.h"
@@ -478,6 +479,10 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
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std::atomic<bool> usedSynthesisMacro = false;
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auto lowerModule = [&](hw::HWModuleOp module) {
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if (failed(lowerPrintFormattedProcToSV(module))) {
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return failure();
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}
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if (moveOpsIntoIfdefGuardsAndProcesses(module))
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usedSynthesisMacro = true;
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‎lib/Conversion/SimToSV/SimToSVInternal.h‎

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//===- SimToSVInternal.h - Internal implementation details ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef CONVERSION_SIMTOSV_SIMTOSVINTERNALS_H
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#define CONVERSION_SIMTOSV_SIMTOSVINTERNALS_H
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Support/LLVM.h"
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namespace circt {
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namespace sim {
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LogicalResult lowerPrintFormattedProcToSV(hw::HWModuleOp module);
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} // namespace sim
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} // namespace circt
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#endif // CONVERSION_SIMTOSV_SIMTOSVINTERNALS_H

‎test/Conversion/SimToSV/lower-print-formatted-proc-to-sv-errors.mlir‎

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// RUN: circt-opt --lower-sim-to-sv --split-input-file --verify-diagnostics %s
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hw.module @unsupported_padding_char(in %arg : i8) {
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sv.initial {
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%lit = sim.fmt.literal "bad="
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.write: sim.fmt.dec only supports paddingChar 32 (' ') or 48 ('0') for SystemVerilog lowering}}
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%bad = sim.fmt.dec %arg paddingChar 42 specifierWidth 2 : i8
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%msg = sim.fmt.concat (%lit, %bad)
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sim.proc.print %msg
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}
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}
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// -----
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.write: block argument format strings are unsupported as sim.proc.print input}}
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hw.module @unsupported_input_block_argument(in %arg : !sim.fstring) {
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sv.initial {
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sim.proc.print %arg
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}
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}
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// -----
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hw.module @unsupported_stream_block_argument(
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in %stream : !sim.output_stream) {
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sv.initial {
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%fmt = sim.fmt.literal "x"
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// expected-error @below {{lowering 'sim.proc.print' with a stream is not supported yet}}
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sim.proc.print %fmt to %stream
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}
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}
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// -----
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hw.module @unsupported_stream_from_get_file() {
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%literal = sim.fmt.literal "stream.log"
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// expected-error @below {{'sim.proc.print' op must not be in a non-procedural region}}
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sim.proc.print %literal
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}

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