[ImportVerilog] Use Slang's LRM clock inference for assertion calls#10370
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AI-assisted-by: Claude Code: claude-sonnet-4.6
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fabianschuiki
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May 4, 2026
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This allows us to connect explicit clocks to sampled value functions by using the LRM clock inference that Slang can do automatically. There are a few cases this doesn't handle yet that I've left for follow-ups - negedge should be quite easy, though supporting an event list might be a bit trickier (since we can't just use the OR of the triggers in case one of them goes low as another goes high). Note that this shouldn't cause a change in sv-tests since LTLToCore doesn't try to legalize certain LTL ops.
Once this is merged, we can think about also making the clock operand of ltl.past non-optional - I believe this is the only existing place where PastOps are created without a clock operand.
AI-assisted-by: Claude Code: claude-sonnet-4.6