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Pull requests: llvm/circt

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269 Open 7,864 Closed
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Pull requests list

[Arc] Move storage size attribute from type to owning op Arc Involving the `arc` dialect
#10767 opened Jul 3, 2026 by fzi-hielscher Contributor Loading…
1
[FIRRTL] Add --disable-line-wrap flag to emitter
#10765 opened Jul 3, 2026 by TaoBi22 Contributor Loading…
1
[Sim][MooreToCore][SimToSV] Add sim.string.format_to_string and lower moore.fstring_to_string
#10764 opened Jul 2, 2026 by VecoMr Member Loading…
8
[FIRRTL][InferDomains] Add option to skip checking specific domains
#10763 opened Jul 2, 2026 by uenoku Member Loading…
1
[RTG] Replace immediate type with MLIR integer RTG Involving the `rtg` dialect
#10760 opened Jul 2, 2026 by maerhart Member Loading…
1
[Arc] Support observed values on llhd.wait in coroutine lowering Arc Involving the `arc` dialect
#10757 opened Jul 2, 2026 by fabianschuiki Contributor Loading…
3
Bump LLVM
#10756 opened Jul 2, 2026 by uenoku Member Loading…
1
[FSM] Eliminate mutually exclusive transition guards (#3577)
#10754 opened Jul 1, 2026 by arefinaa Loading…
2 tasks done
1
[circt-bmc] Add dbg.trace for BMC counterexample value tracking
#10747 opened Jul 1, 2026 by 5iri Contributor Loading…
4
[ImportVerilog][MooreToCore] Adds support for System Verilog real maths functions
#10746 opened Jun 30, 2026 by jpkirs Loading…
3
[Python] Fix ModuleLike.is_external for ops with no region
#10745 opened Jun 30, 2026 by uenoku Member Loading…
1
[FIRRTL] Add edge attribute to LTL clock intrinsic
#10744 opened Jun 29, 2026 by Clo91eaf Contributor Loading…
1
Adding support for the Verilog Real Math system as non synthesisable constructs
#10743 opened Jun 29, 2026 by jpkirs • Draft
[FIRRTL][Seq] Make register reset semantics explicit
#10742 opened Jun 28, 2026 by Clo91eaf Contributor • Draft
4
[RFC] Add Probe dialect prototype for HW-level probe modeling
#10741 opened Jun 27, 2026 by nanjo712 Contributor Loading…
20
[ExportVerilog] Fix enum case labels for anonymous enumerations
#10739 opened Jun 26, 2026 by ConvolutedDog Loading…
1
[FIRRTL] Add LTLClockedDelayIntrinsicOp in FIRRTL
#10737 opened Jun 26, 2026 by Clo91eaf Contributor • Draft
3
[Synth] Use LinearTimingArcAttr sensitivity in TechMappper
#10735 opened Jun 25, 2026 by okekayode Contributor Loading…
1
[TableGen] Make dialect TableGen files self-contained
#10724 opened Jun 24, 2026 by ConvolutedDog Loading…
2
[MooreToCore] Fold zero-width unpacked array comparisons
#10713 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Skip bodies for pure virtual non-void methods
#10709 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[MooreToCore] Lower packed aggregate extraction forms
#10708 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Lower aggregate storage and value materialization
#10707 opened Jun 22, 2026 by AmurG Contributor Loading…
1
[ImportVerilog] Normalize aggregate source operands
#10701 opened Jun 22, 2026 by AmurG Contributor Loading…
2
[MooreToCore] Handle empty array slices and creation
#10697 opened Jun 22, 2026 by AmurG Contributor Loading…
1
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