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[X86] Check useBWIRegs() instead of hasBWI() before creating x86_avx512_psad_bw_512 intrinsic. (#201167)
Need to check that 512-bit vectors are enabled before using a 512-bit intrinsic.
1 parent 9b92e0f commit 162076f

2 files changed

Lines changed: 237 additions & 10 deletions

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‎llvm/lib/Target/X86/X86PartialReduction.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,7 @@ bool X86PartialReduction::trySADReplacement(Instruction *Op) {
271271

272272
unsigned IntrinsicNumElts;
273273
Intrinsic::ID IID;
274-
if (ST->hasBWI() && NumElts >= 64) {
274+
if (ST->useBWIRegs() && NumElts >= 64) {
275275
IID = Intrinsic::x86_avx512_psad_bw_512;
276276
IntrinsicNumElts = 64;
277277
} else if (ST->hasAVX2() && NumElts >= 32) {

‎llvm/test/CodeGen/X86/sad.ll‎

Lines changed: 236 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
44
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
55
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
6-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
6+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
77

88
@a = dso_local global [1024 x i8] zeroinitializer, align 16
99
@b = dso_local global [1024 x i8] zeroinitializer, align 16
@@ -509,14 +509,241 @@ middle.block:
509509
ret i32 %12
510510
}
511511

512+
; Make sure we don't crash if 512-bit vectors aren't enabled.
513+
define i32 @sad_avx64i8_prefer_256() nounwind "min-legal-vector-width"="256" "prefer-vector-width"="256" {
514+
; SSE2-LABEL: sad_avx64i8_prefer_256:
515+
; SSE2: # %bb.0: # %entry
516+
; SSE2-NEXT: pxor %xmm4, %xmm4
517+
; SSE2-NEXT: movq $-1024, %rax # imm = 0xFC00
518+
; SSE2-NEXT: pxor %xmm0, %xmm0
519+
; SSE2-NEXT: pxor %xmm3, %xmm3
520+
; SSE2-NEXT: pxor %xmm2, %xmm2
521+
; SSE2-NEXT: pxor %xmm1, %xmm1
522+
; SSE2-NEXT: .p2align 4
523+
; SSE2-NEXT: .LBB3_1: # %vector.body
524+
; SSE2-NEXT: # =>This Inner Loop Header: Depth=1
525+
; SSE2-NEXT: movdqa a+1024(%rax), %xmm5
526+
; SSE2-NEXT: psadbw b+1024(%rax), %xmm5
527+
; SSE2-NEXT: paddd %xmm5, %xmm0
528+
; SSE2-NEXT: movdqa a+1040(%rax), %xmm5
529+
; SSE2-NEXT: psadbw b+1040(%rax), %xmm5
530+
; SSE2-NEXT: paddd %xmm5, %xmm3
531+
; SSE2-NEXT: movdqa a+1056(%rax), %xmm5
532+
; SSE2-NEXT: psadbw b+1056(%rax), %xmm5
533+
; SSE2-NEXT: paddd %xmm5, %xmm2
534+
; SSE2-NEXT: movdqa a+1072(%rax), %xmm5
535+
; SSE2-NEXT: psadbw b+1072(%rax), %xmm5
536+
; SSE2-NEXT: paddd %xmm5, %xmm1
537+
; SSE2-NEXT: addq $64, %rax
538+
; SSE2-NEXT: jne .LBB3_1
539+
; SSE2-NEXT: # %bb.2: # %middle.block
540+
; SSE2-NEXT: paddd %xmm4, %xmm2
541+
; SSE2-NEXT: pxor %xmm5, %xmm5
542+
; SSE2-NEXT: paddd %xmm5, %xmm5
543+
; SSE2-NEXT: paddd %xmm4, %xmm0
544+
; SSE2-NEXT: paddd %xmm4, %xmm1
545+
; SSE2-NEXT: paddd %xmm4, %xmm3
546+
; SSE2-NEXT: paddd %xmm5, %xmm3
547+
; SSE2-NEXT: paddd %xmm5, %xmm1
548+
; SSE2-NEXT: paddd %xmm3, %xmm1
549+
; SSE2-NEXT: paddd %xmm5, %xmm0
550+
; SSE2-NEXT: paddd %xmm2, %xmm5
551+
; SSE2-NEXT: paddd %xmm0, %xmm5
552+
; SSE2-NEXT: paddd %xmm1, %xmm5
553+
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[2,3,2,3]
554+
; SSE2-NEXT: paddd %xmm5, %xmm0
555+
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
556+
; SSE2-NEXT: paddd %xmm0, %xmm1
557+
; SSE2-NEXT: movd %xmm1, %eax
558+
; SSE2-NEXT: retq
559+
;
560+
; AVX1-LABEL: sad_avx64i8_prefer_256:
561+
; AVX1: # %bb.0: # %entry
562+
; AVX1-NEXT: vpxor %xmm0, %xmm0, %xmm0
563+
; AVX1-NEXT: movq $-1024, %rax # imm = 0xFC00
564+
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
565+
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
566+
; AVX1-NEXT: .p2align 4
567+
; AVX1-NEXT: .LBB3_1: # %vector.body
568+
; AVX1-NEXT: # =>This Inner Loop Header: Depth=1
569+
; AVX1-NEXT: vmovdqa a+1024(%rax), %xmm3
570+
; AVX1-NEXT: vpsadbw b+1024(%rax), %xmm3, %xmm3
571+
; AVX1-NEXT: vmovdqa a+1040(%rax), %xmm4
572+
; AVX1-NEXT: vpsadbw b+1040(%rax), %xmm4, %xmm4
573+
; AVX1-NEXT: vmovdqa a+1056(%rax), %xmm5
574+
; AVX1-NEXT: vpsadbw b+1056(%rax), %xmm5, %xmm5
575+
; AVX1-NEXT: vmovdqa a+1072(%rax), %xmm6
576+
; AVX1-NEXT: vpsadbw b+1072(%rax), %xmm6, %xmm6
577+
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm7
578+
; AVX1-NEXT: vpaddd %xmm7, %xmm6, %xmm6
579+
; AVX1-NEXT: vpaddd %xmm1, %xmm5, %xmm1
580+
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm1, %ymm1
581+
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5
582+
; AVX1-NEXT: vpaddd %xmm5, %xmm4, %xmm4
583+
; AVX1-NEXT: vpaddd %xmm2, %xmm3, %xmm2
584+
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
585+
; AVX1-NEXT: addq $64, %rax
586+
; AVX1-NEXT: jne .LBB3_1
587+
; AVX1-NEXT: # %bb.2: # %middle.block
588+
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
589+
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
590+
; AVX1-NEXT: vpaddd %xmm4, %xmm4, %xmm5
591+
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
592+
; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm7
593+
; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm8
594+
; AVX1-NEXT: vpaddd %xmm0, %xmm8, %xmm8
595+
; AVX1-NEXT: vpaddd %xmm2, %xmm8, %xmm2
596+
; AVX1-NEXT: vpaddd %xmm7, %xmm0, %xmm0
597+
; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0
598+
; AVX1-NEXT: vpaddd %xmm0, %xmm2, %xmm0
599+
; AVX1-NEXT: vpaddd %xmm5, %xmm4, %xmm1
600+
; AVX1-NEXT: vpaddd %xmm1, %xmm6, %xmm2
601+
; AVX1-NEXT: vpaddd %xmm1, %xmm3, %xmm1
602+
; AVX1-NEXT: vpaddd %xmm1, %xmm2, %xmm1
603+
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
604+
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
605+
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
606+
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
607+
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
608+
; AVX1-NEXT: vmovd %xmm0, %eax
609+
; AVX1-NEXT: vzeroupper
610+
; AVX1-NEXT: retq
611+
;
612+
; AVX2-LABEL: sad_avx64i8_prefer_256:
613+
; AVX2: # %bb.0: # %entry
614+
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
615+
; AVX2-NEXT: movq $-1024, %rax # imm = 0xFC00
616+
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
617+
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
618+
; AVX2-NEXT: .p2align 4
619+
; AVX2-NEXT: .LBB3_1: # %vector.body
620+
; AVX2-NEXT: # =>This Inner Loop Header: Depth=1
621+
; AVX2-NEXT: vmovdqa a+1024(%rax), %ymm3
622+
; AVX2-NEXT: vpsadbw b+1024(%rax), %ymm3, %ymm3
623+
; AVX2-NEXT: vpaddd %ymm1, %ymm3, %ymm1
624+
; AVX2-NEXT: vmovdqa a+1056(%rax), %ymm3
625+
; AVX2-NEXT: vpsadbw b+1056(%rax), %ymm3, %ymm3
626+
; AVX2-NEXT: vpaddd %ymm2, %ymm3, %ymm2
627+
; AVX2-NEXT: addq $64, %rax
628+
; AVX2-NEXT: jne .LBB3_1
629+
; AVX2-NEXT: # %bb.2: # %middle.block
630+
; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm2
631+
; AVX2-NEXT: vpaddd %ymm0, %ymm0, %ymm3
632+
; AVX2-NEXT: vpaddd %ymm0, %ymm1, %ymm0
633+
; AVX2-NEXT: vpaddd %ymm3, %ymm0, %ymm0
634+
; AVX2-NEXT: vpaddd %ymm3, %ymm2, %ymm1
635+
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
636+
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
637+
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
638+
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
639+
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
640+
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
641+
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
642+
; AVX2-NEXT: vmovd %xmm0, %eax
643+
; AVX2-NEXT: vzeroupper
644+
; AVX2-NEXT: retq
645+
;
646+
; AVX512F-LABEL: sad_avx64i8_prefer_256:
647+
; AVX512F: # %bb.0: # %entry
648+
; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0
649+
; AVX512F-NEXT: movq $-1024, %rax # imm = 0xFC00
650+
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
651+
; AVX512F-NEXT: .p2align 4
652+
; AVX512F-NEXT: .LBB3_1: # %vector.body
653+
; AVX512F-NEXT: # =>This Inner Loop Header: Depth=1
654+
; AVX512F-NEXT: vmovdqa a+1024(%rax), %ymm2
655+
; AVX512F-NEXT: vpsadbw b+1024(%rax), %ymm2, %ymm2
656+
; AVX512F-NEXT: vmovdqa a+1056(%rax), %ymm3
657+
; AVX512F-NEXT: vpsadbw b+1056(%rax), %ymm3, %ymm3
658+
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2
659+
; AVX512F-NEXT: vpaddd %zmm1, %zmm2, %zmm1
660+
; AVX512F-NEXT: addq $64, %rax
661+
; AVX512F-NEXT: jne .LBB3_1
662+
; AVX512F-NEXT: # %bb.2: # %middle.block
663+
; AVX512F-NEXT: vpaddd %zmm0, %zmm1, %zmm1
664+
; AVX512F-NEXT: vpaddd %zmm0, %zmm0, %zmm0
665+
; AVX512F-NEXT: vpaddd %zmm0, %zmm1, %zmm0
666+
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1
667+
; AVX512F-NEXT: vpaddd %zmm1, %zmm0, %zmm0
668+
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
669+
; AVX512F-NEXT: vpaddd %xmm1, %xmm0, %xmm0
670+
; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
671+
; AVX512F-NEXT: vpaddd %xmm1, %xmm0, %xmm0
672+
; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
673+
; AVX512F-NEXT: vpaddd %xmm1, %xmm0, %xmm0
674+
; AVX512F-NEXT: vmovd %xmm0, %eax
675+
; AVX512F-NEXT: vzeroupper
676+
; AVX512F-NEXT: retq
677+
;
678+
; AVX512BW-LABEL: sad_avx64i8_prefer_256:
679+
; AVX512BW: # %bb.0: # %entry
680+
; AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0
681+
; AVX512BW-NEXT: movq $-1024, %rax # imm = 0xFC00
682+
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
683+
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
684+
; AVX512BW-NEXT: .p2align 4
685+
; AVX512BW-NEXT: .LBB3_1: # %vector.body
686+
; AVX512BW-NEXT: # =>This Inner Loop Header: Depth=1
687+
; AVX512BW-NEXT: vmovdqa a+1024(%rax), %ymm3
688+
; AVX512BW-NEXT: vpsadbw b+1024(%rax), %ymm3, %ymm3
689+
; AVX512BW-NEXT: vpaddd %ymm1, %ymm3, %ymm1
690+
; AVX512BW-NEXT: vmovdqa a+1056(%rax), %ymm3
691+
; AVX512BW-NEXT: vpsadbw b+1056(%rax), %ymm3, %ymm3
692+
; AVX512BW-NEXT: vpaddd %ymm2, %ymm3, %ymm2
693+
; AVX512BW-NEXT: addq $64, %rax
694+
; AVX512BW-NEXT: jne .LBB3_1
695+
; AVX512BW-NEXT: # %bb.2: # %middle.block
696+
; AVX512BW-NEXT: vpaddd %ymm0, %ymm2, %ymm2
697+
; AVX512BW-NEXT: vpaddd %ymm0, %ymm0, %ymm3
698+
; AVX512BW-NEXT: vpaddd %ymm0, %ymm1, %ymm0
699+
; AVX512BW-NEXT: vpaddd %ymm3, %ymm0, %ymm0
700+
; AVX512BW-NEXT: vpaddd %ymm3, %ymm2, %ymm1
701+
; AVX512BW-NEXT: vpaddd %ymm1, %ymm0, %ymm0
702+
; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1
703+
; AVX512BW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
704+
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
705+
; AVX512BW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
706+
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
707+
; AVX512BW-NEXT: vpaddd %xmm1, %xmm0, %xmm0
708+
; AVX512BW-NEXT: vmovd %xmm0, %eax
709+
; AVX512BW-NEXT: vzeroupper
710+
; AVX512BW-NEXT: retq
711+
entry:
712+
br label %vector.body
713+
714+
vector.body:
715+
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
716+
%vec.phi = phi <64 x i32> [ zeroinitializer, %entry ], [ %10, %vector.body ]
717+
%0 = getelementptr inbounds [1024 x i8], ptr @a, i64 0, i64 %index
718+
%1 = bitcast ptr %0 to ptr
719+
%wide.load = load <64 x i8>, ptr %1, align 64
720+
%2 = zext <64 x i8> %wide.load to <64 x i32>
721+
%3 = getelementptr inbounds [1024 x i8], ptr @b, i64 0, i64 %index
722+
%4 = bitcast ptr %3 to ptr
723+
%wide.load1 = load <64 x i8>, ptr %4, align 64
724+
%5 = zext <64 x i8> %wide.load1 to <64 x i32>
725+
%6 = sub nsw <64 x i32> %2, %5
726+
%7 = icmp sgt <64 x i32> %6, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
727+
%8 = sub nsw <64 x i32> zeroinitializer, %6
728+
%9 = select <64 x i1> %7, <64 x i32> %6, <64 x i32> %8
729+
%10 = add nsw <64 x i32> %9, %vec.phi
730+
%index.next = add i64 %index, 64
731+
%11 = icmp eq i64 %index.next, 1024
732+
br i1 %11, label %middle.block, label %vector.body
733+
734+
middle.block:
735+
%12 = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %10)
736+
ret i32 %12
737+
}
738+
512739
define dso_local i32 @sad_2i8() nounwind {
513740
; SSE2-LABEL: sad_2i8:
514741
; SSE2: # %bb.0: # %entry
515742
; SSE2-NEXT: pxor %xmm0, %xmm0
516743
; SSE2-NEXT: movq $-1024, %rax # imm = 0xFC00
517744
; SSE2-NEXT: movd {{.*#+}} xmm1 = [65535,0,0,0]
518745
; SSE2-NEXT: .p2align 4
519-
; SSE2-NEXT: .LBB3_1: # %vector.body
746+
; SSE2-NEXT: .LBB4_1: # %vector.body
520747
; SSE2-NEXT: # =>This Inner Loop Header: Depth=1
521748
; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
522749
; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
@@ -525,7 +752,7 @@ define dso_local i32 @sad_2i8() nounwind {
525752
; SSE2-NEXT: psadbw %xmm2, %xmm3
526753
; SSE2-NEXT: paddd %xmm3, %xmm0
527754
; SSE2-NEXT: addq $2, %rax
528-
; SSE2-NEXT: jne .LBB3_1
755+
; SSE2-NEXT: jne .LBB4_1
529756
; SSE2-NEXT: # %bb.2: # %middle.block
530757
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
531758
; SSE2-NEXT: paddd %xmm0, %xmm1
@@ -538,7 +765,7 @@ define dso_local i32 @sad_2i8() nounwind {
538765
; AVX-NEXT: movq $-1024, %rax # imm = 0xFC00
539766
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
540767
; AVX-NEXT: .p2align 4
541-
; AVX-NEXT: .LBB3_1: # %vector.body
768+
; AVX-NEXT: .LBB4_1: # %vector.body
542769
; AVX-NEXT: # =>This Inner Loop Header: Depth=1
543770
; AVX-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
544771
; AVX-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero
@@ -547,7 +774,7 @@ define dso_local i32 @sad_2i8() nounwind {
547774
; AVX-NEXT: vpsadbw %xmm3, %xmm2, %xmm2
548775
; AVX-NEXT: vpaddd %xmm1, %xmm2, %xmm1
549776
; AVX-NEXT: addq $2, %rax
550-
; AVX-NEXT: jne .LBB3_1
777+
; AVX-NEXT: jne .LBB4_1
551778
; AVX-NEXT: # %bb.2: # %middle.block
552779
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
553780
; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
@@ -587,14 +814,14 @@ define dso_local i32 @sad_4i8() nounwind {
587814
; SSE2-NEXT: pxor %xmm0, %xmm0
588815
; SSE2-NEXT: movq $-1024, %rax # imm = 0xFC00
589816
; SSE2-NEXT: .p2align 4
590-
; SSE2-NEXT: .LBB4_1: # %vector.body
817+
; SSE2-NEXT: .LBB5_1: # %vector.body
591818
; SSE2-NEXT: # =>This Inner Loop Header: Depth=1
592819
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
593820
; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
594821
; SSE2-NEXT: psadbw %xmm1, %xmm2
595822
; SSE2-NEXT: paddd %xmm2, %xmm0
596823
; SSE2-NEXT: addq $4, %rax
597-
; SSE2-NEXT: jne .LBB4_1
824+
; SSE2-NEXT: jne .LBB5_1
598825
; SSE2-NEXT: # %bb.2: # %middle.block
599826
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
600827
; SSE2-NEXT: paddd %xmm0, %xmm1
@@ -608,14 +835,14 @@ define dso_local i32 @sad_4i8() nounwind {
608835
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
609836
; AVX-NEXT: movq $-1024, %rax # imm = 0xFC00
610837
; AVX-NEXT: .p2align 4
611-
; AVX-NEXT: .LBB4_1: # %vector.body
838+
; AVX-NEXT: .LBB5_1: # %vector.body
612839
; AVX-NEXT: # =>This Inner Loop Header: Depth=1
613840
; AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
614841
; AVX-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
615842
; AVX-NEXT: vpsadbw %xmm2, %xmm1, %xmm1
616843
; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
617844
; AVX-NEXT: addq $4, %rax
618-
; AVX-NEXT: jne .LBB4_1
845+
; AVX-NEXT: jne .LBB5_1
619846
; AVX-NEXT: # %bb.2: # %middle.block
620847
; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
621848
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0

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