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AMDGPU/GlobalISel: RegBankLegalize rules for async LDS stores (#192717)
1 parent da663a1 commit 695e1ba

2 files changed

Lines changed: 6 additions & 2 deletions

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llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1766,7 +1766,11 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
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addRulesForIOpcs({amdgcn_global_load_async_to_lds_b8,
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amdgcn_global_load_async_to_lds_b32,
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amdgcn_global_load_async_to_lds_b64,
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amdgcn_global_load_async_to_lds_b128})
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amdgcn_global_load_async_to_lds_b128,
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amdgcn_global_store_async_from_lds_b8,
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amdgcn_global_store_async_from_lds_b32,
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amdgcn_global_store_async_from_lds_b64,
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amdgcn_global_store_async_from_lds_b128})
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.Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
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addRulesForIOpcs({amdgcn_perm_pk16_b4_u4}, StandardB)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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declare void @llvm.amdgcn.global.store.async.from.lds.b8(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol)
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declare void @llvm.amdgcn.global.store.async.from.lds.b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol)

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