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1 parent 739fc35 commit 83d09bd

4 files changed

Lines changed: 8 additions & 9 deletions

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clang/include/clang/Basic/arm_sve.td

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -999,13 +999,8 @@ def SVCVTLT_Z_F64_F32 : SInst<"svcvtlt_f64[_f32]", "dPh", "d", MergeZeroExp, "a
999999
}
10001000

10011001
let SVETargetGuard = "sve2p3|sme2p3", SMETargetGuard = "sve2p3|sme2p3" in {
1002-
def SVCVTZN_S8_F16 : SInst<"svcvtzn_s8[_f16_x2]", "d2.O", "c", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1003-
def SVCVTZN_S16_F32 : SInst<"svcvtzn_s16[_f32_x2]", "d2.M", "s", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1004-
def SVCVTZN_S32_F64 : SInst<"svcvtzn_s32[_f64_x2]", "d2.N", "i", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1005-
1006-
def SVCVTZN_U8_F16 : SInst<"svcvtzn_u8[_f16_x2]", "d2.O", "Uc", MergeNone, "aarch64_sve_fcvtzun_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1007-
def SVCVTZN_U16_F32 : SInst<"svcvtzn_u16[_f32_x2]", "d2.M", "Us", MergeNone, "aarch64_sve_fcvtzun_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1008-
def SVCVTZN_U32_F64 : SInst<"svcvtzn_u32[_f64_x2]", "d2.N", "Ui", MergeNone, "aarch64_sve_fcvtzun_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
1002+
def SVCVTZN_S : SInst<"svcvtzn_{0}[_{1}_x2]", "y2.d", "hfd", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsReductionQV, VerifyRuntimeMode]>;
1003+
def SVCVTZN_U : SInst<"svcvtzn_{0}[_{1}_x2]", "e2.d", "hfd", MergeNone, "aarch64_sve_fcvtzun_x2", [IsReductionQV, VerifyRuntimeMode]>;
10091004

10101005
def SVCVTT_F16_S8 : SInst<"svcvtt_f16[_s8]", "Od", "c", MergeNone, "aarch64_sve_scvtflt_f16i8", [IsOverloadNone, VerifyRuntimeMode]>;
10111006
def SVCVTT_F32_S16 : SInst<"svcvtt_f32[_s16]", "Md", "s", MergeNone, "aarch64_sve_scvtflt_f32i16", [IsOverloadNone, VerifyRuntimeMode]>;

clang/include/clang/Basic/arm_sve_sme_incl.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ include "arm_immcheck_incl.td"
7878
// R: scalar of 1/2 width element type (splat to vector type)
7979
// r: scalar of 1/4 width element type (splat to vector type)
8080
// @: unsigned scalar of 1/4 width element type (splat to vector type)
81+
// y: 1/2 width signed elements, 2x element count
8182
// e: 1/2 width unsigned elements, 2x element count
8283
// b: 1/4 width unsigned elements, 4x element count
8384
// h: 1/2 width elements, 2x element count

clang/lib/CodeGen/TargetBuiltins/ARM.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4564,8 +4564,7 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags,
45644564
if (TypeFlags.isOverloadFirstandLast())
45654565
return {Ops[0]->getType(), Ops.back()->getType()};
45664566

4567-
if (TypeFlags.isReductionQV() && !ResultType->isScalableTy() &&
4568-
ResultType->isVectorTy())
4567+
if (TypeFlags.isReductionQV())
45694568
return {ResultType, Ops[1]->getType()};
45704569

45714570
assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads");

clang/utils/TableGen/SveEmitter.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -697,6 +697,10 @@ void SVEType::applyModifier(char Mod) {
697697
Kind = UInt;
698698
ElementBitwidth /= 2;
699699
break;
700+
case 'y':
701+
Kind = SInt;
702+
ElementBitwidth /= 2;
703+
break;
700704
case 'h':
701705
ElementBitwidth /= 2;
702706
break;

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