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Introduce a new flag for overload resolution and combine some front end intrinsics
1 parent 59676e3 commit ad13945

10 files changed

Lines changed: 181 additions & 78 deletions

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‎clang/include/clang/Basic/TargetBuiltins.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -401,6 +401,9 @@ namespace clang {
401401
bool isOverloadFirstandLast() const {
402402
return Flags & IsOverloadFirstandLast;
403403
}
404+
bool isOverloadDefaultAndOp0() const {
405+
return Flags & IsOverloadDefaultAndOp0;
406+
}
404407
bool isPrefetch() const { return Flags & IsPrefetch; }
405408
bool isReverseCompare() const { return Flags & ReverseCompare; }
406409
bool isAppendSVALL() const { return Flags & IsAppendSVALL; }

‎clang/include/clang/Basic/arm_sve.td‎

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,21 +1006,10 @@ let SVETargetGuard = "sve2p3|sme2p3", SMETargetGuard = "sve2p3|sme2p3" in {
10061006
def SVCVTZN_S : SInst<"svcvtzn_{0}[_{1}_x2]", "y2.d", "hfd", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsReductionQV, VerifyRuntimeMode]>;
10071007
def SVCVTZN_U : SInst<"svcvtzn_{0}[_{1}_x2]", "e2.d", "hfd", MergeNone, "aarch64_sve_fcvtzun_x2", [IsReductionQV, VerifyRuntimeMode]>;
10081008

1009-
def SVCVTT_F16_S8 : SInst<"svcvtt_f16[_s8]", "Od", "c", MergeNone, "aarch64_sve_scvtflt_f16i8", [IsOverloadNone, VerifyRuntimeMode]>;
1010-
def SVCVTT_F32_S16 : SInst<"svcvtt_f32[_s16]", "Md", "s", MergeNone, "aarch64_sve_scvtflt_f32i16", [IsOverloadNone, VerifyRuntimeMode]>;
1011-
def SVCVTT_F64_S32 : SInst<"svcvtt_f64[_s32]", "Nd", "i", MergeNone, "aarch64_sve_scvtflt_f64i32", [IsOverloadNone, VerifyRuntimeMode]>;
1012-
1013-
def SVCVTT_F16_U8 : SInst<"svcvtt_f16[_u8]", "Od", "Uc", MergeNone, "aarch64_sve_ucvtflt_f16i8", [IsOverloadNone, VerifyRuntimeMode]>;
1014-
def SVCVTT_F32_U16 : SInst<"svcvtt_f32[_u16]", "Md", "Us", MergeNone, "aarch64_sve_ucvtflt_f32i16", [IsOverloadNone, VerifyRuntimeMode]>;
1015-
def SVCVTT_F64_U32 : SInst<"svcvtt_f64[_u32]", "Nd", "Ui", MergeNone, "aarch64_sve_ucvtflt_f64i32", [IsOverloadNone, VerifyRuntimeMode]>;
1016-
1017-
def SVCVTB_F16_S8 : SInst<"svcvtb_f16[_s8]", "Od", "c", MergeNone, "aarch64_sve_scvtfb_f16i8", [IsOverloadNone, VerifyRuntimeMode]>;
1018-
def SVCVTB_F32_S16 : SInst<"svcvtb_f32[_s16]", "Md", "s", MergeNone, "aarch64_sve_scvtfb_f32i16", [IsOverloadNone, VerifyRuntimeMode]>;
1019-
def SVCVTB_F64_S32 : SInst<"svcvtb_f64[_s32]", "Nd", "i", MergeNone, "aarch64_sve_scvtfb_f64i32", [IsOverloadNone, VerifyRuntimeMode]>;
1020-
1021-
def SVCVTB_F16_U8 : SInst<"svcvtb_f16[_u8]", "Od", "Uc", MergeNone, "aarch64_sve_ucvtfb_f16i8", [IsOverloadNone, VerifyRuntimeMode]>;
1022-
def SVCVTB_F32_U16 : SInst<"svcvtb_f32[_u16]", "Md", "Us", MergeNone, "aarch64_sve_ucvtfb_f32i16", [IsOverloadNone, VerifyRuntimeMode]>;
1023-
def SVCVTB_F64_U32 : SInst<"svcvtb_f64[_u32]", "Nd", "Ui", MergeNone, "aarch64_sve_ucvtfb_f64i32", [IsOverloadNone, VerifyRuntimeMode]>;
1009+
foreach suffix = ["b", "t"] in {
1010+
def SVCVT # !toupper(suffix) # _S: SInst<"svcvt" # suffix # "_{d}[_{1}]", "dy", "hfd", MergeNone, "aarch64_sve_scvtf" # suffix, [IsOverloadDefaultAndOp0, VerifyRuntimeMode]>;
1011+
def SVCVT # !toupper(suffix) # _U: SInst<"svcvt" # suffix # "_{d}[_{1}]", "de", "hfd", MergeNone, "aarch64_sve_ucvtf" # suffix, [IsOverloadDefaultAndOp0, VerifyRuntimeMode]>;
1012+
}
10241013
}
10251014

10261015
////////////////////////////////////////////////////////////////////////////////
@@ -2557,4 +2546,4 @@ let SVETargetGuard = "sve2p3|sme2p3", SMETargetGuard = "sve2p3|sme2p3" in {
25572546

25582547
def SVDOT_LANE_X2_SH : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "s", MergeNone, "aarch64_sve_sdot_lane_x2", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_7>]>;
25592548
def SVDOT_LANE_X2_UH : SInst<"svdot_lane[_{d}_{2}]", "ddhhi", "Us", MergeNone, "aarch64_sve_udot_lane_x2", [VerifyRuntimeMode], [ImmCheck<3, ImmCheck0_7>]>;
2560-
}
2549+
}

‎clang/include/clang/Basic/arm_sve_sme_incl.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,7 @@ def IsOverloadNone : FlagType<0x00100000>; // Intrinsic does no
216216
def IsOverloadWhileOrMultiVecCvt : FlagType<0x00200000>; // Use {default type, typeof(operand1)} as overloaded types.
217217
def IsOverloadWhileRW : FlagType<0x00400000>; // Use {pred(default type), typeof(operand0)} as overloaded types.
218218
def IsOverloadFirstandLast : FlagType<0x00800000>; // Use {typeof(operand0), typeof(last operand)} as overloaded types.
219+
def IsOverloadDefaultAndOp0 : FlagType<0x4000000000000>; // Use {default type, typeof(operand0)} as overloaded types.
219220
def OverloadKindMask : FlagType<0x00E00000>; // When the masked values are all '0', the default type is used as overload type.
220221
def IsByteIndexed : FlagType<0x01000000>;
221222
def IsAppendSVALL : FlagType<0x02000000>; // Appends SV_ALL as the last operand.

‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3939,6 +3939,9 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags,
39393939
if (TypeFlags.isOverloadWhileRW())
39403940
return {getSVEPredType(TypeFlags), Ops[0]->getType()};
39413941

3942+
if (TypeFlags.isOverloadDefaultAndOp0())
3943+
return {DefaultType, Ops[0]->getType()};
3944+
39423945
if (TypeFlags.isOverloadFirstandLast())
39433946
return {Ops[0]->getType(), Ops.back()->getType()};
39443947

‎clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2_int_fp_cvt.c‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -30,12 +30,12 @@
3030

3131
// CHECK-LABEL: @test_svcvtb_f16_s8(
3232
// CHECK-NEXT: entry:
33-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
33+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
3434
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
3535
//
3636
// CPP-CHECK-LABEL: @_Z18test_svcvtb_f16_s8u10__SVInt8_t(
3737
// CPP-CHECK-NEXT: entry:
38-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
38+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
3939
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
4040
//
4141
svfloat16_t test_svcvtb_f16_s8(svint8_t zn) MODE_ATTR {
@@ -44,12 +44,12 @@ svfloat16_t test_svcvtb_f16_s8(svint8_t zn) MODE_ATTR {
4444

4545
// CHECK-LABEL: @test_svcvtb_f32_s16(
4646
// CHECK-NEXT: entry:
47-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
47+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
4848
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
4949
//
5050
// CPP-CHECK-LABEL: @_Z19test_svcvtb_f32_s16u11__SVInt16_t(
5151
// CPP-CHECK-NEXT: entry:
52-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
52+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
5353
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
5454
//
5555
svfloat32_t test_svcvtb_f32_s16(svint16_t zn) MODE_ATTR {
@@ -58,12 +58,12 @@ svfloat32_t test_svcvtb_f32_s16(svint16_t zn) MODE_ATTR {
5858

5959
// CHECK-LABEL: @test_svcvtb_f64_s32(
6060
// CHECK-NEXT: entry:
61-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
61+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
6262
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
6363
//
6464
// CPP-CHECK-LABEL: @_Z19test_svcvtb_f64_s32u11__SVInt32_t(
6565
// CPP-CHECK-NEXT: entry:
66-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
66+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
6767
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
6868
//
6969
svfloat64_t test_svcvtb_f64_s32(svint32_t zn) MODE_ATTR {
@@ -72,12 +72,12 @@ svfloat64_t test_svcvtb_f64_s32(svint32_t zn) MODE_ATTR {
7272

7373
// CHECK-LABEL: @test_svcvtb_f16_u8(
7474
// CHECK-NEXT: entry:
75-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
75+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
7676
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
7777
//
7878
// CPP-CHECK-LABEL: @_Z18test_svcvtb_f16_u8u11__SVUint8_t(
7979
// CPP-CHECK-NEXT: entry:
80-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
80+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
8181
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
8282
//
8383
svfloat16_t test_svcvtb_f16_u8(svuint8_t zn) MODE_ATTR {
@@ -86,12 +86,12 @@ svfloat16_t test_svcvtb_f16_u8(svuint8_t zn) MODE_ATTR {
8686

8787
// CHECK-LABEL: @test_svcvtb_f32_u16(
8888
// CHECK-NEXT: entry:
89-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
89+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
9090
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
9191
//
9292
// CPP-CHECK-LABEL: @_Z19test_svcvtb_f32_u16u12__SVUint16_t(
9393
// CPP-CHECK-NEXT: entry:
94-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
94+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
9595
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
9696
//
9797
svfloat32_t test_svcvtb_f32_u16(svuint16_t zn) MODE_ATTR {
@@ -100,12 +100,12 @@ svfloat32_t test_svcvtb_f32_u16(svuint16_t zn) MODE_ATTR {
100100

101101
// CHECK-LABEL: @test_svcvtb_f64_u32(
102102
// CHECK-NEXT: entry:
103-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
103+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
104104
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
105105
//
106106
// CPP-CHECK-LABEL: @_Z19test_svcvtb_f64_u32u12__SVUint32_t(
107107
// CPP-CHECK-NEXT: entry:
108-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
108+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
109109
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
110110
//
111111
svfloat64_t test_svcvtb_f64_u32(svuint32_t zn) MODE_ATTR {
@@ -114,12 +114,12 @@ svfloat64_t test_svcvtb_f64_u32(svuint32_t zn) MODE_ATTR {
114114

115115
// CHECK-LABEL: @test_svcvt_f16_s8(
116116
// CHECK-NEXT: entry:
117-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtflt.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
117+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
118118
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
119119
//
120120
// CPP-CHECK-LABEL: @_Z17test_svcvt_f16_s8u10__SVInt8_t(
121121
// CPP-CHECK-NEXT: entry:
122-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtflt.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
122+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.scvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
123123
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
124124
//
125125
svfloat16_t test_svcvt_f16_s8(svint8_t zn) MODE_ATTR {
@@ -128,12 +128,12 @@ svfloat16_t test_svcvt_f16_s8(svint8_t zn) MODE_ATTR {
128128

129129
// CHECK-LABEL: @test_svcvt_f32_s16(
130130
// CHECK-NEXT: entry:
131-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtflt.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
131+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
132132
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
133133
//
134134
// CPP-CHECK-LABEL: @_Z18test_svcvt_f32_s16u11__SVInt16_t(
135135
// CPP-CHECK-NEXT: entry:
136-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtflt.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
136+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.scvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
137137
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
138138
//
139139
svfloat32_t test_svcvt_f32_s16(svint16_t zn) MODE_ATTR {
@@ -142,12 +142,12 @@ svfloat32_t test_svcvt_f32_s16(svint16_t zn) MODE_ATTR {
142142

143143
// CHECK-LABEL: @test_svcvt_f64_s32(
144144
// CHECK-NEXT: entry:
145-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtflt.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
145+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
146146
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
147147
//
148148
// CPP-CHECK-LABEL: @_Z18test_svcvt_f64_s32u11__SVInt32_t(
149149
// CPP-CHECK-NEXT: entry:
150-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtflt.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
150+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.scvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
151151
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
152152
//
153153
svfloat64_t test_svcvt_f64_s32(svint32_t zn) MODE_ATTR {
@@ -156,12 +156,12 @@ svfloat64_t test_svcvt_f64_s32(svint32_t zn) MODE_ATTR {
156156

157157
// CHECK-LABEL: @test_svcvt_f16_u8(
158158
// CHECK-NEXT: entry:
159-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtflt.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
159+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
160160
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
161161
//
162162
// CPP-CHECK-LABEL: @_Z17test_svcvt_f16_u8u11__SVUint8_t(
163163
// CPP-CHECK-NEXT: entry:
164-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtflt.f16i8(<vscale x 16 x i8> [[ZN:%.*]])
164+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ucvtft.nxv8f16.nxv16i8(<vscale x 16 x i8> [[ZN:%.*]])
165165
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
166166
//
167167
svfloat16_t test_svcvt_f16_u8(svuint8_t zn) MODE_ATTR {
@@ -170,12 +170,12 @@ svfloat16_t test_svcvt_f16_u8(svuint8_t zn) MODE_ATTR {
170170

171171
// CHECK-LABEL: @test_svcvt_f32_u16(
172172
// CHECK-NEXT: entry:
173-
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtflt.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
173+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
174174
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
175175
//
176176
// CPP-CHECK-LABEL: @_Z18test_svcvt_f32_u16u12__SVUint16_t(
177177
// CPP-CHECK-NEXT: entry:
178-
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtflt.f32i16(<vscale x 8 x i16> [[ZN:%.*]])
178+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ucvtft.nxv4f32.nxv8i16(<vscale x 8 x i16> [[ZN:%.*]])
179179
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
180180
//
181181
svfloat32_t test_svcvt_f32_u16(svuint16_t zn) MODE_ATTR {
@@ -184,12 +184,12 @@ svfloat32_t test_svcvt_f32_u16(svuint16_t zn) MODE_ATTR {
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// CHECK-LABEL: @test_svcvt_f64_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtflt.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
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// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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// CPP-CHECK-LABEL: @_Z18test_svcvt_f64_u32u12__SVUint32_t(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtflt.f64i32(<vscale x 4 x i32> [[ZN:%.*]])
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ucvtft.nxv2f64.nxv4i32(<vscale x 4 x i32> [[ZN:%.*]])
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// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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svfloat64_t test_svcvt_f64_u32(svuint32_t zn) MODE_ATTR {

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