[AMDGPU][GlobalIsel] Add regbank support for cvt_scalef32_sr_pk_f6_f116/32 intrinsics (#192745)

This patch adds register bank legalization rules for
cvt_scalef32_sr_pk_f6_f116/32 intrinsics in the AMDGPU GlobalISel
pipeline.

Author: mssefat

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

@@ -1450,6 +1450,12 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case VgprV2S64:
   case UniInVgprV2S64:
     return LLT::fixed_vector(2, 64);
+  case VgprV6S32:
+    return LLT::fixed_vector(6, 32);
+  case VgprV32S16:
+    return LLT::fixed_vector(32, 16);
+  case VgprV32S32:
+    return LLT::fixed_vector(32, 32);
   default:
     return LLT();
   }
@@ -1611,7 +1617,9 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case VgprV3S32:
   case VgprV4S16:
   case VgprV4S32:
+  case VgprV6S32:
   case VgprV8S32:
+  case VgprV32S16:
   case VgprB32:
   case VgprB64:
   case VgprB96:
@@ -1675,7 +1683,9 @@ bool RegBankLegalizeHelper::applyMappingDst(
     case VgprV3S32:
     case VgprV4S16:
     case VgprV4S32:
-    case VgprV8S32: {
+    case VgprV6S32:
+    case VgprV8S32:
+    case VgprV32S16: {
       assert(Ty == getTyFromID(MethodIDs[OpIdx]));
       assert(RB == getRegBankFromID(MethodIDs[OpIdx]));
       break;
@@ -1868,7 +1878,10 @@ bool RegBankLegalizeHelper::applyMappingSrc(
     case VgprV3S32:
     case VgprV4S16:
     case VgprV4S32:
-    case VgprV8S32: {
+    case VgprV6S32:
+    case VgprV8S32:
+    case VgprV32S16:
+    case VgprV32S32: {
       assert(Ty == getTyFromID(MethodIDs[i]));
       if (RB != VgprRB) {
         auto CopyToVgpr = B.buildCopy({VgprRB, Ty}, Reg);

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

@@ -193,6 +193,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::fixed_vector(3, 32) && MUI.isDivergent(Reg);
   case DivV4S16:
     return MRI.getType(Reg) == LLT::fixed_vector(4, 16) && MUI.isDivergent(Reg);
+  case DivV6S32:
+    return MRI.getType(Reg) == LLT::fixed_vector(6, 32) && MUI.isDivergent(Reg);
   case DivB32:
     return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergent(Reg);
   case DivB64:
@@ -1714,6 +1716,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32}})
       .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32}});
 
+  addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk32_bf6_f16,
+                    amdgcn_cvt_scalef32_sr_pk32_fp6_f16,
+                    amdgcn_cvt_scalef32_sr_pk32_bf6_bf16,
+                    amdgcn_cvt_scalef32_sr_pk32_fp6_bf16},
+                   Standard)
+      .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S16, Vgpr32, Vgpr32}}});
+
+  addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk32_bf6_f32,
+                    amdgcn_cvt_scalef32_sr_pk32_fp6_f32},
+                   Standard)
+      .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S32, Vgpr32, Vgpr32}}});
+
   addRulesForIOpcs({amdgcn_global_load_tr_b64})
       .Any({{DivB64}, {{VgprB64}, {IntrId, SgprP1}}})
       .Any({{DivB32}, {{VgprB32}, {IntrId, SgprP1}}});

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

@@ -107,6 +107,7 @@ enum UniformityLLTOpPredicateID {
   DivV2S64,
   DivV3S32,
   DivV4S16,
+  DivV6S32,
 
   // B types
   B32,
@@ -255,6 +256,10 @@ enum RegBankLLTMappingApplyID {
   Vgpr32AExt,
   Vgpr32SExt,
   Vgpr32ZExt,
+
+  VgprV6S32,
+  VgprV32S16,
+  VgprV32S32,
 };
 
 // Instruction needs to be replaced with sequence of instructions. Lowering was