[RISC-V][MC] Introduce initial support for RVY (CHERI)#176871
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This adds MC-level support for most of the base Y extension instructions
using version 0.9.8.2 of the specification. This initial pull request is
restricted to the execution-mode-independent subset. The Y extension
(CHERI for RISC-V) also introduces an execution mode that determines
whether certain register operands use the full extended register or only
the address subset (the current XLEN registers). The instructions that
depend on execution mode (loads/stores/jumps + AUIPC) will be added in
the following commits in this stack of changes.
Specification: https://github.com/riscv/riscv-cheri/releases/tag/v0.9.8.1
Co-authored-by: Jessica Clarke jrtc27@jrtc27.com
Co-authored-by: Alexander Richardson alexrichardson@google.com
Co-authored-by: Petr Vesely petr.vesely@codasip.com