[AMDGPU] Drop docs for invalid load-release and store-acquire operations

[ritter-x2a]

The LangRef says "release and acq_rel orderings are not valid on load
instructions" for loads
and "acquire and acq_rel orderings aren't valid on store instructions"
for stores.
Providing them in textual IR is diagnosed with an error.

Therefore, we should not define semantics for these invalid constructs.

Part of LCOMPILER-2273.

[ritter-x2a]

• [AMDGPU] Drop docs for invalid load-release and store-acquire operations #202338 👈 (View in Graphite)
• main

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[llvmorg-github-actions]

@llvm/pr-subscribers-backend-amdgpu

Author: Fabian Ritter (ritter-x2a)

Changes

The LangRef says "release and acq_rel orderings are not valid on load
instructions" for loads
and "acquire and acq_rel orderings aren't valid on store instructions"
for stores.
Providing them in textual IR is diagnosed with an error.

Therefore, we should not define semantics for these invalid constructs.

Part of LCOMPILER-2273.

---

Full diff: https://github.com/llvm/llvm-project/pull/202338.diff

1 Files Affected:

• (modified) llvm/docs/AMDGPUUsage.rst (-9)

diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 121b66a657f5d..ed4c759fd24f8 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -7214,15 +7214,6 @@ orderings (``acquire``, ``release``, ``acq_rel``, or ``seq_cst``).
 The memory model does not support the region address space which is treated as
 non-atomic.
 
-Acquire memory ordering is not meaningful on store atomic instructions and is
-treated as non-atomic.
-
-Release memory ordering is not meaningful on load atomic instructions and is
-treated as non-atomic.
-
-Acquire-release memory ordering is not meaningful on load or store atomic
-instructions and is treated as acquire and release respectively.
-
 The memory order also adds the single thread optimization constraints defined in
 table
 :ref:`amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-table`.

[nhaehnle]

Thanks!