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Tim Corringham
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Update WaveActiveBallot.Wave32.test and WaveActiveBallot.Wave64.test
The Output buffer stride for WaveActiveBallot.Wave32.test and WaveActiveBallot.Wave64.test was set to 4, but the buffer holds uint4 elements so requires a stride of 16 (4 * 4). With the amended stride these now pass on AMD DXIL so the XFAIL has been removed.
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-118
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‎test/WaveOps/WaveActiveBallot.Wave32.test‎

Lines changed: 56 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,59 +1,56 @@
1-
#--- source.hlsl
2-
RWStructuredBuffer<uint4> Out : register(u1);
3-
4-
[WaveSize(32)]
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[numthreads(32, 1, 1)]
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void main(uint3 threadID : SV_DispatchThreadID) {
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// We expect the first resulting uint's bitmask to be
8-
// 0xBFFFFFFF
9-
Out[0] = WaveActiveBallot(threadID.x != 30);
10-
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// We expect the first resulting uint's bitmask to be
12-
// 0x0000FFFF
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Out[1] = WaveActiveBallot(threadID.x < 16);
14-
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// We expect the resulting uint4 to be 4 0x00000000's
16-
Out[2] = WaveActiveBallot(false);
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}
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//--- pipeline.yaml
20-
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: Out
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Format: UInt32
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Stride: 4
30-
FillSize: 48
31-
- Name: ExpectedOut
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Format: UInt32
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Stride: 4
34-
Data: [3221225471, 0, 0, 0, 65535, 0, 0, 0, 0, 0, 0, 0]
35-
Results:
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- Result: Test
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Rule: BufferExact
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Actual: Out
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Expected: ExpectedOut
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DescriptorSets:
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- Resources:
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- Name: Out
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
47-
VulkanBinding:
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Binding: 1
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...
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#--- end
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# REQUIRES: WaveSize_32
53-
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# Bug: https://github.com/llvm/offload-test-suite/issues/688
55-
# XFAIL: AMD && DirectX
56-
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# RUN: split-file %s %t
58-
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
59-
# RUN: %offloader %t/pipeline.yaml %t.o
1+
#--- source.hlsl
2+
RWStructuredBuffer<uint4> Out : register(u1);
3+
4+
[WaveSize(32)]
5+
[numthreads(32, 1, 1)]
6+
void main(uint3 threadID : SV_DispatchThreadID) {
7+
// We expect the first resulting uint's bitmask to be
8+
// 0xBFFFFFFF
9+
Out[0] = WaveActiveBallot(threadID.x != 30);
10+
11+
// We expect the first resulting uint's bitmask to be
12+
// 0x0000FFFF
13+
Out[1] = WaveActiveBallot(threadID.x < 16);
14+
15+
// We expect the resulting uint4 to be 4 0x00000000's
16+
Out[2] = WaveActiveBallot(false);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
25+
DispatchSize: [1, 1, 1]
26+
Buffers:
27+
- Name: Out
28+
Format: UInt32
29+
Stride: 16
30+
FillSize: 48
31+
- Name: ExpectedOut
32+
Format: UInt32
33+
Stride: 4
34+
Data: [3221225471, 0, 0, 0, 65535, 0, 0, 0, 0, 0, 0, 0]
35+
Results:
36+
- Result: Test
37+
Rule: BufferExact
38+
Actual: Out
39+
Expected: ExpectedOut
40+
DescriptorSets:
41+
- Resources:
42+
- Name: Out
43+
Kind: RWStructuredBuffer
44+
DirectXBinding:
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Register: 1
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Space: 0
47+
VulkanBinding:
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Binding: 1
49+
...
50+
#--- end
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# REQUIRES: WaveSize_32
53+
54+
# RUN: split-file %s %t
55+
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
56+
# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WaveActiveBallot.Wave64.test‎

Lines changed: 56 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,59 +1,56 @@
1-
#--- source.hlsl
2-
RWStructuredBuffer<uint4> Out : register(u1);
3-
4-
[WaveSize(64)]
5-
[numthreads(64, 1, 1)]
6-
void main(uint3 threadID : SV_DispatchThreadID) {
7-
// We expect the first and second resulting uint's bitmask to be
8-
// 0xBFFFFFFF
9-
Out[0] = WaveActiveBallot(threadID.x != 30 && threadID.x != 62);
10-
11-
// We expect the first resulting uint's bitmask to be
12-
// 0x0000FFFF, and the second to be 0xFFFF0000
13-
Out[1] = WaveActiveBallot(threadID.x < 16 || threadID.x > 47 );
14-
15-
// We expect the resulting uint4 to be 4 0x00000000's
16-
Out[2] = WaveActiveBallot(false);
17-
}
18-
19-
//--- pipeline.yaml
20-
21-
---
22-
Shaders:
23-
- Stage: Compute
24-
Entry: main
25-
DispatchSize: [1, 1, 1]
26-
Buffers:
27-
- Name: Out
28-
Format: UInt32
29-
Stride: 4
30-
FillSize: 48
31-
- Name: ExpectedOut
32-
Format: UInt32
33-
Stride: 4
34-
Data: [3221225471, 3221225471, 0, 0, 65535, 4294901760, 0, 0, 0, 0, 0, 0]
35-
Results:
36-
- Result: Test
37-
Rule: BufferExact
38-
Actual: Out
39-
Expected: ExpectedOut
40-
DescriptorSets:
41-
- Resources:
42-
- Name: Out
43-
Kind: RWStructuredBuffer
44-
DirectXBinding:
45-
Register: 1
46-
Space: 0
47-
VulkanBinding:
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Binding: 1
49-
...
50-
#--- end
51-
52-
# REQUIRES: WaveSize_64
53-
54-
# Bug: https://github.com/llvm/offload-test-suite/issues/688
55-
# XFAIL: AMD && DirectX
56-
57-
# RUN: split-file %s %t
58-
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
59-
# RUN: %offloader %t/pipeline.yaml %t.o
1+
#--- source.hlsl
2+
RWStructuredBuffer<uint4> Out : register(u1);
3+
4+
[WaveSize(64)]
5+
[numthreads(64, 1, 1)]
6+
void main(uint3 threadID : SV_DispatchThreadID) {
7+
// We expect the first and second resulting uint's bitmask to be
8+
// 0xBFFFFFFF
9+
Out[0] = WaveActiveBallot(threadID.x != 30 && threadID.x != 62);
10+
11+
// We expect the first resulting uint's bitmask to be
12+
// 0x0000FFFF, and the second to be 0xFFFF0000
13+
Out[1] = WaveActiveBallot(threadID.x < 16 || threadID.x > 47 );
14+
15+
// We expect the resulting uint4 to be 4 0x00000000's
16+
Out[2] = WaveActiveBallot(false);
17+
}
18+
19+
//--- pipeline.yaml
20+
21+
---
22+
Shaders:
23+
- Stage: Compute
24+
Entry: main
25+
DispatchSize: [1, 1, 1]
26+
Buffers:
27+
- Name: Out
28+
Format: UInt32
29+
Stride: 16
30+
FillSize: 48
31+
- Name: ExpectedOut
32+
Format: UInt32
33+
Stride: 4
34+
Data: [3221225471, 3221225471, 0, 0, 65535, 4294901760, 0, 0, 0, 0, 0, 0]
35+
Results:
36+
- Result: Test
37+
Rule: BufferExact
38+
Actual: Out
39+
Expected: ExpectedOut
40+
DescriptorSets:
41+
- Resources:
42+
- Name: Out
43+
Kind: RWStructuredBuffer
44+
DirectXBinding:
45+
Register: 1
46+
Space: 0
47+
VulkanBinding:
48+
Binding: 1
49+
...
50+
#--- end
51+
52+
# REQUIRES: WaveSize_64
53+
54+
# RUN: split-file %s %t
55+
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
56+
# RUN: %offloader %t/pipeline.yaml %t.o

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