From bb8461eccee82f846554fa7ce62e0626b06d0ad2 Mon Sep 17 00:00:00 2001
From: Dan Brown <danbrown@amd.com>
Date: Thu, 9 Oct 2025 15:48:23 -0600
Subject: [PATCH 1/2] Adds tests for isnan().

---
 test/Feature/HLSLLib/isnan.16.test | 65 ++++++++++++++++++++++++++++++
 test/Feature/HLSLLib/isnan.32.test | 60 +++++++++++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 test/Feature/HLSLLib/isnan.16.test
 create mode 100644 test/Feature/HLSLLib/isnan.32.test

diff --git a/test/Feature/HLSLLib/isnan.16.test b/test/Feature/HLSLLib/isnan.16.test
new file mode 100644
index 000000000..375093491
--- /dev/null
+++ b/test/Feature/HLSLLib/isnan.16.test
@@ -0,0 +1,65 @@
+#--- source.hlsl
+
+StructuredBuffer<half4> In : register(t0);
+RWStructuredBuffer<bool4> Out : register(u1);
+
+[numthreads(1,1,1)]
+void main() {
+  Out[0] = isnan(In[0]);
+  bool4 Tmp = {isnan(In[0].xyz), isnan(In[0].w)};
+  Out[1] = Tmp;
+  Out[2].zw = isnan(In[0].zw);
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float16
+    Stride: 8
+    Data: [0x7c00, 0xfc00, 0x3c00, 0x7e00] # Inf, -Inf, 1, Nan
+  - Name: Out
+    Format: Bool
+    Stride: 16
+    FillSize: 48
+  - Name: ExpectedOut # The result we expect
+    Format: Bool
+    Stride: 16
+    Data: [0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1]
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+...
+#--- end
+
+# A bug in the Metal Shader Converter caused it to mis-translate this operation.
+# Version 3 fixes this issue.
+# UNSUPPORTED: Clang && Metal && !metal-shaderconverter-3.0.0-or-later
+
+# REQUIRES: Half
+# RUN: split-file %s %t
+# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/Feature/HLSLLib/isnan.32.test b/test/Feature/HLSLLib/isnan.32.test
new file mode 100644
index 000000000..d8432fee5
--- /dev/null
+++ b/test/Feature/HLSLLib/isnan.32.test
@@ -0,0 +1,60 @@
+#--- source.hlsl
+
+StructuredBuffer<float4> In : register(t0);
+RWStructuredBuffer<bool4> Out : register(u1);
+
+[numthreads(1,1,1)]
+void main() {
+  Out[0] = isnan(In[0]);
+  bool4 Tmp = {isnan(In[0].xyz), isnan(In[0].w)};
+  Out[1] = Tmp;
+  Out[2].zw = isnan(In[0].zw);
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float32
+    Stride: 16
+    Data: [inf, -inf, 1.0, nan] # Inf, -Inf, 1, Nan
+  - Name: Out
+    Format: Bool
+    Stride: 16
+    FillSize: 48
+  - Name: ExpectedOut # The result we expect
+    Format: Bool
+    Stride: 16
+    Data: [0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1]
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+...
+#--- end
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o

From 440f873b64f472893bfce5c872ecdd20e89e6252 Mon Sep 17 00:00:00 2001
From: Justin Bogner <mail@justinbogner.com>
Date: Thu, 18 Jun 2026 14:12:48 -0700
Subject: [PATCH 2/2] Remove DispatchSize

it's been moved to DispatchParameters and matches the default anyway

Co-authored-by: Justin Bogner <mail@justinbogner.com>
---
 test/Feature/HLSLLib/isnan.16.test | 1 -
 test/Feature/HLSLLib/isnan.32.test | 1 -
 2 files changed, 2 deletions(-)

diff --git a/test/Feature/HLSLLib/isnan.16.test b/test/Feature/HLSLLib/isnan.16.test
index 375093491..25cd9c2e5 100644
--- a/test/Feature/HLSLLib/isnan.16.test
+++ b/test/Feature/HLSLLib/isnan.16.test
@@ -17,7 +17,6 @@ void main() {
 Shaders:
   - Stage: Compute
     Entry: main
-    DispatchSize: [1, 1, 1]
 Buffers:
   - Name: In
     Format: Float16
diff --git a/test/Feature/HLSLLib/isnan.32.test b/test/Feature/HLSLLib/isnan.32.test
index d8432fee5..266f8e98e 100644
--- a/test/Feature/HLSLLib/isnan.32.test
+++ b/test/Feature/HLSLLib/isnan.32.test
@@ -17,7 +17,6 @@ void main() {
 Shaders:
   - Stage: Compute
     Entry: main
-    DispatchSize: [1, 1, 1]
 Buffers:
   - Name: In
     Format: Float32