A PeakRDL extension to generate OpenTitan register block SystemVerilog from SystemRDL files.
rdl2ot export-rtl <input_rdl> <output_dir>Example:
mkdir -p /tmp/lc_ctrl
rdl2ot export-rtl tests/snapshots/lc_ctrl.rdl /tmp/lc_ctrl/pip install peakrdl rdl2otmkdir -p /tmp/lc_ctrl
peakrdl rdl2ot tests/snapshots/lc_ctrl.rdl -o /tmp/lc_ctrl/cd rdl2ot
pytest