diff --git a/flake.lock b/flake.lock index 788c403..73ee79b 100644 --- a/flake.lock +++ b/flake.lock @@ -24,11 +24,11 @@ "nixpkgs": "nixpkgs" }, "locked": { - "lastModified": 1760457119, - "narHash": "sha256-jbAOK8dLYJSnNzw4CVyJyIsC/lF+wbafcm2OAcYA1Yc=", + "lastModified": 1764161940, + "narHash": "sha256-yAaDczgFXWUxqIzwszB39TPcC7a2fScLbYlKuy8H044=", "owner": "lowRISC", "repo": "lowrisc-nix", - "rev": "4a535a458743de4bff0ecf31d18883c78533a6e8", + "rev": "ab7347279402e92ea9fe667cba5fc417e7d00790", "type": "github" }, "original": { @@ -39,11 +39,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1759994382, - "narHash": "sha256-wSK+3UkalDZRVHGCRikZ//CyZUJWDJkBDTQX1+G77Ow=", + "lastModified": 1763622513, + "narHash": "sha256-1jQnuyu82FpiSxowrF/iFK6Toh9BYprfDqfs4BB+19M=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "5da4a26309e796daa7ffca72df93dbe53b8164c7", + "rev": "c58bc7f5459328e4afac201c5c4feb7c818d604b", "type": "github" }, "original": { @@ -55,11 +55,11 @@ }, "nixpkgs_2": { "locked": { - "lastModified": 1761468971, - "narHash": "sha256-vY2OLVg5ZTobdroQKQQSipSIkHlxOTrIF1fsMzPh8w8=", + "lastModified": 1764836381, + "narHash": "sha256-8jemYbbW9EBttQKHep7Rj8kzXaxsrk/lACdXA2DN5Xk=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "78e34d1667d32d8a0ffc3eba4591ff256e80576e", + "rev": "ff06bd3398fb1bea6c937039ece7e7c8aa396ebf", "type": "github" }, "original": { @@ -82,11 +82,11 @@ ] }, "locked": { - "lastModified": 1759113590, - "narHash": "sha256-fgxP2RCN4cg0jYiMYoETYc7TZ2JjgyvJa2y9l8oSUFE=", + "lastModified": 1763662255, + "narHash": "sha256-4bocaOyLa3AfiS8KrWjZQYu+IAta05u3gYZzZ6zXbT0=", "owner": "pyproject-nix", "repo": "build-system-pkgs", - "rev": "dbfc0483b5952c6b86e36f8b3afeb9dde30ea4b5", + "rev": "042904167604c681a090c07eb6967b4dd4dae88c", "type": "github" }, "original": { @@ -102,11 +102,11 @@ ] }, "locked": { - "lastModified": 1760402624, - "narHash": "sha256-jF6UKLs2uGc2rtved8Vrt58oTWjTQoAssuYs/0578Z4=", + "lastModified": 1764134915, + "narHash": "sha256-xaKvtPx6YAnA3HQVp5LwyYG1MaN4LLehpQI8xEdBvBY=", "owner": "pyproject-nix", "repo": "pyproject.nix", - "rev": "84c4ea102127c77058ea1ed7be7300261fafc7d2", + "rev": "2c8df1383b32e5443c921f61224b198a2282a657", "type": "github" }, "original": { @@ -149,11 +149,11 @@ ] }, "locked": { - "lastModified": 1761527626, - "narHash": "sha256-neDfvbpFlzUQfH9C+hVRUX0/RXUbJBidw4pFcdMYhZA=", + "lastModified": 1764702535, + "narHash": "sha256-W0DLyt1Cmlo3ZPYKZA/pM/YwBHvz+/eP8hVk7VVu0F4=", "owner": "pyproject-nix", "repo": "uv2nix", - "rev": "46a8e8bbb2d9e34b686329ac16e4a8861394f03a", + "rev": "9a903e8b107df2228d79f294044214fa453f430c", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index 0e1635a..0a49689 100644 --- a/flake.nix +++ b/flake.nix @@ -37,7 +37,6 @@ pkgs = import nixpkgs { inherit system; }; - peakrdl = lowrisc-nix.packages.${system}.peakrdl; workspace = uv2nix.lib.workspace.loadWorkspace {workspaceRoot = ./.;}; overlay = workspace.mkPyprojectOverlay { @@ -61,7 +60,6 @@ in { devShells.x86_64-linux.default = pkgs.mkShell { packages = [env pkgs.uv pkgs.reuse]; - buildInputs = [peakrdl]; }; formatter.x86_64-linux = nixpkgs.legacyPackages.x86_64-linux.alejandra; }; diff --git a/rdl2ot/pyproject.toml b/rdl2ot/pyproject.toml index 41e5538..4898b07 100644 --- a/rdl2ot/pyproject.toml +++ b/rdl2ot/pyproject.toml @@ -4,7 +4,7 @@ [project] name = "rdl2ot" -version = "0.3.0" +version = "0.4.0" description = "An extension of PeakRDL to generate OpenTitan RTL." requires-python = ">=3.10" keywords = ["SystemRDL", "OpenTitan", "Codegen"] @@ -12,7 +12,7 @@ readme = "README.md" dependencies = [ "click>=8.3.0", "jinja2>=3.1.6", - "systemrdl-compiler>=1.29", + "systemrdl-compiler~=1.32.1", ] authors = [ diff --git a/rdl2ot/src/rdl2ot/cli.py b/rdl2ot/src/rdl2ot/cli.py index 9f3114e..313c9ea 100644 --- a/rdl2ot/src/rdl2ot/cli.py +++ b/rdl2ot/src/rdl2ot/cli.py @@ -22,18 +22,18 @@ def main() -> None: @main.command() @click.argument( "input_file", - type=click.Path(writable=True), + type=click.Path(path_type=Path, writable=False), ) @click.argument( "out_dir", default="./result", - type=click.Path(writable=True), + type=click.Path(path_type=Path, writable=True), ) @click.option( "--soc", is_flag=True, ) -def export_rtl(input_file: str, out_dir: str, soc: bool = False) -> None: +def export_rtl(input_file: Path, out_dir: Path, soc: bool = False) -> None: """Export opentitan rtl. INPUT_FILE: The input RDL @@ -46,6 +46,6 @@ def export_rtl(input_file: str, out_dir: str, soc: bool = False) -> None: rdlc.compile_file(input_file) root = rdlc.elaborate() - rtl_exporter.run(root.top, Path(out_dir), soc) + rtl_exporter.run(root.top, out_dir, soc) print("Successfully finished!\n") diff --git a/rdl2ot/src/rdl2ot/opentitan.py b/rdl2ot/src/rdl2ot/opentitan.py index bcbfccd..1910211 100644 --- a/rdl2ot/src/rdl2ot/opentitan.py +++ b/rdl2ot/src/rdl2ot/opentitan.py @@ -5,6 +5,7 @@ """Functions with opentitan specific logic.""" import re +from enum import Enum from systemrdl import node from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType @@ -67,7 +68,7 @@ def needs_int_qe(reg: dict) -> bool: An internal q-enable means the net may be consumed by other reg logic but will not be exposed in the package file. """ - return (bool(reg["async_clk"]) and reg["hw_writable"]) or needs_qe(reg) + return (bool(reg.get("async_clk", False)) and reg["hw_writable"]) or needs_qe(reg) def get_bit_width(offset: int) -> int: @@ -98,11 +99,11 @@ def get_sw_access_enum(field: node.FieldNode) -> str: return "NONE" -def fields_no_write_en(reg: dict) -> int: - """Count how many fields has write enable.""" +def fields_write_en_mask(reg: dict) -> int: + """Return a mask of bits mapping to write enable fields.""" res = 0 for idx, field in enumerate(reg["fields"]): - res |= (not needs_we(field)) << idx + res |= int(not needs_we(field)) << idx return res @@ -121,9 +122,44 @@ def is_homogeneous(reg: dict) -> bool: The offset are excluded from the comparison. """ - exclude = ["name", "msb", "lsb", "bitmask", "type"] + exclude = ["name", "msb", "lsb", "bitmask", "type", "type_name"] unamed_fields = [ {key: value for key, value in f.items() if key not in exclude} for f in reg["fields"] ] names = {re.sub(r"_\d+$", "", f["name"]) for f in reg["fields"]} return all(f == unamed_fields[0] for f in unamed_fields[1:]) and len(names) == 1 + + +class SigType(Enum): + """Used to give a signal different purposes.""" + + NONE = "None" + Interrupt = "Interrupt" + Alert = "Alert" + InterModReqRsp = "InterModReqRsp" + InterModReq = "InterModReq" + InterModRecv = "InterModRecv" + InOut = "InOut" + Input = "Input" + Output = "Output" + Sync = "Sync" + + def is_pad(self) -> bool: + """Check whether a signal is a pad.""" + return self in [SigType.InOut, SigType.Input, SigType.Output] + + def is_interrupt(self) -> bool: + """Check whether a signal is a interrupt.""" + return self in [SigType.Interrupt] + + def is_alert(self) -> bool: + """Check whether a signal is a alert.""" + return self in [SigType.Alert] + + def is_inter_module(self) -> bool: + """Check whether a signal is a inter module.""" + return self in [SigType.InterModReqRsp, SigType.InterModReq, SigType.InterModRecv] + + def is_sync(self) -> bool: + """Check whether a signal is used for synchronization.""" + return self in [SigType.Sync] diff --git a/rdl2ot/src/rdl2ot/rtl_exporter.py b/rdl2ot/src/rdl2ot/rtl_exporter.py index 40d8170..c0922f1 100644 --- a/rdl2ot/src/rdl2ot/rtl_exporter.py +++ b/rdl2ot/src/rdl2ot/rtl_exporter.py @@ -5,12 +5,12 @@ """Export RDL to opentitan RTL.""" import json -from enum import Enum +import re from pathlib import Path from jinja2 import Environment, FileSystemLoader from systemrdl import node -from systemrdl.rdltypes import OnReadType +from systemrdl.rdltypes import BuiltinEnum, OnReadType, UserEnum from systemrdl.rdltypes.user_struct import UserStruct from rdl2ot import opentitan @@ -24,6 +24,10 @@ def _camelcase(value: str) -> str: return "".join(word.capitalize() for word in words) +def _reindex(s: str, new_index: int) -> str: + return re.sub(r"\d+", str(new_index), s) + + def run(root_node: node.AddrmapNode, out_dir: Path, is_soc: bool = False) -> None: """Export RDL to opentitan RTL. @@ -49,6 +53,7 @@ def _export(ip_block: dict, out_dir: Path) -> None: file_loader = FileSystemLoader(TEMPLATES_DIR) env = Environment(loader=file_loader) env.filters["camelcase"] = _camelcase + env.filters["reindex"] = _reindex ip_name = ip_block["name"].lower() reg_pkg_tpl = env.get_template("reg_pkg.sv.tpl") @@ -60,40 +65,14 @@ def _export(ip_block: dict, out_dir: Path) -> None: reg_top_tpl = env.get_template("reg_top.sv.tpl") for interface in ip_block["interfaces"]: name = "_{}".format(interface["name"].lower()) if "name" in interface else "" - data_ = {"name": ip_name, "interface": interface} + data_ = {"name": ip_name, "interface": interface, "udps": ip_block.get("udps", {})} + data_["udps"].update(interface.get("udps", {})) stream = reg_top_tpl.render(data_).replace(" \n", "\n") path = out_dir / f"{ip_name}{name}_reg_top.sv" path.open("w").write(stream) print(f"Generated {path}.") -class SigType(Enum): - """Used to give a signal different purposes.""" - - NONE = "None" - PadInOut = "PadInOut" - PadInput = "PadInput" - PadOutput = "PadOutput" - Interrupt = "Interrupt" - - def is_pad(self) -> bool: - """Check whether a signal is a pad.""" - return self in [SigType.PadInOut, SigType.PadInput, SigType.PadOutput] - - def is_interrupt(self) -> bool: - """Check whether a signal is a interrupt.""" - return self in [SigType.Interrupt] - - -class IoCombine(Enum): - """May be used when a signal is a pad.""" - - NONE = "None" - Mux = "Mux" - And = "And" - Or = "Or" - - class OtInterfaceBuilder: """OpenTitan Interface Builder.""" @@ -103,18 +82,16 @@ class OtInterfaceBuilder: all_async_clk: bool = True # Whether all registers have async clock in the interface async_registers: list = [(int, str)] # List of all the (index, register) with async clock any_shadowed_reg: bool = False + any_hw_writable_reg: bool = False + any_sw_writable_reg: bool = False reg_index: int = 0 def get_signal(self, sig: node.SignalNode) -> dict: """Parse a signal and return a dict.""" obj = {} obj["name"] = sig.inst_name - kind = sig.get_property("sigtype") - obj["type"] = kind.name - if SigType(kind.name).is_pad(): - obj["width"] = sig.get_property("signalwidth") - if combine := sig.get_property("io_combine"): - obj["combine"] = combine.name + obj["width"] = sig.get_property("signalwidth") + obj.update(self.get_udps(sig)) return obj def parse_array(self, node_: node.AddressableNode) -> list: @@ -176,6 +153,9 @@ def get_mem(self, mem: node.FieldNode) -> dict: if udps := self.get_udps(mem): obj["udps"] = udps + if properties := self.get_native_properties(mem): + obj.update(properties) + self.all_async_clk &= bool(mem.get_property("async_clk", default=False)) self.num_windows += 1 return obj @@ -190,15 +170,19 @@ def get_reg(self, reg: node.RegNode) -> dict: obj["sw_readable"] = reg.has_sw_readable obj["sw_writable"] = reg.has_sw_writable obj["swmod"] = reg.get_property("swmod", default=None) - obj["async_clk"] = reg.get_property("async_clk", default=None) + if async_clk := reg.get_property("async_clk", default=None): + obj["async_clk"] = async_clk.inst_name + if async_rst := reg.get_property("async_rst", default=None): + obj["async_rst"] = async_rst.inst_name obj["external"] = reg.external obj["shadowed"] = reg.get_property("shadowed", default=False) obj["hwre"] = reg.get_property("hwre", default=False) + obj["compacted"] = reg.get_property("compacted", default=False) obj["offsets"] = self.parse_array(reg) array_size = len(obj["offsets"]) self.num_regs += array_size - obj["is_multireg"] = array_size > 1 + obj["is_multireg"] = reg.is_array sw_write_en = False msb = 0 @@ -225,21 +209,42 @@ def get_reg(self, reg: node.RegNode) -> dict: "needs_read_en": opentitan.needs_read_en(obj), "needs_qe": opentitan.needs_qe(obj), "needs_int_qe": opentitan.needs_int_qe(obj), - "fields_no_write_en": opentitan.fields_no_write_en(obj), + "fields_write_en_mask": opentitan.fields_write_en_mask(obj), + "fields_write_en_bits": opentitan.fields_write_en_mask(obj).bit_count(), "is_homogeneous": opentitan.is_homogeneous(obj), } - self.any_async_clk |= bool(obj["async_clk"]) - self.all_async_clk &= bool(obj["async_clk"]) + self.any_async_clk |= bool(obj.get("async_clk", False)) + self.all_async_clk &= bool(obj.get("async_clk", False)) self.any_shadowed_reg |= bool(obj["shadowed"]) + self.any_hw_writable_reg |= bool(obj["hw_writable"]) + self.any_sw_writable_reg |= bool(obj["sw_writable"]) - if bool(obj["async_clk"]): + if bool(obj.get("async_clk", False)): for index in range(array_size): reg_name = reg.inst_name + (f"_{index}" if array_size > 1 else "") self.async_registers.append((self.reg_index + index, reg_name)) self.reg_index += array_size return obj + def parse_signal(self, interface: dict[str, dict], sig: node.SignalNode) -> None: + """Parse a signal node and return a dictionary.""" + signal = self.get_signal(sig) + if "sigtype" not in signal: + interface["signals"].append(signal) + elif opentitan.SigType(signal["sigtype"]).is_pad(): + interface["pads"].append(signal) + elif opentitan.SigType(signal["sigtype"]).is_interrupt(): + interface["interrupts"].append(signal["name"]) + elif opentitan.SigType(signal["sigtype"]).is_alert(): + interface["alerts"].append(signal["name"]) + elif opentitan.SigType(signal["sigtype"]).is_inter_module(): + interface["inter_modules"].append(signal) + elif opentitan.SigType(signal["sigtype"]).is_sync(): + interface["sync_signals"].append(signal) + else: + print(f"WARNING: Unsupported signal type: {signal}.") + def get_paramesters(self, obj: node.AddrmapNode | node.RegfileNode) -> [dict]: """Parse the custom property localparams and return a list of dictionaries.""" return [ @@ -247,18 +252,47 @@ def get_paramesters(self, obj: node.AddrmapNode | node.RegfileNode) -> [dict]: for param in obj.inst.parameters ] + def parse_type(self, key: str, node: dict) -> dict: + """Parse the custom properties and return a list of dictionaries.""" + if isinstance(node, UserStruct): + obj = {} + for k, v in node.members.items(): + obj.update(self.parse_type(k, v)) + return {key: obj} + if isinstance(node, list): + vec = [self.parse_type(key, item) for item in node] + return {key: vec} + if isinstance(node, UserEnum): + return {key: node.name} + if isinstance(node, BuiltinEnum): + return {key: str(node.name)} + + if not isinstance(node, int | bool | str): + print(f"WARNING: Type {type(node)} not fully supported") + + return {key: node} + def get_udps(self, obj: node.AddrmapNode | node.RegfileNode) -> [dict]: - """Parse the customs properties and return a list of dictionaries.""" + """Parse the custom properties and return a list of dictionaries.""" udps = obj.list_properties(include_native=False) if len(udps) < 1: return None res = {} for name in udps: udp = obj.get_property(name) - if isinstance(udp, list) and isinstance(udp[0], UserStruct): - res.update({name: [dict(item.members) for item in udp]}) - else: - res.update({name: udp}) + res.update(self.parse_type(name, udp)) + + return res + + def get_native_properties(self, obj: node.Node) -> [dict]: + """Parse the native properties and return a list of dictionaries.""" + properties = obj.list_properties(include_udp=False) + if len(properties) < 1: + return None + res = {} + for name in properties: + udp = obj.get_property(name) + res.update(self.parse_type(name, udp)) return res @@ -269,12 +303,20 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non self.any_async_clk = False self.all_async_clk = True self.any_shadowed_reg = False + self.any_hw_writable_reg = False + self.any_sw_writable_reg = False self.async_registers.clear() interface = {} if defalt_name: interface["name"] = addrmap.inst_name or defalt_name + if udps := self.get_udps(addrmap): + interface["udps"] = udps + + if properties := self.get_native_properties(addrmap): + interface.update(properties) + interface["regs"] = [] interface["windows"] = [] for child in addrmap.children(): @@ -313,15 +355,11 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non interface["any_async_clk"] = self.any_async_clk interface["all_async_clk"] = self.all_async_clk interface["any_shadowed_reg"] = self.any_shadowed_reg + interface["any_hw_writable_reg"] = self.any_hw_writable_reg + interface["any_sw_writable_reg"] = self.any_sw_writable_reg interface["any_integrity_bypass"] = any( win["integrity_bypass"] for win in interface["windows"] ) - interface["alerts"] = [ - f["name"] - for reg in interface["regs"] - for f in reg["fields"] - if reg["name"] == "ALERT_TEST" - ] return interface def parse_ip_block(self, ip_block: node.AddrmapNode) -> dict: @@ -333,6 +371,9 @@ def parse_ip_block(self, ip_block: node.AddrmapNode) -> dict: if udps := self.get_udps(ip_block): obj["udps"] = udps + if properties := self.get_native_properties(ip_block): + obj.update(properties) + obj["offsets"] = self.parse_array(ip_block) obj["size"] = ip_block.array_stride if ip_block.is_array else ip_block.size @@ -340,19 +381,15 @@ def parse_ip_block(self, ip_block: node.AddrmapNode) -> dict: obj["alerts"] = [] obj["pads"] = [] obj["interrupts"] = [] + obj["signals"] = [] + obj["inter_modules"] = [] + obj["sync_signals"] = [] for child in ip_block.children(): if isinstance(child, node.AddrmapNode): child_obj = self.get_interface(child, DEFAULT_INTERFACE_NAME) obj["interfaces"].append(child_obj) - obj["alerts"].extend(child_obj["alerts"]) elif isinstance(child, node.SignalNode): - signal = self.get_signal(child) - if SigType(signal["type"]).is_pad(): - obj["pads"].append(signal) - elif SigType(signal["type"]).is_interrupt(): - obj["interrupts"].append(signal) - else: - print(f"WARNING: Unsupported signal type: {signal}.") + self.parse_signal(obj, child) elif isinstance(child, node.RegNode | node.MemNode | node.RegfileNode): continue else: @@ -363,7 +400,6 @@ def parse_ip_block(self, ip_block: node.AddrmapNode) -> dict: if len(ip_block.registers()) > 0: interface = self.get_interface(ip_block) obj["interfaces"].append(interface) - obj["alerts"].extend(interface["alerts"]) return obj diff --git a/rdl2ot/src/templates/reg_pkg.sv.tpl b/rdl2ot/src/templates/reg_pkg.sv.tpl index 9edc396..dc96316 100644 --- a/rdl2ot/src/templates/reg_pkg.sv.tpl +++ b/rdl2ot/src/templates/reg_pkg.sv.tpl @@ -50,7 +50,7 @@ package {{ name }}_reg_pkg; /////////////////////////////////////////////// {%- for reg in registers -%} {%- if reg.hw_readable %} - {%- set fields = reg.fields[0:1] if reg.is_homogeneous else reg.fields %} + {%- set fields = reg.fields[0:1] if reg.opentitan.is_homogeneous else reg.fields %} {%- set indent = " " if fields|length > 1 %} typedef struct packed { @@ -78,7 +78,7 @@ package {{ name }}_reg_pkg; {%- if registers|length > 0 %} {%- for reg in registers %} {%- if reg.hw_writable %} - {%- set fields = reg.fields[0:1] if reg.is_homogeneous else reg.fields %} + {%- set fields = reg.fields[0:1] if reg.opentitan.is_homogeneous else reg.fields %} {%- set indent = " " if fields|length > 1 %} typedef struct packed { @@ -111,9 +111,9 @@ package {{ name }}_reg_pkg; typedef struct packed { {%- set printed.header = true %} {%- endif %} - {%- set width = reg.fields|length * reg.offsets|length if reg.is_homogeneous and reg.is_multifields else reg.offsets|length %} - {%- set bits = " [{}:0]".format(width - 1) if reg.is_multireg %} - {{ name }}_reg2hw_{{ reg.name|lower }}_{{"m" if reg.is_multireg}}reg_t{{ bits }} {{ reg.name|lower }}; + {%- set width = reg.fields|length * reg.offsets|length if reg.opentitan.is_homogeneous and reg.is_multifields else reg.offsets|length %} + {%- set bits = " [{}:0]".format(width - 1) if reg.is_multireg or (reg.opentitan.is_homogeneous and reg.is_multifields) %} + {{ "{}_reg2hw_{}_{}reg_t{} {};".format(name, reg.name, "m" if reg.is_multireg, bits, reg.name)|lower }} {%- endif %} {%- endfor %} {%- if printed.header %} @@ -129,9 +129,9 @@ package {{ name }}_reg_pkg; typedef struct packed { {%- set printed.header = true %} {%- endif %} - {%- set width = reg.fields|length if reg.is_homogeneous and reg.is_multifields else reg.offsets|length %} + {%- set width = reg.fields|length if reg.opentitan.is_homogeneous and reg.is_multifields else reg.offsets|length %} {%- set bits = " [{}:0]".format(width - 1) if reg.is_multireg %} - {{ name }}_hw2reg_{{ reg.name|lower }}_{{"m" if reg.is_multireg}}reg_t{{ bits }} {{ reg.name|lower }}; + {{ "{}_hw2reg_{}_{}reg_t{} {};".format(name, reg.name, "m" if reg.is_multireg, bits, reg.name)|lower }} {%- endif %} {%- endfor %} {%- if printed.header %} diff --git a/rdl2ot/src/templates/reg_top.sv.tpl b/rdl2ot/src/templates/reg_top.sv.tpl index f037b17..8033f91 100644 --- a/rdl2ot/src/templates/reg_top.sv.tpl +++ b/rdl2ot/src/templates/reg_top.sv.tpl @@ -10,10 +10,22 @@ {%- set has_windows = windows|length > 0 %} {%- set has_regs = registers|length > 0 %} {%- set interface_name = ("_" + interface.name|lower) if interface.name %} -{%- set num_regs_digits = interface.num_regs | string | length %} +{%- set num_regs_digits = (interface.num_regs - 1) | string | length %} {%- set clk_name = "aon_" %} - -module {{ name|lower }}{{interface_name}}_reg_top ( +{%- set racl_support = (udps.bus_interface_cfg and udps.bus_interface_cfg.racl_support) %} + +module {{ name|lower }}{{interface_name}}_reg_top {{"(" if not racl_support }} +{%- if racl_support %} + {%- set if_name = interface.name|camelcase if interface.name %} + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1{{"," if racl_support }} + {%- if racl_support %} + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[{{ "{}_reg_pkg::NumRegs{}".format(name|lower, if_name) }}] = + {{ "'{{{}_reg_pkg::NumRegs{}{{0}}}}".format(name|lower, if_name) }} + {%- endif %} + ) ( +{%- endif %} input clk_i, input rst_ni, {%- if interface.any_async_clk %} @@ -36,8 +48,12 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- if has_regs %} // To HW + {%- if interface.any_sw_writable_reg %} output {{ name|lower }}_reg_pkg::{{ name|lower }}{{interface_name}}_reg2hw_t reg2hw, // Write + {%- endif %} + {%- if interface.any_hw_writable_reg %} input {{ name|lower }}_reg_pkg::{{ name|lower }}{{interface_name}}_hw2reg_t hw2reg, // Read + {%- endif %} {%- endif %} {%- if interface.any_shadowed_reg %} @@ -47,6 +63,13 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- endif %} +{%- if racl_support %} + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, +{%- endif %} + // Integrity check errors output logic intg_err_o ); @@ -192,12 +215,10 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- if interface.num_regs > 0 %} assign tl_reg_h2d = tl_socket_h2d[{{ interface.num_windows }}]; assign tl_socket_d2h[{{ interface.num_windows }}] = tl_reg_d2h; - {%- endif %} - +{{ space }} {%- for win in windows %} {%- set win_suff = "[{}]".format(loop.index0) if interface.num_windows > 1 %} - assign tl_win_o{{ win_suff }} = tl_socket_h2d[{{ loop.index0 }}]; assign tl_socket_d2h[{{ loop.index0 }}] = tl_win_i{{ win_suff }}; {%- endfor %} @@ -207,12 +228,12 @@ module {{ name|lower }}{{interface_name}}_reg_top ( .N ({{ num_dsp }}), .HReqPass (1'b1), .HRspPass (1'b1), - .DReqPass ({ {{- num_dsp -}} {1'b1} }), - .DRspPass ({ {{- num_dsp -}} {1'b1} }), + .DReqPass {{"({{{}{{1'b1}}}})".format(num_dsp) }}, + .DRspPass {{"({{{}{{1'b1}}}})".format(num_dsp) }}, .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth ({ {{- num_dsp -}} {4'h0} }), - .DRspDepth ({ {{- num_dsp -}} {4'h0} }), + .DReqDepth {{"({{{}{{4'h0}}}})".format(num_dsp) }}, + .DRspDepth {{"({{{}{{4'h0}}}})".format(num_dsp) }}, .ExplicitErrs (1'b0) ) u_socket ( .clk_i (clk_i), @@ -263,7 +284,10 @@ module {{ name|lower }}{{interface_name}}_reg_top ( .be_o (reg_be), .busy_i (reg_busy), .rdata_i (reg_rdata), - .error_i (reg_error) + {%- if racl_support %} + // Translate RACL error to TLUL error if enabled + {%- endif %} + .error_i (reg_error{{" | (RaclErrorRsp & racl_error_o.valid)" if racl_support }}) ); // cdc oversampling signals @@ -276,17 +300,20 @@ module {{ name|lower }}{{interface_name}}_reg_top ( // or _{wd|we|qs} if field == 1 or 0 {%- endif %} {%- for reg in registers %} + {%- set reindex = namespace(num=0) -%} {%- for offset in reg.offsets %} {%- set multireg_idx = loop.index0 %} {%- set reg_suffix = ('_' ~ multireg_idx|string) if reg.offsets|length > 1 %} {%- if reg.opentitan.needs_read_en %} - logic {{ reg.name|lower }}{{ reg_suffix }}_re; + logic {{ reg.name|lower ~ reg_suffix }}_re; {%- endif %} {%- if reg.opentitan.needs_write_en %} - logic {{ reg.name|lower }}{{ reg_suffix }}_we; + logic {{ reg.name|lower ~ reg_suffix }}_we; {%- endif %} {%- for field in reg.fields %} - {%- set field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set _field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set field_name = (('_' ~ field.name|lower) | reindex(reindex.num)) if reg.is_multifields and reg.compacted else _field_name %} + {%- set reindex.num = reindex.num + 1 %} {%- set width = "[{}:0] ".format(field.width - 1) if field.width > 1 %} {%- if not reg.async_clk and field.sw_readable %} logic {{ width ~ reg.name|lower ~ reg_suffix ~ field_name }}_qs; @@ -307,7 +334,6 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- endfor %} {%- if interface.any_async_clk %} - // Define register CDC handling. // CDC handling is done on a per-reg instead of per-field boundary. {{ space }} @@ -414,18 +440,21 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- endif %} {%- if has_regs %} -{{ space }} // Register instances {%- endif %} {%- set assign = namespace(expr="") %} {%- for reg in registers %} {{- space }} + {%- set reindex = namespace(num=0) -%} {%- for offset in reg.offsets %} {%- set multireg_idx = loop.index0 if reg.is_multireg %} {%- set multireg_suffix = "_{}".format(multireg_idx) if reg.offsets|length > 1 %} {%- set regname = reg.name|lower ~ multireg_suffix %} {%- set clk_prefix = clk_name if reg.async_clk %} + {%- set num_flds_wr_en = reg.opentitan.fields_write_en_bits %} + {%- set flds_wr_en_mask = reg.opentitan.fields_write_en_mask %} + {%- set num_flds = reg.fields|length %} {%- if reg.is_multireg %} // Subregister {{multireg_idx}} of Multireg {{ reg.name|lower }} {%- endif %} @@ -439,22 +468,26 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- endif %} {%- if reg.opentitan.needs_qe %} {%- if reg.external %} - {%- if reg.opentitan.fields_no_write_en > 0 %} + {%- if num_flds_wr_en < num_flds and num_flds_wr_en > 0 %} // This ignores QEs that are set to constant 0 due to read-only fields. logic unused_{{ reg.name|lower }}_flds_we; - assign unused_{{ reg.name|lower }}_flds_we = {{ "^({}_flds_we & {}'h{:x})".format(reg.name|lower, reg.fields|length, reg.opentitan.fields_no_write_en ) }}; + assign unused_{{ reg.name|lower }}_flds_we = {{ "^({}_flds_we & {}'h{:x})".format(reg.name|lower, num_flds, flds_wr_en_mask ) }}; + {%- endif %} + {%- if reg.external and num_flds_wr_en == num_flds %} + // In case all fields are read-only the aggregated register QE will be zero as well. {%- endif %} {%- set right_expr = "{}_flds_we".format(regname) %} - {%- set right_expr = right_expr ~ (" | {}'h{:x}".format(reg.fields|length, reg.opentitan.fields_no_write_en ) if reg.opentitan.fields_no_write_en > 0) %} - assign {{regname }}_qe = &{{ "({})".format(right_expr) if reg.opentitan.fields_no_write_en > 0 else "{}".format(right_expr) }}; + {%- set right_expr = "({} | {}'h{:x})".format(right_expr, num_flds, flds_wr_en_mask ) if reg.external and num_flds_wr_en < num_flds and num_flds_wr_en > 0 else right_expr %} + assign {{regname }}_qe = &{{ "{}".format(right_expr) if num_flds_wr_en > 0 else "{}".format(right_expr) }}; {%- else %} prim_flop #( .Width(1), .ResetValue(0) ) u_{{ reg.name|lower ~ loop.index0}}_qe ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .d_i(&({{ regname }}_flds_we {{"| {}'h{:x}".format(reg.fields|length, reg.opentitan.fields_no_write_en) if reg.opentitan.fields_no_write_en }})), + .clk_i({{reg.async_clk|lower if reg.async_clk else "clk_i"}}), + .rst_ni({{reg.async_rst|lower if reg.async_rst else "rst_ni"}}), + {%- set right_expr = " | {}'h{:x})".format(num_flds, num_flds_wr_en) if num_flds_wr_en %} + .d_i({{"&{}{}_flds_we{}".format("(" if num_flds_wr_en, regname, right_expr) }}), .q_o({{ regname }}_qe) ); {%- endif %} @@ -475,50 +508,71 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- set assign.expr = "prim_mubi_pkg::mubi{}_test_true_strict(prim_mubi_pkg::mubi{}_t'({}_qs))".format(width, width, wr_en_sig_name)|lower %} {%- endif %} {%- endif %} - assign {{ clk_prefix ~ regname }}_gated_we = {{ clk_prefix ~ regname }}_we & {{ assign.expr }}; + {%- set assignment = " assign {}{}_gated_we = {}{}_we & {};".format(clk_prefix, regname, clk_prefix, regname, assign.expr) %} +{{assignment if assignment|length < 100 else assignment|replace("= ", "=\n ")}} {%- endif %} {%- for field in reg.fields %} - {%- set field_name = "_{}{}".format(field.name, multireg_suffix)|lower if reg.is_multifields %} + {%- set _field_name = "_{}{}{}".format(field.name, multireg_suffix, reg_suffix)|lower if reg.is_multifields and not reg.compacted %} + {%- set field_name = (("_" ~ field.name) | reindex(reindex.num) | lower) if reg.is_multifields and reg.compacted else _field_name %} {%- set property = ".{}".format(field.name)|lower if reg.is_multifields and not reg.opentitan.is_homogeneous %} {%- set bit_index = "[{}:{}]".format(field.msb, field.lsb) if field.msb != field.lsb else "[{}]".format(field.msb) %} {%- if reg.is_multifields %} - // F{{ '[{}{}]: {}:{}'.format(field.name, multireg_suffix, field.msb, field.lsb)|lower }} + // F{{ '[{}]: {}:{}'.format(field_name|trim("_"), field.msb, field.lsb)|lower }} {%- endif %} prim_subreg{{ '_ext' if reg.external else ('_shadow' if reg.shadowed) }} #( - .DW ({{ field.width }}) + {%- set align_width = 4 if reg.external else 6 %} + .DW{{ "{space:>{width}}({num})".format(space=" ", num=field.width, width=align_width) }} {%- if not reg.external -%} , .SwAccess(prim_subreg_pkg::SwAccess{{ field.opentitan.reggen_sw_access }}), .RESVAL ({{ "{}'h{:x}".format(field.width, (field.reset if field.reset else 0)) }}), .Mubi (1'b{{ ("MultiBitBool" in field.encode)|int }}) {%- endif %} - ) u_{{ regname ~ field_name }} ( + ) u_{{ regname ~ field_name}} ( {%- if not reg.external %} .clk_i (clk_{{ clk_prefix if reg.async_clk }}i), .rst_ni (rst_{{ clk_prefix if reg.async_clk }}ni), - {%- if reg.shadowed %} + {%- if reg.shadowed %} .rst_shadowed_ni (rst_shadowed_ni), - {%- endif %} + {%- endif %} {%- endif %} {{- space }} - {%- set idx = loop.index0 if reg.opentitan.is_homogeneous and reg.is_multifields else multireg_idx %} - {%- set sig_name = (reg.name ~ ("[{}]".format(idx) if reg.is_multireg) ~ property)|lower -%} - {%- set suffix = "_int" if reg.async_clk %} + {%- set _idx = loop.index0 if reg.opentitan.is_homogeneous and reg.is_multifields else multireg_idx %} + {%- set idx = reindex.num if reg.compacted else _idx %} + {%- set reindex.num = reindex.num + 1 %} + {%- set sig_name = (reg.name ~ ("[{}]".format(idx) if reg.is_multireg or (reg.opentitan.is_homogeneous and reg.is_multifields)) ~ property)|lower -%} + {%- set suffix = "_int" if reg.async_clk %} + {%- if not reg.external %} + + // from register interface + {%- endif %} {%- if reg.external or reg.shadowed %} .re ({{ "{}{}{}_re".format(clk_prefix, reg.name, multireg_suffix)|lower if field.sw_readable or reg.shadowed else "1'b0" }}), {%- endif %} .we ({{ "{}{}_{}".format(clk_prefix ~ regname, ("_gated" if field.sw_write_en), "re" if field.clear_onread else "we") if field.sw_writable else "1'b0" }}), .wd ({{ "{}{}{}_wd{}{}".format(clk_prefix, regname, field_name if not reg.async_clk, "ata" if reg.async_clk, bit_index if reg.async_clk) if field.sw_writable else "'0" }}), {%- if not reg.external %} + + // from internal hardware + {%- endif %} + {%- if not reg.external %} .de ({{ "hw2reg.{}.de".format(sig_name ) if field.hw_writable else "1'b0" }}), {%- endif %} .d ({{ "hw2reg.{}.d".format(sig_name ) if field.hw_writable else "'0" }}), + {%- if not reg.external %} + + // to internal hardware + {%- endif %} {%- if reg.external %} .qre ({{ "reg2hw.{}.re".format(sig_name) if reg.hwre or reg.shadowed }}), {%- endif %} .qe ({{ "{}_flds_we[{}]".format(regname, loop.index0) if reg.opentitan.needs_int_qe }}), .q ({{ "reg2hw.{}.q".format(sig_name) if field.hw_readable }}), .ds ({{ "{}{}{}_ds{}".format(clk_prefix, regname, field_name, suffix) if reg.async_clk and reg.hw_writable }}), + {%- if not reg.external %} + + // to register interface (read) + {%- endif %} .qs ({{ "{}{}_qs{}".format(clk_prefix, regname ~ field_name, suffix) if field.sw_readable }}) {%- if not reg.external and reg.shadowed -%} , @@ -549,7 +603,40 @@ module {{ name|lower }}{{interface_name}}_reg_top ( {%- if has_regs %} logic [{{interface.num_regs - 1 }}:0] addr_hit; + {%- if racl_support %} + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [{{interface.num_regs - 1 }}:0] racl_addr_hit_read; + logic [{{interface.num_regs - 1 }}:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + {%- if udps.static_racl_support %} + // For the static RACL assignment for racl_ctrl only one role (ROT_PRIVATE) is used, + // leaving others unread. Intentionally read them to avoid linting errors. + logic unused_role_vec; + assign unused_role_vec = ^racl_role_vec; + {%- endif %} + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + {%- endif %} always_comb begin + {%- if racl_support %} + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + {%- endif %} {%- set ns = namespace(counter=0) %} {%- for reg in registers %} {%- for offset in reg.offsets %} @@ -558,22 +645,65 @@ module {{ name|lower }}{{interface_name}}_reg_top ( addr_hit[{{ index }}] = (reg_addr == {{ (name ~ '_' ~ reg.name)|upper }}{% if reg.offsets|length > 1 %}_{{ loop.index0 }}{% endif %}_OFFSET); {%- endfor %} {%- endfor %} + {%- if racl_support %} + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < {{interface.num_regs}}; slice_idx++) begin + {%- if not udps.static_racl_support %} + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + {%- else %} + // Static RACL protection with ROT_PRIVATE policy + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(top_racl_pkg::RACL_POLICY_ROT_PRIVATE_RD & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(top_racl_pkg::RACL_POLICY_ROT_PRIVATE_WR & racl_role_vec)); + {%- endif %} + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + {%- endif %} end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + {%- if racl_support %} + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + {%- endif %} + // Check sub-word write is permitted always_comb begin wr_err = (reg_we & {%- set ns = namespace(counter=0) %} {%- set interface_name = ("_" + interface.name|lower) if interface.name -%} + {%- set wr_addr_hit = "racl_addr_hit_write" if racl_support else "addr_hit" %} + {%- set rd_addr_hit = "racl_addr_hit_read" if racl_support else "addr_hit" %} {%- for reg in registers %} {%- set outer_loop = loop -%} {%- for offset in reg.offsets %} {%- set index = "{num:>{width}}".format(num=ns.counter, width=num_regs_digits) %} {%- set ns.counter = ns.counter + 1 %} {{"(" if loop.first and outer_loop.first else " " -}} - (addr_hit[{{ index }}] & (|({{ (name ~ interface_name)|upper}}_PERMIT[{{ index }}] & ~reg_be))) + {{"({}[{}] & (|({}_PERMIT[{}] & ~reg_be)))".format(wr_addr_hit , index,(name ~ interface_name)|upper, index ) }} {%- if loop.last and outer_loop.last %}));{% else %} |{% endif %} {%- endfor %} {%- endfor %} @@ -582,28 +712,33 @@ module {{ name|lower }}{{interface_name}}_reg_top ( // Generate write-enables {%- set ns = namespace(re_index=0) -%} {%- for reg in registers %} + {%- set reindex = namespace(num=0) -%} {%- for offset in reg.offsets %} {%- set reg_suffix = ('_' ~ loop.index0|string) if reg.offsets|length > 1 %} {%- set regname = "{}{}".format(reg.name, reg_suffix)|lower %} {%- if reg.opentitan.needs_read_en %} - assign {{ regname }}_re = addr_hit[{{ ns.re_index }}] & reg_re & !reg_error; + assign {{ regname }}_re = {{rd_addr_hit}}[{{ ns.re_index }}] & reg_re & !reg_error; {%- endif %} {%- if reg.opentitan.needs_write_en %} - assign {{ regname }}_we = addr_hit[{{ ns.re_index }}] & reg_we & !reg_error; + assign {{ regname }}_we = {{wr_addr_hit}}[{{ ns.re_index }}] & reg_we & !reg_error; +{{space}} {%- endif %} {%- set ns.re_index = ns.re_index + 1 %} {%- for field in reg.fields %} {%- if field.sw_writable and not reg.async_clk %} - {%- set field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set _field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set field_name = (('_' ~ field.name|lower) | reindex(reindex.num)) if reg.is_multifields and reg.compacted else _field_name%} + {%- set reindex.num = reindex.num + 1 %} {%- set left_expr = "{}{}{}".format(reg.name, reg_suffix, field_name)|lower %} {%- set bit_index = "{}:{}".format(field.msb, field.lsb) if field.width > 1 else field.msb %} {%- set right_expr = "'1" if field.clear_onread else "reg_wdata[{}]".format(bit_index) %} assign {{ left_expr }}_wd = {{ right_expr }}; +{{space}} {%- endif %} {%- endfor %} {%- endfor %} - {% endfor %} - + {%- endfor %} +{{space}} // Assign write-enables to checker logic vector. always_comb begin {%- set ns = namespace(counter=0) %} @@ -623,22 +758,27 @@ module {{ name|lower }}{{interface_name}}_reg_top ( unique case (1'b1) {%- set ns = namespace(counter=0) %} {%- for reg in registers %} + {%- set reindex = namespace(num=0) -%} {%- for offset in reg.offsets %} - {%- set reg_suffix = ('_' ~ loop.index0|string) if reg.offsets|length > 1 and not (reg.opentitan.is_homogeneous and reg.is_multifields) %} - addr_hit[{{ ns.counter }}]: begin + {%- set reg_suffix = ('_' ~ loop.index0|string) if reg.offsets|length > 1 %} + {{rd_addr_hit}}[{{ ns.counter }}]: begin {%- set ns.counter = ns.counter + 1 %} {%- if reg.async_clk %} reg_rdata_next = DW'({{ "{}{}_qs".format(reg.name, reg_suffix)|lower }}); {%- else %} {%- for field in reg.fields %} - {%- set field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set _field_name = ('_' ~ field.name|lower ~ reg_suffix) if reg.is_multifields %} + {%- set field_name = (('_' ~ field.name) | reindex(reindex.num)) if reg.is_multifields and reg.compacted else _field_name %} + {%- set reindex.num = reindex.num + 1 %} {%- set index = "{}:{}".format(field.msb, field.lsb) if field.width > 1 else field.msb %} {%- set expr = "{}{}{}_qs".format(reg.name, reg_suffix, field_name)|lower if field.sw_readable else "'0" %} reg_rdata_next{{ "[{}] = {}".format(index, expr)|lower }}; {%- endfor %} {%- endif %} end + {%- if not reg.async_clk %} {{ space }} + {%- endif %} {%- endfor -%} {%- endfor %} default: begin @@ -738,6 +878,10 @@ module {{ name|lower }}{{interface_name}}_reg_top ( logic unused_be; assign unused_wdata = ^reg_wdata; assign unused_be = ^reg_be; +{%- if racl_support %} + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; +{%- endif %} // Assertions for Register Interface `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) diff --git a/rdl2ot/tests/snapshots/lc_ctrl.rdl b/rdl2ot/tests/snapshots/lc_ctrl.rdl index 56c977e..882ebeb 100644 --- a/rdl2ot/tests/snapshots/lc_ctrl.rdl +++ b/rdl2ot/tests/snapshots/lc_ctrl.rdl @@ -14,6 +14,24 @@ addrmap lc_ctrl #( longint NumManufStateWords = 8, longint NumAlerts = 3 ){ + signal { + desc = ""; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_PROG_ERROR; + + signal { + desc = ""; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_STATE_ERROR; + + signal { + desc = ""; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_BUS_INTEG_ERROR; + addrmap { external reg { field { diff --git a/rdl2ot/tests/snapshots/lc_ctrl_regs_reg_top.sv b/rdl2ot/tests/snapshots/lc_ctrl_regs_reg_top.sv index 2270744..54b1827 100644 --- a/rdl2ot/tests/snapshots/lc_ctrl_regs_reg_top.sv +++ b/rdl2ot/tests/snapshots/lc_ctrl_regs_reg_top.sv @@ -225,7 +225,6 @@ module lc_ctrl_regs_reg_top ( logic [31:0] manuf_state_6_qs; logic manuf_state_7_re; logic [31:0] manuf_state_7_qs; - // Register instances // R[alert_test]: V(True) logic alert_test_qe; @@ -464,20 +463,28 @@ module lc_ctrl_regs_reg_top ( // R[claim_transition_if_regwen]: V(False) prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW0C), .RESVAL (1'h1), .Mubi (1'b0) ) u_claim_transition_if_regwen ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (claim_transition_if_regwen_we), .wd (claim_transition_if_regwen_wd), + + // from internal hardware .de (1'b0), .d ('0), + + // to internal hardware .qe (), .q (), .ds (), + + // to register interface (read) .qs (claim_transition_if_regwen_qs) ); @@ -1210,62 +1217,71 @@ module lc_ctrl_regs_reg_top ( // Generate write-enables assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_fatal_prog_error_wd = reg_wdata[0]; + assign alert_test_fatal_state_error_wd = reg_wdata[1]; + assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2]; - + assign status_re = addr_hit[1] & reg_re & !reg_error; - assign claim_transition_if_regwen_we = addr_hit[2] & reg_we & !reg_error; + assign claim_transition_if_regwen_wd = reg_wdata[0]; - + assign claim_transition_if_re = addr_hit[3] & reg_re & !reg_error; assign claim_transition_if_we = addr_hit[3] & reg_we & !reg_error; + assign claim_transition_if_wd = reg_wdata[7:0]; - + assign transition_regwen_re = addr_hit[4] & reg_re & !reg_error; - assign transition_cmd_we = addr_hit[5] & reg_we & !reg_error; + assign transition_cmd_wd = reg_wdata[0]; - + assign transition_ctrl_re = addr_hit[6] & reg_re & !reg_error; assign transition_ctrl_we = addr_hit[6] & reg_we & !reg_error; + assign transition_ctrl_ext_clock_en_wd = reg_wdata[0]; + assign transition_ctrl_volatile_raw_unlock_wd = reg_wdata[1]; - + assign transition_token_0_re = addr_hit[7] & reg_re & !reg_error; assign transition_token_0_we = addr_hit[7] & reg_we & !reg_error; + assign transition_token_0_wd = reg_wdata[31:0]; + assign transition_token_1_re = addr_hit[8] & reg_re & !reg_error; assign transition_token_1_we = addr_hit[8] & reg_we & !reg_error; + assign transition_token_1_wd = reg_wdata[31:0]; + assign transition_token_2_re = addr_hit[9] & reg_re & !reg_error; assign transition_token_2_we = addr_hit[9] & reg_we & !reg_error; + assign transition_token_2_wd = reg_wdata[31:0]; + assign transition_token_3_re = addr_hit[10] & reg_re & !reg_error; assign transition_token_3_we = addr_hit[10] & reg_we & !reg_error; + assign transition_token_3_wd = reg_wdata[31:0]; - + assign transition_target_re = addr_hit[11] & reg_re & !reg_error; assign transition_target_we = addr_hit[11] & reg_we & !reg_error; + assign transition_target_wd = reg_wdata[29:0]; - + assign otp_vendor_test_ctrl_re = addr_hit[12] & reg_re & !reg_error; assign otp_vendor_test_ctrl_we = addr_hit[12] & reg_we & !reg_error; + assign otp_vendor_test_ctrl_wd = reg_wdata[31:0]; - + assign otp_vendor_test_status_re = addr_hit[13] & reg_re & !reg_error; - assign lc_state_re = addr_hit[14] & reg_re & !reg_error; - assign lc_transition_cnt_re = addr_hit[15] & reg_re & !reg_error; - assign lc_id_state_re = addr_hit[16] & reg_re & !reg_error; - assign hw_revision0_re = addr_hit[17] & reg_re & !reg_error; - assign hw_revision1_re = addr_hit[18] & reg_re & !reg_error; - assign device_id_0_re = addr_hit[19] & reg_re & !reg_error; assign device_id_1_re = addr_hit[20] & reg_re & !reg_error; assign device_id_2_re = addr_hit[21] & reg_re & !reg_error; @@ -1274,7 +1290,6 @@ module lc_ctrl_regs_reg_top ( assign device_id_5_re = addr_hit[24] & reg_re & !reg_error; assign device_id_6_re = addr_hit[25] & reg_re & !reg_error; assign device_id_7_re = addr_hit[26] & reg_re & !reg_error; - assign manuf_state_0_re = addr_hit[27] & reg_re & !reg_error; assign manuf_state_1_re = addr_hit[28] & reg_re & !reg_error; assign manuf_state_2_re = addr_hit[29] & reg_re & !reg_error; @@ -1283,7 +1298,6 @@ module lc_ctrl_regs_reg_top ( assign manuf_state_5_re = addr_hit[32] & reg_re & !reg_error; assign manuf_state_6_re = addr_hit[33] & reg_re & !reg_error; assign manuf_state_7_re = addr_hit[34] & reg_re & !reg_error; - // Assign write-enables to checker logic vector. always_comb begin diff --git a/rdl2ot/tests/snapshots/mbx.rdl b/rdl2ot/tests/snapshots/mbx.rdl new file mode 100644 index 0000000..00dd0eb --- /dev/null +++ b/rdl2ot/tests/snapshots/mbx.rdl @@ -0,0 +1,486 @@ +`include "udp.rdl" + +addrmap mbx #( + longint NumAlerts = 2 +){ + bridge = true; + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "logic"; + } DOE_INTR_SUPPORT; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "logic"; + } DOE_INTR_EN; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "logic"; + } DOE_INTR; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "logic"; + } DOE_ASYNC_MSG_SUPPORT; + + signal { + desc = "Incoming RACL policy vector from a racl_ctrl instance.The policy selection vector (parameter) selects the policy for each register."; + signalwidth = 0x1; + sigtype = SigType::InterModRecv; + inter_mod_struct = "racl_policy_vec"; + inter_mod_package = "top_racl_pkg"; + } RACL_POLICIES; + + signal { + desc = "RACL error log information of this module."; + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "racl_error_log"; + inter_mod_package = "top_racl_pkg"; + } RACL_ERROR; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReqRsp; + inter_mod_struct = "tl"; + inter_mod_package = "tlul_pkg"; + } SRAM_TL_H; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReqRsp; + inter_mod_struct = "tl"; + inter_mod_package = "tlul_pkg"; + } CORE_TL_D; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReqRsp; + inter_mod_struct = "tl"; + inter_mod_package = "tlul_pkg"; + } SOC_TL_D; + + signal { + desc = "A new object was received in the inbound mailbox."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } MBX_READY; + + signal { + desc = "An abort request was received from the requester."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } MBX_ABORT; + + signal { + desc = "The mailbox instance generated an error."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } MBX_ERROR; + + signal { + desc = "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected."; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_FAULT; + + signal { + desc = "This recoverable alert is triggered when memory with invalid ECC (e.g., uninitialized memory) or at an invalid address is accessed."; + signalwidth = 0x1; + sigtype = SigType::Alert; + } RECOV_FAULT; + + signal { + signalwidth = 0x1; + sigtype = SigType::Sync; + } CLK_I; + + signal { + signalwidth = 0x1; + sigtype = SigType::Sync; + } RST_NI; + + addrmap { + bus_interface_cfg = BusInterfaceCfg'{ + racl_support : true, + direction : BusDirection::Device, + protocol : BusProtocol::TlUl, + hier_path : "u_hostif.u_regs" + }; + reg { + desc = "Interrupt State Register"; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "A new object was received in the inbound mailbox."; + } MBX_READY[0:0]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "An abort request was received from the requester."; + } MBX_ABORT[1:1]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "The mailbox instance generated an error."; + } MBX_ERROR[2:2]; + } INTR_STATE @ 0x0; + + reg { + desc = "Interrupt Enable Register"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.mbx_ready is set."; + } MBX_READY[0:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.mbx_abort is set."; + } MBX_ABORT[1:1]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.mbx_error is set."; + } MBX_ERROR[2:2]; + } INTR_ENABLE @ 0x4; + + external reg { + desc = "Interrupt Test Register"; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.mbx_ready to 1."; + } MBX_READY[0:0]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.mbx_abort to 1."; + } MBX_ABORT[1:1]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.mbx_error to 1."; + } MBX_ERROR[2:2]; + } INTR_TEST @ 0x8; + + external reg { + desc = "Alert Test Register"; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_FAULT[0:0]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to trigger one alert event of this kind."; + } RECOV_FAULT[1:1]; + } ALERT_TEST @ 0xC; + + external reg { + desc = "DOE mailbox control register visible to OpenTitan"; + field { + sw = rw; + hw = rw; + reset = 0x0; + swmod = true; + desc = "Alias of the DoE mailbox abort bit"; + } ABORT[0:0]; + field { + sw = rw; + hw = rw; + reset = 0x0; + swmod = true; + desc = "Set by firmware to signal an error, e.g. unable to provide a response to request.Set by hardware, on SYS.WDATA or SYS.RDATA performing an invalid access.Cleared by the hardware when SYS sets CONTROL.ABORT."; + } ERROR[1:1]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Indicates an async message request"; + } SYS_ASYNC_MSG[3:3]; + } CONTROL @ 0x10; + + external reg { + desc = "DOE mailbox status register visible to OpenTitan"; + field { + sw = r; + hw = w; + reset = 0x1; + desc = "Alias of the DoE mailbox busy bit"; + } BUSY[0:0]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Alias of the DoE mailbox interrupt status bit"; + } SYS_INTR_STATE[1:1]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Alias of the DoE mailbox interrupt enable bit"; + } SYS_INTR_ENABLE[2:2]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Alias of the DoE mailbox async message support enable bit"; + } SYS_ASYNC_ENABLE[3:3]; + } STATUS @ 0x14; + + reg { + desc = "Used to lock the inbound/outbound base/limit configuration registers."; + field { + sw = rw; + onwrite = wzc; + hw = na; + reset = 0x6; + desc = "Once cleared the mailbox inbound/outbound base/limit registers will be locked until the next reset.Default Value = kMultiBitBool4True -> Unlocked at reset."; + encode = MultiBitBool4; + } REGWEN[3:0]; + } ADDRESS_RANGE_REGWEN @ 0x18; + + reg { + desc = "Used to mark the inbound/outbound base/limit configuration registers to have a valid configuration."; + field { + sw = rw; + hw = r; + reset = false; + swmod = true; + desc = "Once set the mailbox inbound/outbound base/limit registers are valid."; + } RANGE_VALID[0:0]; + } ADDRESS_RANGE_VALID @ 0x1C; + + reg { + desc = "Base address of SRAM region, which is used to back up the inbound mailbox data.This address is 4-byte aligned, the lower 2 bits are ignored."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Base address of SRAM region, which is used to back up the inbound mailbox data."; + } BASE_ADDRESS[31:2]; + } INBOUND_BASE_ADDRESS @ 0x20; + + reg { + desc = "Inclusive end address of the inbound mailbox memory range in the private SRAM.This address is 4-byte aligned and it specifies the start address of the final validDWORD location. The lower 2 bits are ignored."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Limit Address to mark the end of the inbound mailbox memory range in the private SRAM."; + } LIMIT[31:2]; + } INBOUND_LIMIT_ADDRESS @ 0x24; + + external reg { + desc = "Write pointer for the next inbound DWORD write (32 bits).Pointer is initialized to the Inbox memory base address before the start of a transfer.Inbox handler maintains the updated pointer as data DWORDs are received by the DOE inbox.This pointer is 4-byte aligned; the lower 2 bits are always zero."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Write pointer for the next inbound data write."; + } INBOUND_WRITE_PTR[31:2]; + } INBOUND_WRITE_PTR @ 0x28; + + reg { + desc = "Base address of SRAM region, which is used to buffer the outbound mailbox data.This address is 4-byte aligned, the lower 2 bits are ignored."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Base address of SRAM region, which is used to buffer the outbound mailbox data."; + } BASE_ADDRESS[31:2]; + } OUTBOUND_BASE_ADDRESS @ 0x2C; + + reg { + desc = "Inclusive end address of the outbound mailbox memory range in the private SRAM.This address is 4-byte aligned and it specifies the start address of the final validDWORD location. The lower 2 bits are ignored."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Limit Address to mark the end of the outbound mailbox memory range in the private SRAM."; + } LIMIT[31:2]; + } OUTBOUND_LIMIT_ADDRESS @ 0x30; + + external reg { + desc = "Read pointer for the next outbound DWORD read.Pointer is initialized to the Outbox memory base address before the start of an outgoingobject transfer. Outbox handler maintains the updated pointer as data DWORDs are readfrom the DOE instance by the requester.This pointer is 4-byte aligned; the lower 2 bits are always zero."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Read pointer for the next outbound data read."; + } OUTBOUND_READ_PTR[31:2]; + } OUTBOUND_READ_PTR @ 0x34; + + reg { + desc = "Indicates the size of the data object to be transferred out.Note that this size specifies the number of DWORDs (32 bits).Maximum size supported by any OT DOE instance is 1024 DWORDs."; + field { + sw = rw; + hw = rw; + reset = 0x0; + swmod = true; + desc = "Indicates the size of the data object to be transferred out in 4-byte words."; + } CNT[10:0]; + } OUTBOUND_OBJECT_SIZE @ 0x38; + + external reg { + desc = "Software read-only alias of the DOE_INTR_MSG_ADDR register of the SoC interface for convenient access of the OT firmware.Defined only for FW-to-FW mailboxes."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address."; + } DOE_INTR_MSG_ADDR[31:0]; + } DOE_INTR_MSG_ADDR @ 0x3C; + + external reg { + desc = "Software read-only alias of the DOE_INTR_MSG_DATA register of the SoC interface for convenient access of the OT firmware.Defined only for FW-to-FW mailboxes."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register."; + } DOE_INTR_MSG_DATA[31:0]; + } DOE_INTR_MSG_DATA @ 0x40; + + INBOUND_BASE_ADDRESS.BASE_ADDRESS -> mubi_swwe = ADDRESS_RANGE_REGWEN.REGWEN; + INBOUND_LIMIT_ADDRESS.LIMIT -> mubi_swwe = ADDRESS_RANGE_REGWEN.REGWEN; + OUTBOUND_BASE_ADDRESS.BASE_ADDRESS -> mubi_swwe = ADDRESS_RANGE_REGWEN.REGWEN; + OUTBOUND_LIMIT_ADDRESS.LIMIT -> mubi_swwe = ADDRESS_RANGE_REGWEN.REGWEN; + } CORE; + + addrmap { + bus_interface_cfg = BusInterfaceCfg'{ + racl_support : true, + direction : BusDirection::Device, + protocol : BusProtocol::TlUl, + hier_path : "u_sysif.u_regs" + }; + external reg { + desc = "DOE mailbox control register."; + field { + sw = w; + hw = rw; + reset = 0x0; + swmod = true; + desc = "A write of 1 to this bit causes all data object transfer operations associated with this DOE instance to be aborted."; + } ABORT[0:0]; + field { + sw = rw; + hw = rw; + reset = 0x0; + swmod = true; + desc = "If DOE interrupt support is set, when this bit is set and MSI/MSI-X is enabled in MSI capability registers, the DOE instance must issue an MSI/MSI-X interrupt."; + } DOE_INTR_EN[1:1]; + field { + sw = rw; + hw = rw; + reset = 0x0; + swmod = true; + desc = "If DOE Async Message Support is Set, this bit, when Set, enables the use of the DOE Async Message mechanism.When this bit is set, it allows the DOE instance to raise the SOC_STATUS.doe_async_msg_status, indicating an asynchronous message request."; + } DOE_ASYNC_MSG_EN[3:3]; + field { + sw = w; + hw = rw; + reset = 0x0; + swmod = true; + desc = "A write of 1 to this bit indicates to the DOE instance that it can start consuming the data object transferred through the DOE Write Data Mailbox register."; + } GO[31:31]; + } SOC_CONTROL @ 0x8; + + reg { + desc = "DOE mailbox status register"; + field { + sw = r; + hw = rw; + reset = 0x1; + desc = "When Set, this bit indicates the DOE instance is temporarily unable to receive a new data object through the DOE Write Data Mailbox register.This bit is also set by the DOE instance when processing an abort command and remains set until abort handling is complete."; + } BUSY[0:0]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = 0x0; + desc = "This bit is set when an interrupt event occurs. Writing a value of 1 to this bit clears the status bit."; + } DOE_INTR_STATUS[1:1]; + field { + sw = r; + hw = rw; + reset = 0x0; + desc = "When Set, this bit indicates that there has been an internal error associated with data object received, or that a data object has been received for which the DOE instance is unable to provide a response.The transition of this bit from Clear to Set is an interrupt-triggering event."; + } ERROR[2:2]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "This bit, when Set, indicates the DOE instance has one or more asynchronous messages to transfer.The transition of this bit from Clear to Set is an interrupt-triggering event.This bit is set when an interrupt event occurs."; + } DOE_ASYNC_MSG_STATUS[3:3]; + field { + sw = r; + hw = rw; + reset = 0x0; + desc = "When Set, this bit indicates the DOE instance has a data object available to be read by SoC firmware/software.The transition of this bit from Clear to Set is an interrupt-triggering event."; + } READY[31:31]; + } SOC_STATUS @ 0xC; + + reg { + desc = "Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address.Defined only for FW-to-FW mailboxes."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address."; + } DOE_INTR_MSG_ADDR[31:0]; + } SOC_DOE_INTR_MSG_ADDR @ 0x18; + + reg { + desc = "Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register.Defined only for FW-to-FW mailboxes."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register."; + } DOE_INTR_MSG_DATA[31:0]; + } SOC_DOE_INTR_MSG_DATA @ 0x1C; + + external mem { + memwidth = 0x20; + mementries = 0x1; + sw = rw; + } WDATA @ 0x10; + + external mem { + memwidth = 0x20; + mementries = 0x1; + sw = rw; + } RDATA @ 0x14; + + } SOC; + +}; diff --git a/rdl2ot/tests/snapshots/mbx_core_reg_top.sv b/rdl2ot/tests/snapshots/mbx_core_reg_top.sv new file mode 100644 index 0000000..dc8c7b2 --- /dev/null +++ b/rdl2ot/tests/snapshots/mbx_core_reg_top.sv @@ -0,0 +1,1165 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `rdl2ot` + +`include "prim_assert.sv" + +module mbx_core_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[mbx_reg_pkg::NumRegsCore] = + '{mbx_reg_pkg::NumRegsCore{0}} + ) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output mbx_reg_pkg::mbx_core_reg2hw_t reg2hw, // Write + input mbx_reg_pkg::mbx_core_hw2reg_t hw2reg, // Read + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import mbx_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [16:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(17) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_mbx_ready_qs; + logic intr_state_mbx_ready_wd; + logic intr_state_mbx_abort_qs; + logic intr_state_mbx_abort_wd; + logic intr_state_mbx_error_qs; + logic intr_state_mbx_error_wd; + logic intr_enable_we; + logic intr_enable_mbx_ready_qs; + logic intr_enable_mbx_ready_wd; + logic intr_enable_mbx_abort_qs; + logic intr_enable_mbx_abort_wd; + logic intr_enable_mbx_error_qs; + logic intr_enable_mbx_error_wd; + logic intr_test_we; + logic intr_test_mbx_ready_wd; + logic intr_test_mbx_abort_wd; + logic intr_test_mbx_error_wd; + logic alert_test_we; + logic alert_test_fatal_fault_wd; + logic alert_test_recov_fault_wd; + logic control_re; + logic control_we; + logic control_abort_qs; + logic control_abort_wd; + logic control_error_qs; + logic control_error_wd; + logic control_sys_async_msg_wd; + logic status_re; + logic status_busy_qs; + logic status_sys_intr_state_qs; + logic status_sys_intr_enable_qs; + logic status_sys_async_enable_qs; + logic address_range_regwen_we; + logic [3:0] address_range_regwen_qs; + logic [3:0] address_range_regwen_wd; + logic address_range_valid_we; + logic address_range_valid_qs; + logic address_range_valid_wd; + logic inbound_base_address_we; + logic [29:0] inbound_base_address_qs; + logic [29:0] inbound_base_address_wd; + logic inbound_limit_address_we; + logic [29:0] inbound_limit_address_qs; + logic [29:0] inbound_limit_address_wd; + logic inbound_write_ptr_re; + logic [29:0] inbound_write_ptr_qs; + logic outbound_base_address_we; + logic [29:0] outbound_base_address_qs; + logic [29:0] outbound_base_address_wd; + logic outbound_limit_address_we; + logic [29:0] outbound_limit_address_qs; + logic [29:0] outbound_limit_address_wd; + logic outbound_read_ptr_re; + logic [29:0] outbound_read_ptr_qs; + logic outbound_object_size_we; + logic [10:0] outbound_object_size_qs; + logic [10:0] outbound_object_size_wd; + logic doe_intr_msg_addr_re; + logic [31:0] doe_intr_msg_addr_qs; + logic doe_intr_msg_data_re; + logic [31:0] doe_intr_msg_data_qs; + // Register instances + // R[intr_state]: V(False) + // F[mbx_ready]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_mbx_ready ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_mbx_ready_wd), + + // from internal hardware + .de (hw2reg.intr_state.mbx_ready.de), + .d (hw2reg.intr_state.mbx_ready.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.mbx_ready.q), + .ds (), + + // to register interface (read) + .qs (intr_state_mbx_ready_qs) + ); + + // F[mbx_abort]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_mbx_abort ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_mbx_abort_wd), + + // from internal hardware + .de (hw2reg.intr_state.mbx_abort.de), + .d (hw2reg.intr_state.mbx_abort.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.mbx_abort.q), + .ds (), + + // to register interface (read) + .qs (intr_state_mbx_abort_qs) + ); + + // F[mbx_error]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_mbx_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_mbx_error_wd), + + // from internal hardware + .de (hw2reg.intr_state.mbx_error.de), + .d (hw2reg.intr_state.mbx_error.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.mbx_error.q), + .ds (), + + // to register interface (read) + .qs (intr_state_mbx_error_qs) + ); + + + // R[intr_enable]: V(False) + // F[mbx_ready]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_mbx_ready ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_mbx_ready_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.mbx_ready.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_mbx_ready_qs) + ); + + // F[mbx_abort]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_mbx_abort ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_mbx_abort_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.mbx_abort.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_mbx_abort_qs) + ); + + // F[mbx_error]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_mbx_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_mbx_error_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.mbx_error.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_mbx_error_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [2:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[mbx_ready]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_mbx_ready ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_mbx_ready_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.mbx_ready.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.mbx_ready.qe = intr_test_qe; + + // F[mbx_abort]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_mbx_abort ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_mbx_abort_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.mbx_abort.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.mbx_abort.qe = intr_test_qe; + + // F[mbx_error]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_mbx_error ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_mbx_error_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[2]), + .q (reg2hw.intr_test.mbx_error.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.mbx_error.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + // F[recov_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.recov_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_fault.qe = alert_test_qe; + + + // R[control]: V(True) + logic control_qe; + logic [2:0] control_flds_we; + assign control_qe = &control_flds_we; + // F[abort]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_control_abort ( + .re (control_re), + .we (control_we), + .wd (control_abort_wd), + .d (hw2reg.control.abort.d), + .qre (), + .qe (control_flds_we[0]), + .q (reg2hw.control.abort.q), + .ds (), + .qs (control_abort_qs) + ); + assign reg2hw.control.abort.qe = control_qe; + + // F[error]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_control_error ( + .re (control_re), + .we (control_we), + .wd (control_error_wd), + .d (hw2reg.control.error.d), + .qre (), + .qe (control_flds_we[1]), + .q (reg2hw.control.error.q), + .ds (), + .qs (control_error_qs) + ); + assign reg2hw.control.error.qe = control_qe; + + // F[sys_async_msg]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_control_sys_async_msg ( + .re (1'b0), + .we (control_we), + .wd (control_sys_async_msg_wd), + .d ('0), + .qre (), + .qe (control_flds_we[2]), + .q (reg2hw.control.sys_async_msg.q), + .ds (), + .qs () + ); + assign reg2hw.control.sys_async_msg.qe = control_qe; + + + // R[status]: V(True) + // F[busy]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_status_busy ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.busy.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_busy_qs) + ); + + // F[sys_intr_state]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_status_sys_intr_state ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sys_intr_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sys_intr_state_qs) + ); + + // F[sys_intr_enable]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_status_sys_intr_enable ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sys_intr_enable.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sys_intr_enable_qs) + ); + + // F[sys_async_enable]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_status_sys_async_enable ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.sys_async_enable.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_sys_async_enable_qs) + ); + + + // R[address_range_regwen]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_address_range_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (address_range_regwen_we), + .wd (address_range_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (address_range_regwen_qs) + ); + + + // R[address_range_valid]: V(False) + logic address_range_valid_qe; + logic [0:0] address_range_valid_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_address_range_valid0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&address_range_valid_flds_we), + .q_o(address_range_valid_qe) + ); + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_address_range_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (address_range_valid_we), + .wd (address_range_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (address_range_valid_flds_we[0]), + .q (reg2hw.address_range_valid.q), + .ds (), + + // to register interface (read) + .qs (address_range_valid_qs) + ); + assign reg2hw.address_range_valid.qe = address_range_valid_qe; + + + // R[inbound_base_address]: V(False) + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_inbound_base_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inbound_base_address_we), + .wd (inbound_base_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.inbound_base_address.q), + .ds (), + + // to register interface (read) + .qs (inbound_base_address_qs) + ); + + + // R[inbound_limit_address]: V(False) + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_inbound_limit_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inbound_limit_address_we), + .wd (inbound_limit_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.inbound_limit_address.q), + .ds (), + + // to register interface (read) + .qs (inbound_limit_address_qs) + ); + + + // R[inbound_write_ptr]: V(True) + prim_subreg_ext #( + .DW (30) + ) u_inbound_write_ptr ( + .re (inbound_write_ptr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.inbound_write_ptr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (inbound_write_ptr_qs) + ); + + + // R[outbound_base_address]: V(False) + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_outbound_base_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (outbound_base_address_we), + .wd (outbound_base_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.outbound_base_address.q), + .ds (), + + // to register interface (read) + .qs (outbound_base_address_qs) + ); + + + // R[outbound_limit_address]: V(False) + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_outbound_limit_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (outbound_limit_address_we), + .wd (outbound_limit_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.outbound_limit_address.q), + .ds (), + + // to register interface (read) + .qs (outbound_limit_address_qs) + ); + + + // R[outbound_read_ptr]: V(True) + prim_subreg_ext #( + .DW (30) + ) u_outbound_read_ptr ( + .re (outbound_read_ptr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.outbound_read_ptr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (outbound_read_ptr_qs) + ); + + + // R[outbound_object_size]: V(False) + logic outbound_object_size_qe; + logic [0:0] outbound_object_size_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_outbound_object_size0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&outbound_object_size_flds_we), + .q_o(outbound_object_size_qe) + ); + prim_subreg #( + .DW (11), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (11'h0), + .Mubi (1'b0) + ) u_outbound_object_size ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (outbound_object_size_we), + .wd (outbound_object_size_wd), + + // from internal hardware + .de (hw2reg.outbound_object_size.de), + .d (hw2reg.outbound_object_size.d), + + // to internal hardware + .qe (outbound_object_size_flds_we[0]), + .q (reg2hw.outbound_object_size.q), + .ds (), + + // to register interface (read) + .qs (outbound_object_size_qs) + ); + assign reg2hw.outbound_object_size.qe = outbound_object_size_qe; + + + // R[doe_intr_msg_addr]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_doe_intr_msg_addr ( + .re (doe_intr_msg_addr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.doe_intr_msg_addr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (doe_intr_msg_addr_qs) + ); + + + // R[doe_intr_msg_data]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_doe_intr_msg_data ( + .re (doe_intr_msg_data_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.doe_intr_msg_data.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (doe_intr_msg_data_qs) + ); + + + + logic [16:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [16:0] racl_addr_hit_read; + logic [16:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[ 0] = (reg_addr == MBX_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == MBX_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == MBX_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == MBX_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == MBX_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == MBX_STATUS_OFFSET); + addr_hit[ 6] = (reg_addr == MBX_ADDRESS_RANGE_REGWEN_OFFSET); + addr_hit[ 7] = (reg_addr == MBX_ADDRESS_RANGE_VALID_OFFSET); + addr_hit[ 8] = (reg_addr == MBX_INBOUND_BASE_ADDRESS_OFFSET); + addr_hit[ 9] = (reg_addr == MBX_INBOUND_LIMIT_ADDRESS_OFFSET); + addr_hit[10] = (reg_addr == MBX_INBOUND_WRITE_PTR_OFFSET); + addr_hit[11] = (reg_addr == MBX_OUTBOUND_BASE_ADDRESS_OFFSET); + addr_hit[12] = (reg_addr == MBX_OUTBOUND_LIMIT_ADDRESS_OFFSET); + addr_hit[13] = (reg_addr == MBX_OUTBOUND_READ_PTR_OFFSET); + addr_hit[14] = (reg_addr == MBX_OUTBOUND_OBJECT_SIZE_OFFSET); + addr_hit[15] = (reg_addr == MBX_DOE_INTR_MSG_ADDR_OFFSET); + addr_hit[16] = (reg_addr == MBX_DOE_INTR_MSG_DATA_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 17; slice_idx++) begin + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[ 0] & (|(MBX_CORE_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(MBX_CORE_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(MBX_CORE_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(MBX_CORE_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(MBX_CORE_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(MBX_CORE_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(MBX_CORE_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(MBX_CORE_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(MBX_CORE_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(MBX_CORE_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[10] & (|(MBX_CORE_PERMIT[10] & ~reg_be))) | + (racl_addr_hit_write[11] & (|(MBX_CORE_PERMIT[11] & ~reg_be))) | + (racl_addr_hit_write[12] & (|(MBX_CORE_PERMIT[12] & ~reg_be))) | + (racl_addr_hit_write[13] & (|(MBX_CORE_PERMIT[13] & ~reg_be))) | + (racl_addr_hit_write[14] & (|(MBX_CORE_PERMIT[14] & ~reg_be))) | + (racl_addr_hit_write[15] & (|(MBX_CORE_PERMIT[15] & ~reg_be))) | + (racl_addr_hit_write[16] & (|(MBX_CORE_PERMIT[16] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = racl_addr_hit_write[0] & reg_we & !reg_error; + + assign intr_state_mbx_ready_wd = reg_wdata[0]; + + assign intr_state_mbx_abort_wd = reg_wdata[1]; + + assign intr_state_mbx_error_wd = reg_wdata[2]; + + assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign intr_enable_mbx_ready_wd = reg_wdata[0]; + + assign intr_enable_mbx_abort_wd = reg_wdata[1]; + + assign intr_enable_mbx_error_wd = reg_wdata[2]; + + assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign intr_test_mbx_ready_wd = reg_wdata[0]; + + assign intr_test_mbx_abort_wd = reg_wdata[1]; + + assign intr_test_mbx_error_wd = reg_wdata[2]; + + assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error; + + assign alert_test_fatal_fault_wd = reg_wdata[0]; + + assign alert_test_recov_fault_wd = reg_wdata[1]; + + assign control_re = racl_addr_hit_read[4] & reg_re & !reg_error; + assign control_we = racl_addr_hit_write[4] & reg_we & !reg_error; + + assign control_abort_wd = reg_wdata[0]; + + assign control_error_wd = reg_wdata[1]; + + assign control_sys_async_msg_wd = reg_wdata[3]; + + assign status_re = racl_addr_hit_read[5] & reg_re & !reg_error; + assign address_range_regwen_we = racl_addr_hit_write[6] & reg_we & !reg_error; + + assign address_range_regwen_wd = reg_wdata[3:0]; + + assign address_range_valid_we = racl_addr_hit_write[7] & reg_we & !reg_error; + + assign address_range_valid_wd = reg_wdata[0]; + + assign inbound_base_address_we = racl_addr_hit_write[8] & reg_we & !reg_error; + + assign inbound_base_address_wd = reg_wdata[31:2]; + + assign inbound_limit_address_we = racl_addr_hit_write[9] & reg_we & !reg_error; + + assign inbound_limit_address_wd = reg_wdata[31:2]; + + assign inbound_write_ptr_re = racl_addr_hit_read[10] & reg_re & !reg_error; + assign outbound_base_address_we = racl_addr_hit_write[11] & reg_we & !reg_error; + + assign outbound_base_address_wd = reg_wdata[31:2]; + + assign outbound_limit_address_we = racl_addr_hit_write[12] & reg_we & !reg_error; + + assign outbound_limit_address_wd = reg_wdata[31:2]; + + assign outbound_read_ptr_re = racl_addr_hit_read[13] & reg_re & !reg_error; + assign outbound_object_size_we = racl_addr_hit_write[14] & reg_we & !reg_error; + + assign outbound_object_size_wd = reg_wdata[10:0]; + + assign doe_intr_msg_addr_re = racl_addr_hit_read[15] & reg_re & !reg_error; + assign doe_intr_msg_data_re = racl_addr_hit_read[16] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = control_we; + reg_we_check[5] = 1'b0; + reg_we_check[6] = address_range_regwen_we; + reg_we_check[7] = address_range_valid_we; + reg_we_check[8] = inbound_base_address_we; + reg_we_check[9] = inbound_limit_address_we; + reg_we_check[10] = 1'b0; + reg_we_check[11] = outbound_base_address_we; + reg_we_check[12] = outbound_limit_address_we; + reg_we_check[13] = 1'b0; + reg_we_check[14] = outbound_object_size_we; + reg_we_check[15] = 1'b0; + reg_we_check[16] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[0] = intr_state_mbx_ready_qs; + reg_rdata_next[1] = intr_state_mbx_abort_qs; + reg_rdata_next[2] = intr_state_mbx_error_qs; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[0] = intr_enable_mbx_ready_qs; + reg_rdata_next[1] = intr_enable_mbx_abort_qs; + reg_rdata_next[2] = intr_enable_mbx_error_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + racl_addr_hit_read[4]: begin + reg_rdata_next[0] = control_abort_qs; + reg_rdata_next[1] = control_error_qs; + reg_rdata_next[3] = '0; + end + + racl_addr_hit_read[5]: begin + reg_rdata_next[0] = status_busy_qs; + reg_rdata_next[1] = status_sys_intr_state_qs; + reg_rdata_next[2] = status_sys_intr_enable_qs; + reg_rdata_next[3] = status_sys_async_enable_qs; + end + + racl_addr_hit_read[6]: begin + reg_rdata_next[3:0] = address_range_regwen_qs; + end + + racl_addr_hit_read[7]: begin + reg_rdata_next[0] = address_range_valid_qs; + end + + racl_addr_hit_read[8]: begin + reg_rdata_next[31:2] = inbound_base_address_qs; + end + + racl_addr_hit_read[9]: begin + reg_rdata_next[31:2] = inbound_limit_address_qs; + end + + racl_addr_hit_read[10]: begin + reg_rdata_next[31:2] = inbound_write_ptr_qs; + end + + racl_addr_hit_read[11]: begin + reg_rdata_next[31:2] = outbound_base_address_qs; + end + + racl_addr_hit_read[12]: begin + reg_rdata_next[31:2] = outbound_limit_address_qs; + end + + racl_addr_hit_read[13]: begin + reg_rdata_next[31:2] = outbound_read_ptr_qs; + end + + racl_addr_hit_read[14]: begin + reg_rdata_next[10:0] = outbound_object_size_qs; + end + + racl_addr_hit_read[15]: begin + reg_rdata_next[31:0] = doe_intr_msg_addr_qs; + end + + racl_addr_hit_read[16]: begin + reg_rdata_next[31:0] = doe_intr_msg_data_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/rdl2ot/tests/snapshots/mbx_reg_pkg.sv b/rdl2ot/tests/snapshots/mbx_reg_pkg.sv new file mode 100644 index 0000000..6709c2f --- /dev/null +++ b/rdl2ot/tests/snapshots/mbx_reg_pkg.sv @@ -0,0 +1,430 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `rdl2ot` containing data structure + +package mbx_reg_pkg; + + // Param list + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int CoreAw = 7; + parameter int SocAw = 5; + + // Number of registers for every interface + parameter int NumRegsCore = 17; + parameter int NumRegsSoc = 4; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0, + AlertRecovFaultIdx = 1 + } mbx_alert_idx_t; + + /////////////////////////////////////////////// + // Typedefs for registers for core interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } mbx_error; + struct packed { + logic q; + } mbx_abort; + struct packed { + logic q; + } mbx_ready; + } mbx_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } mbx_error; + struct packed { + logic q; + } mbx_abort; + struct packed { + logic q; + } mbx_ready; + } mbx_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } mbx_error; + struct packed { + logic q; + logic qe; + } mbx_abort; + struct packed { + logic q; + logic qe; + } mbx_ready; + } mbx_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov_fault; + struct packed { + logic q; + logic qe; + } fatal_fault; + } mbx_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } sys_async_msg; + struct packed { + logic q; + logic qe; + } error; + struct packed { + logic q; + logic qe; + } abort; + } mbx_reg2hw_control_reg_t; + + typedef struct packed { + logic q; + logic qe; + } mbx_reg2hw_address_range_valid_reg_t; + + typedef struct packed { + logic [29:0] q; + } mbx_reg2hw_inbound_base_address_reg_t; + + typedef struct packed { + logic [29:0] q; + } mbx_reg2hw_inbound_limit_address_reg_t; + + typedef struct packed { + logic [29:0] q; + } mbx_reg2hw_outbound_base_address_reg_t; + + typedef struct packed { + logic [29:0] q; + } mbx_reg2hw_outbound_limit_address_reg_t; + + typedef struct packed { + logic [10:0] q; + logic qe; + } mbx_reg2hw_outbound_object_size_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } mbx_error; + struct packed { + logic d; + logic de; + } mbx_abort; + struct packed { + logic d; + logic de; + } mbx_ready; + } mbx_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic d; + } error; + struct packed { + logic d; + } abort; + } mbx_hw2reg_control_reg_t; + + typedef struct packed { + struct packed { + logic d; + } sys_async_enable; + struct packed { + logic d; + } sys_intr_enable; + struct packed { + logic d; + } sys_intr_state; + struct packed { + logic d; + } busy; + } mbx_hw2reg_status_reg_t; + + typedef struct packed { + logic [29:0] d; + } mbx_hw2reg_inbound_write_ptr_reg_t; + + typedef struct packed { + logic [29:0] d; + } mbx_hw2reg_outbound_read_ptr_reg_t; + + typedef struct packed { + logic [10:0] d; + logic de; + } mbx_hw2reg_outbound_object_size_reg_t; + + typedef struct packed { + logic [31:0] d; + } mbx_hw2reg_doe_intr_msg_addr_reg_t; + + typedef struct packed { + logic [31:0] d; + } mbx_hw2reg_doe_intr_msg_data_reg_t; + + // Register -> HW type for core interface + typedef struct packed { + mbx_reg2hw_intr_state_reg_t intr_state; + mbx_reg2hw_intr_enable_reg_t intr_enable; + mbx_reg2hw_intr_test_reg_t intr_test; + mbx_reg2hw_alert_test_reg_t alert_test; + mbx_reg2hw_control_reg_t control; + mbx_reg2hw_address_range_valid_reg_t address_range_valid; + mbx_reg2hw_inbound_base_address_reg_t inbound_base_address; + mbx_reg2hw_inbound_limit_address_reg_t inbound_limit_address; + mbx_reg2hw_outbound_base_address_reg_t outbound_base_address; + mbx_reg2hw_outbound_limit_address_reg_t outbound_limit_address; + mbx_reg2hw_outbound_object_size_reg_t outbound_object_size; + } mbx_core_reg2hw_t; + + // HW -> register type for core interface + typedef struct packed { + mbx_hw2reg_intr_state_reg_t intr_state; + mbx_hw2reg_control_reg_t control; + mbx_hw2reg_status_reg_t status; + mbx_hw2reg_inbound_write_ptr_reg_t inbound_write_ptr; + mbx_hw2reg_outbound_read_ptr_reg_t outbound_read_ptr; + mbx_hw2reg_outbound_object_size_reg_t outbound_object_size; + mbx_hw2reg_doe_intr_msg_addr_reg_t doe_intr_msg_addr; + mbx_hw2reg_doe_intr_msg_data_reg_t doe_intr_msg_data; + } mbx_core_hw2reg_t; + + // Register offsets for core interface + parameter logic [CoreAw-1:0] MBX_INTR_STATE_OFFSET = 7'h 0; + parameter logic [CoreAw-1:0] MBX_INTR_ENABLE_OFFSET = 7'h 4; + parameter logic [CoreAw-1:0] MBX_INTR_TEST_OFFSET = 7'h 8; + parameter logic [CoreAw-1:0] MBX_ALERT_TEST_OFFSET = 7'h c; + parameter logic [CoreAw-1:0] MBX_CONTROL_OFFSET = 7'h 10; + parameter logic [CoreAw-1:0] MBX_STATUS_OFFSET = 7'h 14; + parameter logic [CoreAw-1:0] MBX_ADDRESS_RANGE_REGWEN_OFFSET = 7'h 18; + parameter logic [CoreAw-1:0] MBX_ADDRESS_RANGE_VALID_OFFSET = 7'h 1c; + parameter logic [CoreAw-1:0] MBX_INBOUND_BASE_ADDRESS_OFFSET = 7'h 20; + parameter logic [CoreAw-1:0] MBX_INBOUND_LIMIT_ADDRESS_OFFSET = 7'h 24; + parameter logic [CoreAw-1:0] MBX_INBOUND_WRITE_PTR_OFFSET = 7'h 28; + parameter logic [CoreAw-1:0] MBX_OUTBOUND_BASE_ADDRESS_OFFSET = 7'h 2c; + parameter logic [CoreAw-1:0] MBX_OUTBOUND_LIMIT_ADDRESS_OFFSET = 7'h 30; + parameter logic [CoreAw-1:0] MBX_OUTBOUND_READ_PTR_OFFSET = 7'h 34; + parameter logic [CoreAw-1:0] MBX_OUTBOUND_OBJECT_SIZE_OFFSET = 7'h 38; + parameter logic [CoreAw-1:0] MBX_DOE_INTR_MSG_ADDR_OFFSET = 7'h 3c; + parameter logic [CoreAw-1:0] MBX_DOE_INTR_MSG_DATA_OFFSET = 7'h 40; + + // Reset values for hwext registers and their fields for core interface + parameter logic [2:0] MBX_INTR_TEST_RESVAL = 3'h 0; + parameter logic [0:0] MBX_INTR_TEST_MBX_READY_RESVAL = 1'h 0; + parameter logic [0:0] MBX_INTR_TEST_MBX_ABORT_RESVAL = 1'h 0; + parameter logic [0:0] MBX_INTR_TEST_MBX_ERROR_RESVAL = 1'h 0; + parameter logic [1:0] MBX_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] MBX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] MBX_ALERT_TEST_RECOV_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] MBX_CONTROL_RESVAL = 4'h 0; + parameter logic [0:0] MBX_CONTROL_ABORT_RESVAL = 1'h 0; + parameter logic [0:0] MBX_CONTROL_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] MBX_CONTROL_SYS_ASYNC_MSG_RESVAL = 1'h 0; + parameter logic [3:0] MBX_STATUS_RESVAL = 4'h 1; + parameter logic [0:0] MBX_STATUS_BUSY_RESVAL = 1'h 1; + parameter logic [0:0] MBX_STATUS_SYS_INTR_STATE_RESVAL = 1'h 0; + parameter logic [0:0] MBX_STATUS_SYS_INTR_ENABLE_RESVAL = 1'h 0; + parameter logic [0:0] MBX_STATUS_SYS_ASYNC_ENABLE_RESVAL = 1'h 0; + parameter logic [31:0] MBX_INBOUND_WRITE_PTR_RESVAL = 32'h 0; + parameter logic [29:0] MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_RESVAL = 30'h 0; + parameter logic [31:0] MBX_OUTBOUND_READ_PTR_RESVAL = 32'h 0; + parameter logic [29:0] MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_RESVAL = 30'h 0; + parameter logic [31:0] MBX_DOE_INTR_MSG_ADDR_RESVAL = 32'h 0; + parameter logic [31:0] MBX_DOE_INTR_MSG_ADDR_DOE_INTR_MSG_ADDR_RESVAL = 32'h 0; + parameter logic [31:0] MBX_DOE_INTR_MSG_DATA_RESVAL = 32'h 0; + parameter logic [31:0] MBX_DOE_INTR_MSG_DATA_DOE_INTR_MSG_DATA_RESVAL = 32'h 0; + + // Register index for core interface + typedef enum int { + MBX_INTR_STATE, + MBX_INTR_ENABLE, + MBX_INTR_TEST, + MBX_ALERT_TEST, + MBX_CONTROL, + MBX_STATUS, + MBX_ADDRESS_RANGE_REGWEN, + MBX_ADDRESS_RANGE_VALID, + MBX_INBOUND_BASE_ADDRESS, + MBX_INBOUND_LIMIT_ADDRESS, + MBX_INBOUND_WRITE_PTR, + MBX_OUTBOUND_BASE_ADDRESS, + MBX_OUTBOUND_LIMIT_ADDRESS, + MBX_OUTBOUND_READ_PTR, + MBX_OUTBOUND_OBJECT_SIZE, + MBX_DOE_INTR_MSG_ADDR, + MBX_DOE_INTR_MSG_DATA + } mbx_core_id_e; + + // Register width information to check illegal writes for core interface + parameter logic [3:0] MBX_CORE_PERMIT [17] = '{ + 4'b 0001, // index[ 0] MBX_INTR_STATE + 4'b 0001, // index[ 1] MBX_INTR_ENABLE + 4'b 0001, // index[ 2] MBX_INTR_TEST + 4'b 0001, // index[ 3] MBX_ALERT_TEST + 4'b 0001, // index[ 4] MBX_CONTROL + 4'b 0001, // index[ 5] MBX_STATUS + 4'b 0001, // index[ 6] MBX_ADDRESS_RANGE_REGWEN + 4'b 0001, // index[ 7] MBX_ADDRESS_RANGE_VALID + 4'b 1111, // index[ 8] MBX_INBOUND_BASE_ADDRESS + 4'b 1111, // index[ 9] MBX_INBOUND_LIMIT_ADDRESS + 4'b 1111, // index[10] MBX_INBOUND_WRITE_PTR + 4'b 1111, // index[11] MBX_OUTBOUND_BASE_ADDRESS + 4'b 1111, // index[12] MBX_OUTBOUND_LIMIT_ADDRESS + 4'b 1111, // index[13] MBX_OUTBOUND_READ_PTR + 4'b 0011, // index[14] MBX_OUTBOUND_OBJECT_SIZE + 4'b 1111, // index[15] MBX_DOE_INTR_MSG_ADDR + 4'b 1111 // index[16] MBX_DOE_INTR_MSG_DATA + }; + + /////////////////////////////////////////////// + // Typedefs for registers for soc interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } go; + struct packed { + logic q; + logic qe; + } doe_async_msg_en; + struct packed { + logic q; + logic qe; + } doe_intr_en; + struct packed { + logic q; + logic qe; + } abort; + } mbx_reg2hw_soc_control_reg_t; + + typedef struct packed { + struct packed { + logic q; + } ready; + struct packed { + logic q; + } error; + struct packed { + logic q; + } doe_intr_status; + struct packed { + logic q; + } busy; + } mbx_reg2hw_soc_status_reg_t; + + typedef struct packed { + logic [31:0] q; + } mbx_reg2hw_soc_doe_intr_msg_addr_reg_t; + + typedef struct packed { + logic [31:0] q; + } mbx_reg2hw_soc_doe_intr_msg_data_reg_t; + + typedef struct packed { + struct packed { + logic d; + } go; + struct packed { + logic d; + } doe_async_msg_en; + struct packed { + logic d; + } doe_intr_en; + struct packed { + logic d; + } abort; + } mbx_hw2reg_soc_control_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } ready; + struct packed { + logic d; + logic de; + } doe_async_msg_status; + struct packed { + logic d; + logic de; + } error; + struct packed { + logic d; + logic de; + } doe_intr_status; + struct packed { + logic d; + logic de; + } busy; + } mbx_hw2reg_soc_status_reg_t; + + // Register -> HW type for soc interface + typedef struct packed { + mbx_reg2hw_soc_control_reg_t soc_control; + mbx_reg2hw_soc_status_reg_t soc_status; + mbx_reg2hw_soc_doe_intr_msg_addr_reg_t soc_doe_intr_msg_addr; + mbx_reg2hw_soc_doe_intr_msg_data_reg_t soc_doe_intr_msg_data; + } mbx_soc_reg2hw_t; + + // HW -> register type for soc interface + typedef struct packed { + mbx_hw2reg_soc_control_reg_t soc_control; + mbx_hw2reg_soc_status_reg_t soc_status; + } mbx_soc_hw2reg_t; + + // Register offsets for soc interface + parameter logic [SocAw-1:0] MBX_SOC_CONTROL_OFFSET = 5'h 8; + parameter logic [SocAw-1:0] MBX_SOC_STATUS_OFFSET = 5'h c; + parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_ADDR_OFFSET = 5'h 18; + parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_DATA_OFFSET = 5'h 1c; + + // Reset values for hwext registers and their fields for soc interface + parameter logic [31:0] MBX_SOC_CONTROL_RESVAL = 32'h 0; + parameter logic [0:0] MBX_SOC_CONTROL_ABORT_RESVAL = 1'h 0; + parameter logic [0:0] MBX_SOC_CONTROL_DOE_INTR_EN_RESVAL = 1'h 0; + parameter logic [0:0] MBX_SOC_CONTROL_DOE_ASYNC_MSG_EN_RESVAL = 1'h 0; + parameter logic [0:0] MBX_SOC_CONTROL_GO_RESVAL = 1'h 0; + + // Window parameters for soc interface + parameter logic [SocAw-1:0] MBX_WDATA_OFFSET = 5'h 10; + parameter int unsigned MBX_WDATA_SIZE = 'h 4; + parameter int unsigned MBX_WDATA_IDX = 0; + parameter logic [SocAw-1:0] MBX_RDATA_OFFSET = 5'h 14; + parameter int unsigned MBX_RDATA_SIZE = 'h 4; + parameter int unsigned MBX_RDATA_IDX = 1; + + // Register index for soc interface + typedef enum int { + MBX_SOC_CONTROL, + MBX_SOC_STATUS, + MBX_SOC_DOE_INTR_MSG_ADDR, + MBX_SOC_DOE_INTR_MSG_DATA + } mbx_soc_id_e; + + // Register width information to check illegal writes for soc interface + parameter logic [3:0] MBX_SOC_PERMIT [4] = '{ + 4'b 1111, // index[0] MBX_SOC_CONTROL + 4'b 1111, // index[1] MBX_SOC_STATUS + 4'b 1111, // index[2] MBX_SOC_DOE_INTR_MSG_ADDR + 4'b 1111 // index[3] MBX_SOC_DOE_INTR_MSG_DATA + }; + +endpackage \ No newline at end of file diff --git a/rdl2ot/tests/snapshots/mbx_soc_reg_top.sv b/rdl2ot/tests/snapshots/mbx_soc_reg_top.sv new file mode 100644 index 0000000..2444311 --- /dev/null +++ b/rdl2ot/tests/snapshots/mbx_soc_reg_top.sv @@ -0,0 +1,637 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `rdl2ot` + +`include "prim_assert.sv" + +module mbx_soc_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[mbx_reg_pkg::NumRegsSoc] = + '{mbx_reg_pkg::NumRegsSoc{0}} + ) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o [2], + input tlul_pkg::tl_d2h_t tl_win_i [2], + // To HW + output mbx_reg_pkg::mbx_soc_reg2hw_t reg2hw, // Write + input mbx_reg_pkg::mbx_soc_hw2reg_t hw2reg, // Read + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import mbx_reg_pkg::* ; + + localparam int AW = 5; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [3:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(4) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + tlul_pkg::tl_h2d_t tl_socket_h2d [3]; + tlul_pkg::tl_d2h_t tl_socket_d2h [3]; + + logic [1:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[2]; + assign tl_socket_d2h[2] = tl_reg_d2h; + + assign tl_win_o[0] = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i[0]; + assign tl_win_o[1] = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_win_i[1]; + + // Create Socket_1n + tlul_socket_1n #( + .N (3), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({3{1'b1}}), + .DRspPass ({3{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({3{4'h0}}), + .DRspDepth ({3{4'h0}}), + .ExplicitErrs (1'b0) + ) u_socket ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = + tl_i.a_address[AW-1:0] inside {[16:19]} ? 2'd0 : + tl_i.a_address[AW-1:0] inside {[20:23]} ? 2'd1 : + // Default set to register + 2'd2; + + // Override this in case of an integrity error + if (intg_err) begin + reg_steer = 2'd2; + end + end + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic soc_control_re; + logic soc_control_we; + logic soc_control_abort_wd; + logic soc_control_doe_intr_en_qs; + logic soc_control_doe_intr_en_wd; + logic soc_control_doe_async_msg_en_qs; + logic soc_control_doe_async_msg_en_wd; + logic soc_control_go_wd; + logic soc_status_we; + logic soc_status_busy_qs; + logic soc_status_doe_intr_status_qs; + logic soc_status_doe_intr_status_wd; + logic soc_status_error_qs; + logic soc_status_doe_async_msg_status_qs; + logic soc_status_ready_qs; + logic soc_doe_intr_msg_addr_we; + logic [31:0] soc_doe_intr_msg_addr_qs; + logic [31:0] soc_doe_intr_msg_addr_wd; + logic soc_doe_intr_msg_data_we; + logic [31:0] soc_doe_intr_msg_data_qs; + logic [31:0] soc_doe_intr_msg_data_wd; + // Register instances + // R[soc_control]: V(True) + logic soc_control_qe; + logic [3:0] soc_control_flds_we; + assign soc_control_qe = &soc_control_flds_we; + // F[abort]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_soc_control_abort ( + .re (1'b0), + .we (soc_control_we), + .wd (soc_control_abort_wd), + .d (hw2reg.soc_control.abort.d), + .qre (), + .qe (soc_control_flds_we[0]), + .q (reg2hw.soc_control.abort.q), + .ds (), + .qs () + ); + assign reg2hw.soc_control.abort.qe = soc_control_qe; + + // F[doe_intr_en]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_soc_control_doe_intr_en ( + .re (soc_control_re), + .we (soc_control_we), + .wd (soc_control_doe_intr_en_wd), + .d (hw2reg.soc_control.doe_intr_en.d), + .qre (), + .qe (soc_control_flds_we[1]), + .q (reg2hw.soc_control.doe_intr_en.q), + .ds (), + .qs (soc_control_doe_intr_en_qs) + ); + assign reg2hw.soc_control.doe_intr_en.qe = soc_control_qe; + + // F[doe_async_msg_en]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_soc_control_doe_async_msg_en ( + .re (soc_control_re), + .we (soc_control_we), + .wd (soc_control_doe_async_msg_en_wd), + .d (hw2reg.soc_control.doe_async_msg_en.d), + .qre (), + .qe (soc_control_flds_we[2]), + .q (reg2hw.soc_control.doe_async_msg_en.q), + .ds (), + .qs (soc_control_doe_async_msg_en_qs) + ); + assign reg2hw.soc_control.doe_async_msg_en.qe = soc_control_qe; + + // F[go]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_soc_control_go ( + .re (1'b0), + .we (soc_control_we), + .wd (soc_control_go_wd), + .d (hw2reg.soc_control.go.d), + .qre (), + .qe (soc_control_flds_we[3]), + .q (reg2hw.soc_control.go.q), + .ds (), + .qs () + ); + assign reg2hw.soc_control.go.qe = soc_control_qe; + + + // R[soc_status]: V(False) + // F[busy]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_soc_status_busy ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.soc_status.busy.de), + .d (hw2reg.soc_status.busy.d), + + // to internal hardware + .qe (), + .q (reg2hw.soc_status.busy.q), + .ds (), + + // to register interface (read) + .qs (soc_status_busy_qs) + ); + + // F[doe_intr_status]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_soc_status_doe_intr_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (soc_status_we), + .wd (soc_status_doe_intr_status_wd), + + // from internal hardware + .de (hw2reg.soc_status.doe_intr_status.de), + .d (hw2reg.soc_status.doe_intr_status.d), + + // to internal hardware + .qe (), + .q (reg2hw.soc_status.doe_intr_status.q), + .ds (), + + // to register interface (read) + .qs (soc_status_doe_intr_status_qs) + ); + + // F[error]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_soc_status_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.soc_status.error.de), + .d (hw2reg.soc_status.error.d), + + // to internal hardware + .qe (), + .q (reg2hw.soc_status.error.q), + .ds (), + + // to register interface (read) + .qs (soc_status_error_qs) + ); + + // F[doe_async_msg_status]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_soc_status_doe_async_msg_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.soc_status.doe_async_msg_status.de), + .d (hw2reg.soc_status.doe_async_msg_status.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (soc_status_doe_async_msg_status_qs) + ); + + // F[ready]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_soc_status_ready ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.soc_status.ready.de), + .d (hw2reg.soc_status.ready.d), + + // to internal hardware + .qe (), + .q (reg2hw.soc_status.ready.q), + .ds (), + + // to register interface (read) + .qs (soc_status_ready_qs) + ); + + + // R[soc_doe_intr_msg_addr]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_soc_doe_intr_msg_addr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (soc_doe_intr_msg_addr_we), + .wd (soc_doe_intr_msg_addr_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.soc_doe_intr_msg_addr.q), + .ds (), + + // to register interface (read) + .qs (soc_doe_intr_msg_addr_qs) + ); + + + // R[soc_doe_intr_msg_data]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_soc_doe_intr_msg_data ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (soc_doe_intr_msg_data_we), + .wd (soc_doe_intr_msg_data_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.soc_doe_intr_msg_data.q), + .ds (), + + // to register interface (read) + .qs (soc_doe_intr_msg_data_qs) + ); + + + + logic [3:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [3:0] racl_addr_hit_read; + logic [3:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[0] = (reg_addr == MBX_SOC_CONTROL_OFFSET); + addr_hit[1] = (reg_addr == MBX_SOC_STATUS_OFFSET); + addr_hit[2] = (reg_addr == MBX_SOC_DOE_INTR_MSG_ADDR_OFFSET); + addr_hit[3] = (reg_addr == MBX_SOC_DOE_INTR_MSG_DATA_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 4; slice_idx++) begin + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[0] & (|(MBX_SOC_PERMIT[0] & ~reg_be))) | + (racl_addr_hit_write[1] & (|(MBX_SOC_PERMIT[1] & ~reg_be))) | + (racl_addr_hit_write[2] & (|(MBX_SOC_PERMIT[2] & ~reg_be))) | + (racl_addr_hit_write[3] & (|(MBX_SOC_PERMIT[3] & ~reg_be))))); + end + + // Generate write-enables + assign soc_control_re = racl_addr_hit_read[0] & reg_re & !reg_error; + assign soc_control_we = racl_addr_hit_write[0] & reg_we & !reg_error; + + assign soc_control_abort_wd = reg_wdata[0]; + + assign soc_control_doe_intr_en_wd = reg_wdata[1]; + + assign soc_control_doe_async_msg_en_wd = reg_wdata[3]; + + assign soc_control_go_wd = reg_wdata[31]; + + assign soc_status_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign soc_status_doe_intr_status_wd = reg_wdata[1]; + + assign soc_doe_intr_msg_addr_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign soc_doe_intr_msg_addr_wd = reg_wdata[31:0]; + + assign soc_doe_intr_msg_data_we = racl_addr_hit_write[3] & reg_we & !reg_error; + + assign soc_doe_intr_msg_data_wd = reg_wdata[31:0]; + + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = soc_control_we; + reg_we_check[1] = soc_status_we; + reg_we_check[2] = soc_doe_intr_msg_addr_we; + reg_we_check[3] = soc_doe_intr_msg_data_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = soc_control_doe_intr_en_qs; + reg_rdata_next[3] = soc_control_doe_async_msg_en_qs; + reg_rdata_next[31] = '0; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[0] = soc_status_busy_qs; + reg_rdata_next[1] = soc_status_doe_intr_status_qs; + reg_rdata_next[2] = soc_status_error_qs; + reg_rdata_next[3] = soc_status_doe_async_msg_status_qs; + reg_rdata_next[31] = soc_status_ready_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[31:0] = soc_doe_intr_msg_addr_qs; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[31:0] = soc_doe_intr_msg_data_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/rdl2ot/tests/snapshots/spi_device.rdl b/rdl2ot/tests/snapshots/spi_device.rdl new file mode 100644 index 0000000..91a16f7 --- /dev/null +++ b/rdl2ot/tests/snapshots/spi_device.rdl @@ -0,0 +1,1270 @@ +`include "udp.rdl" + +addrmap spi_device #( + longint SramDepth = 1024, + longint SramEgressDepth = 848, + longint SramIngressDepth = 112, + longint SramReadBufferOffset = 0, + longint SramReadBufferDepth = 512, + longint SramMailboxOffset = 512, + longint SramMailboxDepth = 256, + longint SramSfdpOffset = 768, + longint SramSfdpDepth = 64, + longint SramTpmRdFifoOffset = 832, + longint SramTpmRdFifoDepth = 16, + longint SramPayloadOffset = 0, + longint SramPayloadDepth = 64, + longint SramCmdFifoOffset = 64, + longint SramCmdFifoDepth = 16, + longint SramAddrFifoOffset = 80, + longint SramAddrFifoDepth = 16, + longint SramTpmWrFifoOffset = 96, + longint SramTpmWrFifoDepth = 16, + longint NumCmdInfo = 24, + longint NumLocality = 5, + longint TpmRdFifoPtrW = 5, + longint TpmRdFifoWidth = 32, + longint NumAlerts = 1 +){ + bus_interface_cfg = BusInterfaceCfg'{ + racl_support : true, + direction : BusDirection::Device, + protocol : BusProtocol::TlUl, + hier_path : "u_reg" + }; + signal { + signalwidth = 0x1; + sigtype = SigType::InterModRecv; + inter_mod_struct = "ram_2p_cfg"; + inter_mod_package = "prim_ram_2p_pkg"; + } RAM_CFG_SYS2SPI; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "ram_2p_cfg_rsp"; + inter_mod_package = "prim_ram_2p_pkg"; + } RAM_CFG_RSP_SYS2SPI; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModRecv; + inter_mod_struct = "ram_2p_cfg"; + inter_mod_package = "prim_ram_2p_pkg"; + } RAM_CFG_SPI2SYS; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "ram_2p_cfg_rsp"; + inter_mod_package = "prim_ram_2p_pkg"; + } RAM_CFG_RSP_SPI2SYS; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReqRsp; + inter_mod_struct = "passthrough"; + inter_mod_package = "spi_device_pkg"; + } PASSTHROUGH; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModRecv; + inter_mod_struct = "logic"; + } MBIST_EN; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "logic"; + } SCK_MONITOR; + + signal { + desc = "Incoming RACL policy vector from a racl_ctrl instance.The policy selection vector (parameter) selects the policy for each register."; + signalwidth = 0x1; + sigtype = SigType::InterModRecv; + inter_mod_struct = "racl_policy_vec"; + inter_mod_package = "top_racl_pkg"; + } RACL_POLICIES; + + signal { + desc = "RACL error log information of this module."; + signalwidth = 0x1; + sigtype = SigType::InterModReq; + inter_mod_struct = "racl_error_log"; + inter_mod_package = "top_racl_pkg"; + } RACL_ERROR; + + signal { + signalwidth = 0x1; + sigtype = SigType::InterModReqRsp; + inter_mod_struct = "tl"; + inter_mod_package = "tlul_pkg"; + } TL; + + signal { + desc = "Upload Command FIFO is not empty"; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } UPLOAD_CMDFIFO_NOT_EMPTY; + + signal { + desc = "Upload payload is not empty.The event occurs after SPI transaction completed"; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } UPLOAD_PAYLOAD_NOT_EMPTY; + + signal { + desc = "Upload payload overflow event.When a SPI Host system issues a command with payload more than 256B,this event is reported. When it happens, SW should read the lastwritten payload index CSR to figure out the starting address of thelast 256B."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } UPLOAD_PAYLOAD_OVERFLOW; + + signal { + desc = "Read Buffer Threshold event.The host system accesses greater than or equal to the threshold of abuffer."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } READBUF_WATERMARK; + + signal { + desc = "Read buffer flipped event.The host system accesses other side of buffer."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } READBUF_FLIP; + + signal { + desc = "TPM Header(Command/Address) buffer available"; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } TPM_HEADER_NOT_EMPTY; + + signal { + desc = "TPM RdFIFO command ended.The TPM Read command targeting the RdFIFO ended.Check TPM_STATUS.rdfifo_aborted to see if the transaction completed."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } TPM_RDFIFO_CMD_END; + + signal { + desc = "TPM RdFIFO data dropped.Data was dropped from the RdFIFO.Data was written while a read command was not active, and it was not accepted.This can occur when the host aborts a read command."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } TPM_RDFIFO_DROP; + + signal { + desc = "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected."; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_FAULT; + + signal { + signalwidth = 0x1; + sigtype = SigType::Sync; + } CLK_I; + + signal { + signalwidth = 0x1; + sigtype = SigType::Sync; + } RST_NI; + + signal { + signalwidth = 0x1; + sigtype = SigType::Sync; + } SCAN_CLK_I; + + signal { + desc = "SPI IO, IO2/IO3 has multi-purpose (/WP, /HOLD)"; + signalwidth = 0x4; + sigtype = SigType::InOut; + } SD; + + signal { + desc = "SPI Clock"; + signalwidth = 0x1; + sigtype = SigType::Input; + } SCK; + + signal { + desc = "Chip Select#"; + signalwidth = 0x1; + sigtype = SigType::Input; + } CSB; + + signal { + desc = "TPM Chip Select#"; + signalwidth = 0x1; + sigtype = SigType::Input; + } TPM_CSB; + + reg { + desc = "Interrupt State Register"; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "Upload Command FIFO is not empty"; + } UPLOAD_CMDFIFO_NOT_EMPTY[0:0]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "Upload payload is not empty.The event occurs after SPI transaction completed"; + } UPLOAD_PAYLOAD_NOT_EMPTY[1:1]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "Upload payload overflow event.When a SPI Host system issues a command with payload more than 256B,this event is reported. When it happens, SW should read the lastwritten payload index CSR to figure out the starting address of thelast 256B."; + } UPLOAD_PAYLOAD_OVERFLOW[2:2]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "Read Buffer Threshold event.The host system accesses greater than or equal to the threshold of abuffer."; + } READBUF_WATERMARK[3:3]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "Read buffer flipped event.The host system accesses other side of buffer."; + } READBUF_FLIP[4:4]; + field { + sw = r; + hw = rw; + reset = false; + desc = "TPM Header(Command/Address) buffer available"; + } TPM_HEADER_NOT_EMPTY[5:5]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "TPM RdFIFO command ended.The TPM Read command targeting the RdFIFO ended.Check TPM_STATUS.rdfifo_aborted to see if the transaction completed."; + } TPM_RDFIFO_CMD_END[6:6]; + field { + sw = rw; + onwrite = woclr; + hw = rw; + reset = false; + desc = "TPM RdFIFO data dropped.Data was dropped from the RdFIFO.Data was written while a read command was not active, and it was not accepted.This can occur when the host aborts a read command."; + } TPM_RDFIFO_DROP[7:7]; + } INTR_STATE @ 0x0; + + reg { + desc = "Interrupt Enable Register"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.upload_cmdfifo_not_empty is set."; + } UPLOAD_CMDFIFO_NOT_EMPTY[0:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.upload_payload_not_empty is set."; + } UPLOAD_PAYLOAD_NOT_EMPTY[1:1]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.upload_payload_overflow is set."; + } UPLOAD_PAYLOAD_OVERFLOW[2:2]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.readbuf_watermark is set."; + } READBUF_WATERMARK[3:3]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.readbuf_flip is set."; + } READBUF_FLIP[4:4]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.tpm_header_not_empty is set."; + } TPM_HEADER_NOT_EMPTY[5:5]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.tpm_rdfifo_cmd_end is set."; + } TPM_RDFIFO_CMD_END[6:6]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Enable interrupt when !!INTR_STATE.tpm_rdfifo_drop is set."; + } TPM_RDFIFO_DROP[7:7]; + } INTR_ENABLE @ 0x4; + + external reg { + desc = "Interrupt Test Register"; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.upload_cmdfifo_not_empty to 1."; + } UPLOAD_CMDFIFO_NOT_EMPTY[0:0]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.upload_payload_not_empty to 1."; + } UPLOAD_PAYLOAD_NOT_EMPTY[1:1]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.upload_payload_overflow to 1."; + } UPLOAD_PAYLOAD_OVERFLOW[2:2]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.readbuf_watermark to 1."; + } READBUF_WATERMARK[3:3]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.readbuf_flip to 1."; + } READBUF_FLIP[4:4]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.tpm_header_not_empty to 1."; + } TPM_HEADER_NOT_EMPTY[5:5]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.tpm_rdfifo_cmd_end to 1."; + } TPM_RDFIFO_CMD_END[6:6]; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to force !!INTR_STATE.tpm_rdfifo_drop to 1."; + } TPM_RDFIFO_DROP[7:7]; + } INTR_TEST @ 0x8; + + external reg { + desc = "Alert Test Register"; + field { + sw = w; + hw = r; + reset = 0x0; + swmod = true; + desc = "Write 1 to trigger one alert event of this kind."; + } FATAL_FAULT[0:0]; + } ALERT_TEST @ 0xC; + + reg { + desc = "Control register"; + field { + sw = rw; + onwrite = woset; + hw = rw; + reset = false; + desc = "Set to clear the flash status FIFO.When set to 1, resets the flash status FIFO used for synchronizing changes from firmware.The reset should only be used when the upstream SPI host is known to be inactive.This function is intended to allow restoring initial values when the upstream SPI host is reset.This CSR automatically resets to 0."; + } FLASH_STATUS_FIFO_CLR[0:0]; + field { + sw = rw; + onwrite = woset; + hw = rw; + reset = false; + desc = "Set to clear the read buffer state.When set to 1, resets the flash read buffer state that tracks the host read address.The reset should only be used when the upstream SPI host is known to be inactive.This function is intended to allow restoring initial values when the upstream SPI host is reset.This CSR automatically resets to 0."; + } FLASH_READ_BUFFER_CLR[1:1]; + field { + sw = rw; + hw = r; + reset = true; + desc = "SPI Device flash operation mode."; + } MODE[5:4]; + } CONTROL @ 0x10; + + reg { + desc = "Configuration Register"; + field { + sw = rw; + hw = r; + reset = false; + desc = "TX bit order on SDO. 0 for MSB to LSB, 1 for LSB to MSB"; + } TX_ORDER[2:2]; + field { + sw = rw; + hw = r; + reset = false; + desc = "RX bit order on SDI. Module stores bitstream from MSB to LSB if value is 0."; + } RX_ORDER[3:3]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Mailbox enable.If 1, in the flash and passthrough mode, the IP checks the incomingaddress and return from the internal Mailbox buffer if the addressfalls into the MAILBOX range(MAILBOX_ADDR:MAILBOX_ADDR+MAILBOX_SIZE)}."; + } MAILBOX_EN[24:24]; + } CFG @ 0x14; + + external reg { + desc = "SPI Device status register"; + field { + sw = r; + hw = w; + reset = true; + desc = "Direct input of CSb signal"; + } CSB[5:5]; + field { + sw = r; + hw = w; + reset = true; + desc = "Direct input of TPM CSb"; + } TPM_CSB[6:6]; + } STATUS @ 0x18; + + reg { + desc = "Intercept Passthrough datapath."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If set, Read Status is processed internally."; + } STATUS[0:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If set, Read JEDEC ID is processed internally."; + } JEDEC[1:1]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If set, Read SFDP is processed internally."; + } SFDP[2:2]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If set, Read Command to Mailbox region is processed internally."; + } MBX[3:3]; + } INTERCEPT_EN @ 0x1C; + + external reg { + desc = "Flash address mode configurationThis register shows the current address mode and pending changes.It is updated by the HW when the command phase completes."; + field { + sw = rw; + hw = rw; + swmod = true; + desc = "4B Address Mode enable.This field configures the internal module to receive 32 bits of the SPI commands.The affected commands are the SPI read commands except QPI, and program commands.It is expected for SW to configure this field at the configuration stage and release control to HW until the next reset.Even though Read SFDP command has address fields, the SFDP command is not affected by this field.The command always parse 24 bits on the SPI line 0 following the SPI command as the address field.This field has noteworthy read behavior.If a software-initiated change is still pending the sync to the SPI domain, this bit will reflect the value to be sent.Otherwise, this field will reflect the current value observed in the SPI domain."; + } ADDR_4B_EN[0:0]; + field { + sw = r; + hw = w; + desc = "SW-originated change is pending.This bit is 1 whenever the current value of addr_4b_en has yet to sync with the SPI domain.If an EN4B or EX4B command arrives next, the current value in addr_4b_en will be ignored,and the SPI flash command will take priority, with an update to addr_4b_en to match the command's result."; + } PENDING[31:31]; + } ADDR_MODE @ 0x20; + + external reg { + desc = "Last Read AddressThis register shows the last address accessed by the host system.It is updated by the HW when CSb is de-asserted."; + field { + sw = r; + hw = w; + desc = "Last address"; + } ADDR[31:0]; + } LAST_READ_ADDR @ 0x24; + + external reg { + desc = "SPI Flash Status register.This register emulates the SPI Flash Status 3, 2, 1 registers.bit [7:0] is for Status register, bit [15:8] is for Status-2 register,and bit [23:16] is for Status-3 register. It is SW responsibility tomaintain this register value up to date.When software writes a value here, it is delivered to a staging async FIFO, where it waits for the SPI side to commit it.Any updates require at least 8 SPI clocks before they commit on the SPI side, which is the source-of-truth.After committing on the SPI side, the CSRs will eventually update with the latest value."; + field { + sw = rw; + onwrite = wzc; + hw = rw; + swmod = true; + desc = "The BUSY signal. SW should read back the register to confirm the value is cleared.Bit 0 (BUSY) is a SW modifiable and HW modifiable field.HW updates the BUSY field for matching uploaded commands in the CMD_INFO table, when the upload and busy bits are set in the table entry.Note that the observable state of the BUSY bit updates every 8 SPI clocks.This enables continuous polling of the BUSY bit.However, the passthrough gate (for passthrough mode) only updates when CSB is de-asserted, not on SPI clocks."; + } BUSY[0:0]; + field { + sw = rw; + onwrite = wzc; + hw = rw; + swmod = true; + desc = "The Write Enable Latch signal.SW should read back the register to confirm the value is cleared.Bit 1 (WEL) is a SW modifiable and HW modifiable field.HW updates the WEL field when WRDI or WREN command is received."; + } WEL[1:1]; + field { + sw = rw; + hw = rw; + swmod = true; + desc = "Rest of the status register.Fields other than the bit 0 (BUSY) and bit 1 (WEL) fields areSW-maintained fields. HW just reads and returns to the host system.- [ 2]: BP0- [ 3]: BP1- [ 4]: BP2- [ 5]: TB- [ 6]: SEC- [ 7]: SRP0- [ 8]: SRP1- [ 9]: QE- [11]: LB1- [12]: LB2- [13]: LB3- [14]: CMP- [15]: SUS- [18]: WPS- [21]: DRV0- [22]: DRV1- [23]: HOLD /RST"; + } STATUS[23:2]; + } FLASH_STATUS @ 0x28; + + reg { + desc = "JEDEC Continuation Code configuration register.Read JEDEC ID must return the continuation code if the manufacturer IDis not shown in the first page of JEDEC table. This register controlsthe Continuation Code."; + field { + sw = rw; + hw = r; + reset = 0x7f; + desc = "Continuation Code byte"; + } CC[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "The number that Continuation Code repeats"; + } NUM_CC[15:8]; + } JEDEC_CC @ 0x2C; + + reg { + desc = "JEDEC ID register."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Device ID"; + } ID[15:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Manufacturer ID"; + } MF[23:16]; + } JEDEC_ID @ 0x30; + + reg { + desc = "Read Buffer threshold register."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 0, disable the watermark. If non-zero, when the hostaccess above or equal to the threshold, it reports an interrupt.The value is byte-granularity not SRAM index."; + } THRESHOLD[9:0]; + } READ_THRESHOLD @ 0x34; + + reg { + desc = "Mailbox Base address register.The mailbox size is fixed. In this version of IP, the size is 1kB.Lower 10 bits of the Mailbox address is tied to 0."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Mailbox Address. Lower 10 bits are ignored"; + } ADDR[31:0]; + } MAILBOX_ADDR @ 0x38; + + reg { + desc = "Upload module status register."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Command FIFO Entry"; + } CMDFIFO_DEPTH[4:0]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Upload Command FIFO Not Empty"; + } CMDFIFO_NOTEMPTY[7:7]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Address FIFO Entry"; + } ADDRFIFO_DEPTH[12:8]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Upload Address FIFO Not Empty"; + } ADDRFIFO_NOTEMPTY[15:15]; + } UPLOAD_STATUS @ 0x3C; + + reg { + desc = "Upload module status 2 register.This register contains payload related status. payload_depth indicatesthe payload size (from 0 to 256 bytes).payload_start_idx indicates the start of the 256B. This stays 0usually. However, when the SPI host system issues more than 256B ofpayload in a command, this field may not be 0. For example, if thesystem issues 258B payload, the payload_depth is 256 (as the IP onlyholds 256B of payload), the payload_start_idx is 2. SW should read from2 to 255 then 0 and 1."; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Payload buffer depth"; + } PAYLOAD_DEPTH[8:0]; + field { + sw = r; + hw = w; + reset = 0x0; + desc = "Payload Start Index"; + } PAYLOAD_START_IDX[23:16]; + } UPLOAD_STATUS2 @ 0x40; + + external reg { + hwre = true; + desc = "Command Fifo Read Port."; + field { + sw = r; + hw = rw; + desc = "command opcode"; + } DATA[7:0]; + field { + sw = r; + hw = rw; + desc = "State of BUSY bit at command time"; + } BUSY[13:13]; + field { + sw = r; + hw = rw; + desc = "State of WEL bit at command time"; + } WEL[14:14]; + field { + sw = r; + hw = rw; + desc = "1 if address mode at command time is 4 Bytes, else 3 Bytes"; + } ADDR4B_MODE[15:15]; + } UPLOAD_CMDFIFO @ 0x44; + + external reg { + hwre = true; + desc = "Address Fifo Read Port."; + field { + sw = r; + hw = rw; + desc = "read data"; + } DATA[31:0]; + } UPLOAD_ADDRFIFO @ 0x48; + + reg { + desc = "Address Swap Mask register.This register is used in the SPI passthrough mode. If any of bits inthis register is set, the corresponding address bit in the SPI Readcommands is replaced with the data from !!ADDR_SWAP_DATA.If 3B address mode is active, upper 8bit [31:24] is ignored."; + field { + sw = rw; + hw = r; + reset = false; + desc = "When a bit is 1, the SPI read address to the downstream SPIFlash device is swapped to !!ADDR_SWAP_DATA."; + } MASK[31:0]; + } ADDR_SWAP_MASK @ 0x6C; + + reg { + desc = "The address value for the address swap feature."; + field { + sw = rw; + hw = r; + reset = false; + desc = "Desired value to be swapped for the SPI read commands."; + } DATA[31:0]; + } ADDR_SWAP_DATA @ 0x70; + + reg { + desc = "Write Data Swap in the passthrough mode.PAYLOAD_SWAP_MASK CSR provides the SW to change certain bits in thefirst 4 bytes of the write payload in the passthrough mode."; + field { + sw = rw; + hw = r; + reset = false; + desc = "byte mask"; + } MASK[31:0]; + } PAYLOAD_SWAP_MASK @ 0x74; + + reg { + desc = "Write Data Swap in the passthrough mode.PAYLOAD_SWAP_DATA combined with PAYLOAD_SWAP_MASK provides the SW tochange certain bits in the first 4 bytes of the write payload in thepassthrough mode.The register should be written in Little-Endian order. [7:0] bits areprocessed in the first received payload byte. [31:24] bits for the 4thbyte."; + field { + sw = rw; + hw = r; + reset = false; + desc = "replaced data"; + } DATA[31:0]; + } PAYLOAD_SWAP_DATA @ 0x78; + + reg { + desc = "Opcode for EN4B.If the register is active, it affects in flash / passthrough modes."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "EN4B opcode"; + } OPCODE[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, Opcode affects"; + } VALID[31:31]; + } CMD_INFO_EN4B @ 0xDC; + + reg { + desc = "Opcode for EX4B"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "EX4B opcode"; + } OPCODE[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, Opcode affects"; + } VALID[31:31]; + } CMD_INFO_EX4B @ 0xE0; + + reg { + desc = "Opcode for Write Enable (WREN)"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "WREN opcode"; + } OPCODE[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, opcode affects"; + } VALID[31:31]; + } CMD_INFO_WREN @ 0xE4; + + reg { + desc = "Opcode for Write Disable (WRDI)"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "WRDI opcode"; + } OPCODE[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, opcode affects"; + } VALID[31:31]; + } CMD_INFO_WRDI @ 0xE8; + + reg { + desc = "TPM HWIP Capability register.This register shows the features the current TPM HWIP supports."; + field { + sw = r; + hw = w; + reset = false; + desc = "Revision of the TPM submodule"; + } REV[7:0]; + field { + sw = r; + hw = w; + reset = true; + desc = "If 1, the TPM submodule supports 5 Locality.If 0, only one Locality is provided"; + } LOCALITY[8:8]; + field { + sw = r; + hw = w; + reset = 0x6; + desc = "The maximum write size in bytes the TPM submodule supports.The value is the exponent of the 2.- 3'b 010: Support up to 4B- 3'b 011: Support up to 8B- 3'b 100: Support up to 16B- 3'b 101: Support up to 32B- 3'b 110: Support up to 64BAll other values are reserved.It is not recommended for SW to advertise TPM supporting more than max_wr_size to the South Bridge."; + } MAX_WR_SIZE[18:16]; + field { + sw = r; + hw = w; + reset = 0x6; + desc = "The maximum read size in bytes the TPM submodule supports.The value is the exponent of the 2.- 3'b 010: Support up to 4B- 3'b 011: Support up to 8B- 3'b 100: Support up to 16B- 3'b 101: Support up to 32B- 3'b 110: Support up to 64BAll other values are reserved.It is not recommended for SW to advertise TPM supporting more than max_rd_size to the South Bridge."; + } MAX_RD_SIZE[22:20]; + } TPM_CAP @ 0x800; + + reg { + desc = "TPM Configuration register."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, TPM submodule accepts the transactions over SPI"; + } EN[0:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Configure the TPM mode. 1 for CRB, 0 for FIFO.If the SW set this field to 1, the HW logic always pushes thecommand/addr and write data to buffers. The logic does not comparethe incoming address to the list of managed-by-HW registeraddresses.The invalid locality check still runs based on the invalid_localityconfiguration."; + } TPM_MODE[1:1]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 0, TPM submodule directly returns the return-by-HW registers for the read requests.If 1, TPM submodule uploads the TPM command regardless of the address, and the SW may return the value through the read FIFO."; + } HW_REG_DIS[2:2]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, the logic does not compare the upper 8 bit of thereceived address with the TpmAddr constant, D4h.If this field is 0, the HW uploads the command, address, and writepayload to the buffers in case of address that is not 0xD4_XXXX."; + } TPM_REG_CHK_DIS[3:3]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, TPM submodule returns the invalid data (0xFF) for theout of the max Locality request.If it is a write request, HW still uploads the command and address.SW needs to process the incoming invalid command.If 0, TPM submodule uploads the TPM command and address. The SW maywrite 0xFF to the read FIFO.Note: The TPM submodule uploads the TPM commands that do not fallinto the FIFO registers (0xD4_XXXX) regardless ofinvalid_locality bit."; + } INVALID_LOCALITY[4:4]; + } TPM_CFG @ 0x804; + + external reg { + desc = "TPM submodule state register.The TPM_STATUS CSR provides the current TPM status, mostly the buffer and FIFO status."; + field { + sw = r; + hw = w; + swmod = true; + desc = "If 1, the TPM_CMD_ADDR has a valid data. This status is reported via the interrupt also."; + } CMDADDR_NOTEMPTY[0:0]; + field { + sw = rw; + onwrite = wzc; + hw = rw; + swmod = true; + desc = "If 1, the Write FIFO is reserved for software processing.This bit becomes 1 when a complete write command is received.While it remains 1, subsequent write commands will block at the wait state until it is cleared.Write 0 to release the Write FIFO back to the TPM module."; + } WRFIFO_PENDING[1:1]; + field { + sw = r; + hw = w; + swmod = true; + desc = "If 1, the last Read FIFO command was aborted.This bit becomes 1 when a Read FIFO command became active, but the transaction did not complete.An aborted transaction occurs when the host de-asserts CSB without clocking all the requested data.This bit remains 1 until reset, or it will clear automatically after the next valid command is read from TPM_CMD_ADDR."; + } RDFIFO_ABORTED[2:2]; + } TPM_STATUS @ 0x808; + + reg { + desc = "TPM_STS_x register.The register is mirrored to all Localities.The value is returned to the host system only when the activeLocalityin the TPM_ACCESS_x is matched to the current received Locality."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_STS_x"; + } STS[31:0]; + } TPM_STS @ 0x814; + + reg { + desc = "TPM_INTF_CAPABILITY"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_INTF_CAPABILITY"; + } INTF_CAPABILITY[31:0]; + } TPM_INTF_CAPABILITY @ 0x818; + + reg { + desc = "TPM_INT_ENABLE"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_INT_ENABLE"; + } INT_ENABLE[31:0]; + } TPM_INT_ENABLE @ 0x81C; + + reg { + desc = "TPM_INT_VECTOR"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_INT_VECTOR"; + } INT_VECTOR[7:0]; + } TPM_INT_VECTOR @ 0x820; + + reg { + desc = "TPM_INT_STATUS"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_INT_STATUS"; + } INT_STATUS[31:0]; + } TPM_INT_STATUS @ 0x824; + + reg { + desc = "TPM_DID/ TPM_VID register"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_VID"; + } VID[15:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_DID"; + } DID[31:16]; + } TPM_DID_VID @ 0x828; + + reg { + desc = "TPM_RID"; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_RID"; + } RID[7:0]; + } TPM_RID @ 0x82C; + + external reg { + hwre = true; + desc = "TPM Command and Address bufferThe SW may get the received TPM command and address by reading this CSR."; + field { + sw = r; + hw = rw; + swmod = true; + desc = "received address"; + } ADDR[23:0]; + field { + sw = r; + hw = rw; + swmod = true; + desc = "received command"; + } CMD[31:24]; + } TPM_CMD_ADDR @ 0x830; + + external reg { + desc = "TPM Read command return data FIFO.The write port of the read command FIFO."; + field { + sw = w; + hw = r; + swmod = true; + desc = "write port of the read FIFO"; + } VALUE[31:0]; + } TPM_READ_FIFO @ 0x834; + + reg { + compacted = true; + desc = "Command FilterIf a bit in this CSR is 1, then corresponding SPI command w.r.t thebit position among 256 bit is dropped in SPI Passthrough mode."; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_0[0:0]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_1[1:1]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_2[2:2]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_3[3:3]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_4[4:4]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_5[5:5]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_6[6:6]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_7[7:7]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_8[8:8]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_9[9:9]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_10[10:10]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_11[11:11]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_12[12:12]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_13[13:13]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_14[14:14]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_15[15:15]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_16[16:16]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_17[17:17]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_18[18:18]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_19[19:19]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_20[20:20]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_21[21:21]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_22[22:22]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_23[23:23]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_24[24:24]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_25[25:25]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_26[26:26]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_27[27:27]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_28[28:28]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_29[29:29]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_30[30:30]; + field { + sw = rw; + hw = r; + reset = false; + desc = "If 1, command will be filtered"; + } FILTER_31[31:31]; + } CMD_FILTER[8] @ 0x4C; + + reg { + desc = "Command Info register."; + field { + sw = rw; + hw = r; + reset = false; + desc = "Command Opcode"; + } OPCODE[7:0]; + field { + sw = rw; + hw = r; + reset = false; + desc = "Command address modeA command can have four modes:- 0: Command does not have an address field- 1: CFG.addr_4b_en decides the address size (3B/4B)- 2: Address size is always 3B regardless of CFG.addr_4b_en- 3: Address size is always 4B regardless of CFG.addr_4b_en"; + } ADDR_MODE[9:8]; + field { + sw = rw; + hw = r; + reset = false; + desc = "This field is used in the passthrough logic.If this field is set to 1, the address in the passthrough commandis replaced to the preconfigured value."; + } ADDR_SWAP_EN[10:10]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "If 1, the command has a MByte field following theaddress field. This is set to 1 for DualIO, QuadIO commands."; + } MBYTE_EN[11:11]; + field { + sw = rw; + hw = r; + reset = 0x7; + desc = "The number of dummy cycles -1 for the command"; + } DUMMY_SIZE[14:12]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Set to 1 if the command has a dummy cycle following the address field."; + } DUMMY_EN[15:15]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Payload Enable per SPI lane.Set to non-zero if the command has payload at the end of theprotocol. This field has four bits. Each bit represents the SPIline. If a command is a Single IO command and returns data to thehost system, the data is returned on the MISO line (IO[1]). Inthis case, SW sets payload_en to 4'b 0010."; + } PAYLOAD_EN[19:16]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Set to 1 if the command returns data. If 0, the payloadsends to the downstream Flash device."; + } PAYLOAD_DIR[20:20]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Swap the first byte of the write payload.If payload_swap_en is set, the passthrough logic swaps the first byte of the write payload with DATA_SWAP CSR.payload_swap_en only works with write data and SingleIO mode. payload_en must be 4'b 0001 and paylod_dir to be PayloadIn."; + } PAYLOAD_SWAP_EN[21:21]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Add 2-stage pipeline to read payload.If read_pipeline_mode is not set to zero_stages, the read logic adds a 2-stage pipeline to the read data for this command.This read pipeline enables higher throughput for certain read commands in passthrough mode.payload_dir must be set to PayloadOut: payload_pipeline_en only works with read data.It may be used with any IO mode, but general host compatibility is likely limited to Quad Read.If this pipeline is used for passthrough, the internal SFDP should report 2 additional dummy cycles compared to the downstream flash.SFDP read commands should be processed internally, and dummy_size should still reflect the downstream device's dummy cycle count."; + } READ_PIPELINE_MODE[23:22]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Set to 1 to upload the command.If upload field in the command info entry is set, the cmdparseactivates the upload submodule when the opcode is received.addr_en, addr_4B_affected, and addr_4b_forced (TBD) affectthe upload functionality. The three address related configsdefines the command address field size.The logic assumes the following SPI input stream as payload,which max size is 256B. If the command exceeds the maximumpayload size 256B, the logic wraps the payload and overwrites."; + } UPLOAD[24:24]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Set to 1 to set the BUSY bit in the FLASH_STATUS when thecommand is received. This bit is active only when upload bit isset."; + } BUSY[25:25]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "Set to 1 if the config in the register is valid"; + } VALID[31:31]; + } CMD_INFO[24] @ 0x7C; + + reg { + desc = "TPM_ACCESS_x register."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_ACCESS"; + } ACCESS_0[7:0]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_ACCESS"; + } ACCESS_1[15:8]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_ACCESS"; + } ACCESS_2[23:16]; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "TPM_ACCESS"; + } ACCESS_3[31:24]; + } TPM_ACCESS_0 @ 0x80C; + + reg { + desc = "TPM_ACCESS_x register."; + field { + sw = rw; + hw = r; + reset = 0x0; + desc = "For TPM1"; + } ACCESS_4[7:0]; + } TPM_ACCESS_1 @ 0x810; + + external mem { + memwidth = 0x20; + mementries = 0x350; + sw = w; + } EGRESS_BUFFER @ 0x1000; + + external mem { + memwidth = 0x20; + mementries = 0x70; + sw = r; + } INGRESS_BUFFER @ 0x1E00; + +}; diff --git a/rdl2ot/tests/snapshots/spi_device_reg_pkg.sv b/rdl2ot/tests/snapshots/spi_device_reg_pkg.sv new file mode 100644 index 0000000..73752f9 --- /dev/null +++ b/rdl2ot/tests/snapshots/spi_device_reg_pkg.sv @@ -0,0 +1,926 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `rdl2ot` containing data structure + +package spi_device_reg_pkg; + + // Param list + parameter int SramDepth = 1024; + parameter int SramEgressDepth = 848; + parameter int SramIngressDepth = 112; + parameter int SramReadBufferOffset = 0; + parameter int SramReadBufferDepth = 512; + parameter int SramMailboxOffset = 512; + parameter int SramMailboxDepth = 256; + parameter int SramSfdpOffset = 768; + parameter int SramSfdpDepth = 64; + parameter int SramTpmRdFifoOffset = 832; + parameter int SramTpmRdFifoDepth = 16; + parameter int SramPayloadOffset = 0; + parameter int SramPayloadDepth = 64; + parameter int SramCmdFifoOffset = 64; + parameter int SramCmdFifoDepth = 16; + parameter int SramAddrFifoOffset = 80; + parameter int SramAddrFifoDepth = 16; + parameter int SramTpmWrFifoOffset = 96; + parameter int SramTpmWrFifoDepth = 16; + parameter int NumCmdInfo = 24; + parameter int NumLocality = 5; + parameter int TpmRdFifoPtrW = 5; + parameter int TpmRdFifoWidth = 32; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 13; + + // Number of registers for every interface + parameter int NumRegs = 73; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } spi_device_alert_idx_t; + + /////////////////////////////////////////////// + // Typedefs for registers for interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } tpm_rdfifo_drop; + struct packed { + logic q; + } tpm_rdfifo_cmd_end; + struct packed { + logic q; + } tpm_header_not_empty; + struct packed { + logic q; + } readbuf_flip; + struct packed { + logic q; + } readbuf_watermark; + struct packed { + logic q; + } upload_payload_overflow; + struct packed { + logic q; + } upload_payload_not_empty; + struct packed { + logic q; + } upload_cmdfifo_not_empty; + } spi_device_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } tpm_rdfifo_drop; + struct packed { + logic q; + } tpm_rdfifo_cmd_end; + struct packed { + logic q; + } tpm_header_not_empty; + struct packed { + logic q; + } readbuf_flip; + struct packed { + logic q; + } readbuf_watermark; + struct packed { + logic q; + } upload_payload_overflow; + struct packed { + logic q; + } upload_payload_not_empty; + struct packed { + logic q; + } upload_cmdfifo_not_empty; + } spi_device_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } tpm_rdfifo_drop; + struct packed { + logic q; + logic qe; + } tpm_rdfifo_cmd_end; + struct packed { + logic q; + logic qe; + } tpm_header_not_empty; + struct packed { + logic q; + logic qe; + } readbuf_flip; + struct packed { + logic q; + logic qe; + } readbuf_watermark; + struct packed { + logic q; + logic qe; + } upload_payload_overflow; + struct packed { + logic q; + logic qe; + } upload_payload_not_empty; + struct packed { + logic q; + logic qe; + } upload_cmdfifo_not_empty; + } spi_device_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } spi_device_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } mode; + struct packed { + logic q; + } flash_read_buffer_clr; + struct packed { + logic q; + } flash_status_fifo_clr; + } spi_device_reg2hw_control_reg_t; + + typedef struct packed { + struct packed { + logic q; + } mailbox_en; + struct packed { + logic q; + } rx_order; + struct packed { + logic q; + } tx_order; + } spi_device_reg2hw_cfg_reg_t; + + typedef struct packed { + struct packed { + logic q; + } mbx; + struct packed { + logic q; + } sfdp; + struct packed { + logic q; + } jedec; + struct packed { + logic q; + } status; + } spi_device_reg2hw_intercept_en_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } addr_4b_en; + } spi_device_reg2hw_addr_mode_reg_t; + + typedef struct packed { + struct packed { + logic [21:0] q; + logic qe; + } status; + struct packed { + logic q; + logic qe; + } wel; + struct packed { + logic q; + logic qe; + } busy; + } spi_device_reg2hw_flash_status_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } num_cc; + struct packed { + logic [7:0] q; + } cc; + } spi_device_reg2hw_jedec_cc_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } mf; + struct packed { + logic [15:0] q; + } id; + } spi_device_reg2hw_jedec_id_reg_t; + + typedef struct packed { + logic [9:0] q; + } spi_device_reg2hw_read_threshold_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_mailbox_addr_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic re; + } addr4b_mode; + struct packed { + logic q; + logic re; + } wel; + struct packed { + logic q; + logic re; + } busy; + struct packed { + logic [7:0] q; + logic re; + } data; + } spi_device_reg2hw_upload_cmdfifo_reg_t; + + typedef struct packed { + logic [31:0] q; + logic re; + } spi_device_reg2hw_upload_addrfifo_reg_t; + + typedef struct packed { + logic q; + } spi_device_reg2hw_cmd_filter_mreg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_addr_swap_mask_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_addr_swap_data_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_payload_swap_mask_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_payload_swap_data_reg_t; + + typedef struct packed { + struct packed { + logic q; + } valid; + struct packed { + logic q; + } busy; + struct packed { + logic q; + } upload; + struct packed { + logic [1:0] q; + } read_pipeline_mode; + struct packed { + logic q; + } payload_swap_en; + struct packed { + logic q; + } payload_dir; + struct packed { + logic [3:0] q; + } payload_en; + struct packed { + logic q; + } dummy_en; + struct packed { + logic [2:0] q; + } dummy_size; + struct packed { + logic q; + } mbyte_en; + struct packed { + logic q; + } addr_swap_en; + struct packed { + logic [1:0] q; + } addr_mode; + struct packed { + logic [7:0] q; + } opcode; + } spi_device_reg2hw_cmd_info_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } valid; + struct packed { + logic [7:0] q; + } opcode; + } spi_device_reg2hw_cmd_info_en4b_reg_t; + + typedef struct packed { + struct packed { + logic q; + } valid; + struct packed { + logic [7:0] q; + } opcode; + } spi_device_reg2hw_cmd_info_ex4b_reg_t; + + typedef struct packed { + struct packed { + logic q; + } valid; + struct packed { + logic [7:0] q; + } opcode; + } spi_device_reg2hw_cmd_info_wren_reg_t; + + typedef struct packed { + struct packed { + logic q; + } valid; + struct packed { + logic [7:0] q; + } opcode; + } spi_device_reg2hw_cmd_info_wrdi_reg_t; + + typedef struct packed { + struct packed { + logic q; + } invalid_locality; + struct packed { + logic q; + } tpm_reg_chk_dis; + struct packed { + logic q; + } hw_reg_dis; + struct packed { + logic q; + } tpm_mode; + struct packed { + logic q; + } en; + } spi_device_reg2hw_tpm_cfg_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } wrfifo_pending; + } spi_device_reg2hw_tpm_status_reg_t; + + typedef struct packed { + logic [7:0] q; + } spi_device_reg2hw_tpm_access_0_reg_t; + + typedef struct packed { + logic [7:0] q; + } spi_device_reg2hw_tpm_access_1_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_tpm_sts_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_tpm_intf_capability_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_tpm_int_enable_reg_t; + + typedef struct packed { + logic [7:0] q; + } spi_device_reg2hw_tpm_int_vector_reg_t; + + typedef struct packed { + logic [31:0] q; + } spi_device_reg2hw_tpm_int_status_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } did; + struct packed { + logic [15:0] q; + } vid; + } spi_device_reg2hw_tpm_did_vid_reg_t; + + typedef struct packed { + logic [7:0] q; + } spi_device_reg2hw_tpm_rid_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + logic qe; + logic re; + } cmd; + struct packed { + logic [23:0] q; + logic qe; + logic re; + } addr; + } spi_device_reg2hw_tpm_cmd_addr_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } spi_device_reg2hw_tpm_read_fifo_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } tpm_rdfifo_drop; + struct packed { + logic d; + logic de; + } tpm_rdfifo_cmd_end; + struct packed { + logic d; + logic de; + } tpm_header_not_empty; + struct packed { + logic d; + logic de; + } readbuf_flip; + struct packed { + logic d; + logic de; + } readbuf_watermark; + struct packed { + logic d; + logic de; + } upload_payload_overflow; + struct packed { + logic d; + logic de; + } upload_payload_not_empty; + struct packed { + logic d; + logic de; + } upload_cmdfifo_not_empty; + } spi_device_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } flash_read_buffer_clr; + struct packed { + logic d; + logic de; + } flash_status_fifo_clr; + } spi_device_hw2reg_control_reg_t; + + typedef struct packed { + struct packed { + logic d; + } tpm_csb; + struct packed { + logic d; + } csb; + } spi_device_hw2reg_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + } pending; + struct packed { + logic d; + } addr_4b_en; + } spi_device_hw2reg_addr_mode_reg_t; + + typedef struct packed { + logic [31:0] d; + } spi_device_hw2reg_last_read_addr_reg_t; + + typedef struct packed { + struct packed { + logic [21:0] d; + } status; + struct packed { + logic d; + } wel; + struct packed { + logic d; + } busy; + } spi_device_hw2reg_flash_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } addrfifo_notempty; + struct packed { + logic [4:0] d; + logic de; + } addrfifo_depth; + struct packed { + logic d; + logic de; + } cmdfifo_notempty; + struct packed { + logic [4:0] d; + logic de; + } cmdfifo_depth; + } spi_device_hw2reg_upload_status_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] d; + logic de; + } payload_start_idx; + struct packed { + logic [8:0] d; + logic de; + } payload_depth; + } spi_device_hw2reg_upload_status2_reg_t; + + typedef struct packed { + struct packed { + logic d; + } addr4b_mode; + struct packed { + logic d; + } wel; + struct packed { + logic d; + } busy; + struct packed { + logic [7:0] d; + } data; + } spi_device_hw2reg_upload_cmdfifo_reg_t; + + typedef struct packed { + logic [31:0] d; + } spi_device_hw2reg_upload_addrfifo_reg_t; + + typedef struct packed { + struct packed { + logic [2:0] d; + logic de; + } max_rd_size; + struct packed { + logic [2:0] d; + logic de; + } max_wr_size; + struct packed { + logic d; + logic de; + } locality; + struct packed { + logic [7:0] d; + logic de; + } rev; + } spi_device_hw2reg_tpm_cap_reg_t; + + typedef struct packed { + struct packed { + logic d; + } rdfifo_aborted; + struct packed { + logic d; + } wrfifo_pending; + struct packed { + logic d; + } cmdaddr_notempty; + } spi_device_hw2reg_tpm_status_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] d; + } cmd; + struct packed { + logic [23:0] d; + } addr; + } spi_device_hw2reg_tpm_cmd_addr_reg_t; + + // Register -> HW type for interface + typedef struct packed { + spi_device_reg2hw_intr_state_reg_t intr_state; + spi_device_reg2hw_intr_enable_reg_t intr_enable; + spi_device_reg2hw_intr_test_reg_t intr_test; + spi_device_reg2hw_alert_test_reg_t alert_test; + spi_device_reg2hw_control_reg_t control; + spi_device_reg2hw_cfg_reg_t cfg; + spi_device_reg2hw_intercept_en_reg_t intercept_en; + spi_device_reg2hw_addr_mode_reg_t addr_mode; + spi_device_reg2hw_flash_status_reg_t flash_status; + spi_device_reg2hw_jedec_cc_reg_t jedec_cc; + spi_device_reg2hw_jedec_id_reg_t jedec_id; + spi_device_reg2hw_read_threshold_reg_t read_threshold; + spi_device_reg2hw_mailbox_addr_reg_t mailbox_addr; + spi_device_reg2hw_upload_cmdfifo_reg_t upload_cmdfifo; + spi_device_reg2hw_upload_addrfifo_reg_t upload_addrfifo; + spi_device_reg2hw_cmd_filter_mreg_t [255:0] cmd_filter; + spi_device_reg2hw_addr_swap_mask_reg_t addr_swap_mask; + spi_device_reg2hw_addr_swap_data_reg_t addr_swap_data; + spi_device_reg2hw_payload_swap_mask_reg_t payload_swap_mask; + spi_device_reg2hw_payload_swap_data_reg_t payload_swap_data; + spi_device_reg2hw_cmd_info_mreg_t [23:0] cmd_info; + spi_device_reg2hw_cmd_info_en4b_reg_t cmd_info_en4b; + spi_device_reg2hw_cmd_info_ex4b_reg_t cmd_info_ex4b; + spi_device_reg2hw_cmd_info_wren_reg_t cmd_info_wren; + spi_device_reg2hw_cmd_info_wrdi_reg_t cmd_info_wrdi; + spi_device_reg2hw_tpm_cfg_reg_t tpm_cfg; + spi_device_reg2hw_tpm_status_reg_t tpm_status; + spi_device_reg2hw_tpm_access_0_reg_t [3:0] tpm_access_0; + spi_device_reg2hw_tpm_access_1_reg_t tpm_access_1; + spi_device_reg2hw_tpm_sts_reg_t tpm_sts; + spi_device_reg2hw_tpm_intf_capability_reg_t tpm_intf_capability; + spi_device_reg2hw_tpm_int_enable_reg_t tpm_int_enable; + spi_device_reg2hw_tpm_int_vector_reg_t tpm_int_vector; + spi_device_reg2hw_tpm_int_status_reg_t tpm_int_status; + spi_device_reg2hw_tpm_did_vid_reg_t tpm_did_vid; + spi_device_reg2hw_tpm_rid_reg_t tpm_rid; + spi_device_reg2hw_tpm_cmd_addr_reg_t tpm_cmd_addr; + spi_device_reg2hw_tpm_read_fifo_reg_t tpm_read_fifo; + } spi_device_reg2hw_t; + + // HW -> register type for interface + typedef struct packed { + spi_device_hw2reg_intr_state_reg_t intr_state; + spi_device_hw2reg_control_reg_t control; + spi_device_hw2reg_status_reg_t status; + spi_device_hw2reg_addr_mode_reg_t addr_mode; + spi_device_hw2reg_last_read_addr_reg_t last_read_addr; + spi_device_hw2reg_flash_status_reg_t flash_status; + spi_device_hw2reg_upload_status_reg_t upload_status; + spi_device_hw2reg_upload_status2_reg_t upload_status2; + spi_device_hw2reg_upload_cmdfifo_reg_t upload_cmdfifo; + spi_device_hw2reg_upload_addrfifo_reg_t upload_addrfifo; + spi_device_hw2reg_tpm_cap_reg_t tpm_cap; + spi_device_hw2reg_tpm_status_reg_t tpm_status; + spi_device_hw2reg_tpm_cmd_addr_reg_t tpm_cmd_addr; + } spi_device_hw2reg_t; + + // Register offsets for interface + parameter logic [BlockAw-1:0] SPI_DEVICE_INTR_STATE_OFFSET = 13'h 0; + parameter logic [BlockAw-1:0] SPI_DEVICE_INTR_ENABLE_OFFSET = 13'h 4; + parameter logic [BlockAw-1:0] SPI_DEVICE_INTR_TEST_OFFSET = 13'h 8; + parameter logic [BlockAw-1:0] SPI_DEVICE_ALERT_TEST_OFFSET = 13'h c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CONTROL_OFFSET = 13'h 10; + parameter logic [BlockAw-1:0] SPI_DEVICE_CFG_OFFSET = 13'h 14; + parameter logic [BlockAw-1:0] SPI_DEVICE_STATUS_OFFSET = 13'h 18; + parameter logic [BlockAw-1:0] SPI_DEVICE_INTERCEPT_EN_OFFSET = 13'h 1c; + parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_MODE_OFFSET = 13'h 20; + parameter logic [BlockAw-1:0] SPI_DEVICE_LAST_READ_ADDR_OFFSET = 13'h 24; + parameter logic [BlockAw-1:0] SPI_DEVICE_FLASH_STATUS_OFFSET = 13'h 28; + parameter logic [BlockAw-1:0] SPI_DEVICE_JEDEC_CC_OFFSET = 13'h 2c; + parameter logic [BlockAw-1:0] SPI_DEVICE_JEDEC_ID_OFFSET = 13'h 30; + parameter logic [BlockAw-1:0] SPI_DEVICE_READ_THRESHOLD_OFFSET = 13'h 34; + parameter logic [BlockAw-1:0] SPI_DEVICE_MAILBOX_ADDR_OFFSET = 13'h 38; + parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_STATUS_OFFSET = 13'h 3c; + parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_STATUS2_OFFSET = 13'h 40; + parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET = 13'h 44; + parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET = 13'h 48; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_0_OFFSET = 13'h 4c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_1_OFFSET = 13'h 50; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_2_OFFSET = 13'h 54; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_3_OFFSET = 13'h 58; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_4_OFFSET = 13'h 5c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_5_OFFSET = 13'h 60; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_6_OFFSET = 13'h 64; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_7_OFFSET = 13'h 68; + parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_MASK_OFFSET = 13'h 6c; + parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_DATA_OFFSET = 13'h 70; + parameter logic [BlockAw-1:0] SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET = 13'h 74; + parameter logic [BlockAw-1:0] SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET = 13'h 78; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_0_OFFSET = 13'h 7c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_1_OFFSET = 13'h 80; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_2_OFFSET = 13'h 84; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_3_OFFSET = 13'h 88; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_4_OFFSET = 13'h 8c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_5_OFFSET = 13'h 90; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_6_OFFSET = 13'h 94; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_7_OFFSET = 13'h 98; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_8_OFFSET = 13'h 9c; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_9_OFFSET = 13'h a0; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_10_OFFSET = 13'h a4; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_11_OFFSET = 13'h a8; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_12_OFFSET = 13'h ac; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_13_OFFSET = 13'h b0; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_14_OFFSET = 13'h b4; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_15_OFFSET = 13'h b8; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_16_OFFSET = 13'h bc; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_17_OFFSET = 13'h c0; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_18_OFFSET = 13'h c4; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_19_OFFSET = 13'h c8; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_20_OFFSET = 13'h cc; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_21_OFFSET = 13'h d0; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_22_OFFSET = 13'h d4; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_23_OFFSET = 13'h d8; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_EN4B_OFFSET = 13'h dc; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_EX4B_OFFSET = 13'h e0; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_WREN_OFFSET = 13'h e4; + parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_WRDI_OFFSET = 13'h e8; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_CAP_OFFSET = 13'h 800; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_CFG_OFFSET = 13'h 804; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_STATUS_OFFSET = 13'h 808; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_ACCESS_0_OFFSET = 13'h 80c; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_ACCESS_1_OFFSET = 13'h 810; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_STS_OFFSET = 13'h 814; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET = 13'h 818; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_INT_ENABLE_OFFSET = 13'h 81c; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_INT_VECTOR_OFFSET = 13'h 820; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_INT_STATUS_OFFSET = 13'h 824; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_DID_VID_OFFSET = 13'h 828; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_RID_OFFSET = 13'h 82c; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_CMD_ADDR_OFFSET = 13'h 830; + parameter logic [BlockAw-1:0] SPI_DEVICE_TPM_READ_FIFO_OFFSET = 13'h 834; + + // Reset values for hwext registers and their fields for interface + parameter logic [7:0] SPI_DEVICE_INTR_TEST_RESVAL = 8'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_UPLOAD_CMDFIFO_NOT_EMPTY_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_NOT_EMPTY_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_UPLOAD_PAYLOAD_OVERFLOW_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_READBUF_WATERMARK_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_READBUF_FLIP_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_RDFIFO_CMD_END_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_RDFIFO_DROP_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] SPI_DEVICE_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [6:0] SPI_DEVICE_STATUS_RESVAL = 7'h 60; + parameter logic [0:0] SPI_DEVICE_STATUS_CSB_RESVAL = 1'h 1; + parameter logic [0:0] SPI_DEVICE_STATUS_TPM_CSB_RESVAL = 1'h 1; + parameter logic [31:0] SPI_DEVICE_ADDR_MODE_RESVAL = 32'h 0; + parameter logic [31:0] SPI_DEVICE_LAST_READ_ADDR_RESVAL = 32'h 0; + parameter logic [23:0] SPI_DEVICE_FLASH_STATUS_RESVAL = 24'h 0; + parameter logic [15:0] SPI_DEVICE_UPLOAD_CMDFIFO_RESVAL = 16'h 0; + parameter logic [31:0] SPI_DEVICE_UPLOAD_ADDRFIFO_RESVAL = 32'h 0; + parameter logic [2:0] SPI_DEVICE_TPM_STATUS_RESVAL = 3'h 0; + parameter logic [31:0] SPI_DEVICE_TPM_CMD_ADDR_RESVAL = 32'h 0; + parameter logic [31:0] SPI_DEVICE_TPM_READ_FIFO_RESVAL = 32'h 0; + + // Window parameters for interface + parameter logic [BlockAw-1:0] SPI_DEVICE_EGRESS_BUFFER_OFFSET = 13'h 1000; + parameter int unsigned SPI_DEVICE_EGRESS_BUFFER_SIZE = 'h d40; + parameter int unsigned SPI_DEVICE_EGRESS_BUFFER_IDX = 0; + parameter logic [BlockAw-1:0] SPI_DEVICE_INGRESS_BUFFER_OFFSET = 13'h 1e00; + parameter int unsigned SPI_DEVICE_INGRESS_BUFFER_SIZE = 'h 1c0; + parameter int unsigned SPI_DEVICE_INGRESS_BUFFER_IDX = 1; + + // Register index for interface + typedef enum int { + SPI_DEVICE_INTR_STATE, + SPI_DEVICE_INTR_ENABLE, + SPI_DEVICE_INTR_TEST, + SPI_DEVICE_ALERT_TEST, + SPI_DEVICE_CONTROL, + SPI_DEVICE_CFG, + SPI_DEVICE_STATUS, + SPI_DEVICE_INTERCEPT_EN, + SPI_DEVICE_ADDR_MODE, + SPI_DEVICE_LAST_READ_ADDR, + SPI_DEVICE_FLASH_STATUS, + SPI_DEVICE_JEDEC_CC, + SPI_DEVICE_JEDEC_ID, + SPI_DEVICE_READ_THRESHOLD, + SPI_DEVICE_MAILBOX_ADDR, + SPI_DEVICE_UPLOAD_STATUS, + SPI_DEVICE_UPLOAD_STATUS2, + SPI_DEVICE_UPLOAD_CMDFIFO, + SPI_DEVICE_UPLOAD_ADDRFIFO, + SPI_DEVICE_CMD_FILTER_0, + SPI_DEVICE_CMD_FILTER_1, + SPI_DEVICE_CMD_FILTER_2, + SPI_DEVICE_CMD_FILTER_3, + SPI_DEVICE_CMD_FILTER_4, + SPI_DEVICE_CMD_FILTER_5, + SPI_DEVICE_CMD_FILTER_6, + SPI_DEVICE_CMD_FILTER_7, + SPI_DEVICE_ADDR_SWAP_MASK, + SPI_DEVICE_ADDR_SWAP_DATA, + SPI_DEVICE_PAYLOAD_SWAP_MASK, + SPI_DEVICE_PAYLOAD_SWAP_DATA, + SPI_DEVICE_CMD_INFO_0, + SPI_DEVICE_CMD_INFO_1, + SPI_DEVICE_CMD_INFO_2, + SPI_DEVICE_CMD_INFO_3, + SPI_DEVICE_CMD_INFO_4, + SPI_DEVICE_CMD_INFO_5, + SPI_DEVICE_CMD_INFO_6, + SPI_DEVICE_CMD_INFO_7, + SPI_DEVICE_CMD_INFO_8, + SPI_DEVICE_CMD_INFO_9, + SPI_DEVICE_CMD_INFO_10, + SPI_DEVICE_CMD_INFO_11, + SPI_DEVICE_CMD_INFO_12, + SPI_DEVICE_CMD_INFO_13, + SPI_DEVICE_CMD_INFO_14, + SPI_DEVICE_CMD_INFO_15, + SPI_DEVICE_CMD_INFO_16, + SPI_DEVICE_CMD_INFO_17, + SPI_DEVICE_CMD_INFO_18, + SPI_DEVICE_CMD_INFO_19, + SPI_DEVICE_CMD_INFO_20, + SPI_DEVICE_CMD_INFO_21, + SPI_DEVICE_CMD_INFO_22, + SPI_DEVICE_CMD_INFO_23, + SPI_DEVICE_CMD_INFO_EN4B, + SPI_DEVICE_CMD_INFO_EX4B, + SPI_DEVICE_CMD_INFO_WREN, + SPI_DEVICE_CMD_INFO_WRDI, + SPI_DEVICE_TPM_CAP, + SPI_DEVICE_TPM_CFG, + SPI_DEVICE_TPM_STATUS, + SPI_DEVICE_TPM_ACCESS_0, + SPI_DEVICE_TPM_ACCESS_1, + SPI_DEVICE_TPM_STS, + SPI_DEVICE_TPM_INTF_CAPABILITY, + SPI_DEVICE_TPM_INT_ENABLE, + SPI_DEVICE_TPM_INT_VECTOR, + SPI_DEVICE_TPM_INT_STATUS, + SPI_DEVICE_TPM_DID_VID, + SPI_DEVICE_TPM_RID, + SPI_DEVICE_TPM_CMD_ADDR, + SPI_DEVICE_TPM_READ_FIFO + } spi_device_id_e; + + // Register width information to check illegal writes for interface + parameter logic [3:0] SPI_DEVICE_PERMIT [73] = '{ + 4'b 0001, // index[ 0] SPI_DEVICE_INTR_STATE + 4'b 0001, // index[ 1] SPI_DEVICE_INTR_ENABLE + 4'b 0001, // index[ 2] SPI_DEVICE_INTR_TEST + 4'b 0001, // index[ 3] SPI_DEVICE_ALERT_TEST + 4'b 0001, // index[ 4] SPI_DEVICE_CONTROL + 4'b 1111, // index[ 5] SPI_DEVICE_CFG + 4'b 0001, // index[ 6] SPI_DEVICE_STATUS + 4'b 0001, // index[ 7] SPI_DEVICE_INTERCEPT_EN + 4'b 1111, // index[ 8] SPI_DEVICE_ADDR_MODE + 4'b 1111, // index[ 9] SPI_DEVICE_LAST_READ_ADDR + 4'b 0111, // index[10] SPI_DEVICE_FLASH_STATUS + 4'b 0011, // index[11] SPI_DEVICE_JEDEC_CC + 4'b 0111, // index[12] SPI_DEVICE_JEDEC_ID + 4'b 0011, // index[13] SPI_DEVICE_READ_THRESHOLD + 4'b 1111, // index[14] SPI_DEVICE_MAILBOX_ADDR + 4'b 0011, // index[15] SPI_DEVICE_UPLOAD_STATUS + 4'b 0111, // index[16] SPI_DEVICE_UPLOAD_STATUS2 + 4'b 0011, // index[17] SPI_DEVICE_UPLOAD_CMDFIFO + 4'b 1111, // index[18] SPI_DEVICE_UPLOAD_ADDRFIFO + 4'b 1111, // index[19] SPI_DEVICE_CMD_FILTER_0 + 4'b 1111, // index[20] SPI_DEVICE_CMD_FILTER_1 + 4'b 1111, // index[21] SPI_DEVICE_CMD_FILTER_2 + 4'b 1111, // index[22] SPI_DEVICE_CMD_FILTER_3 + 4'b 1111, // index[23] SPI_DEVICE_CMD_FILTER_4 + 4'b 1111, // index[24] SPI_DEVICE_CMD_FILTER_5 + 4'b 1111, // index[25] SPI_DEVICE_CMD_FILTER_6 + 4'b 1111, // index[26] SPI_DEVICE_CMD_FILTER_7 + 4'b 1111, // index[27] SPI_DEVICE_ADDR_SWAP_MASK + 4'b 1111, // index[28] SPI_DEVICE_ADDR_SWAP_DATA + 4'b 1111, // index[29] SPI_DEVICE_PAYLOAD_SWAP_MASK + 4'b 1111, // index[30] SPI_DEVICE_PAYLOAD_SWAP_DATA + 4'b 1111, // index[31] SPI_DEVICE_CMD_INFO_0 + 4'b 1111, // index[32] SPI_DEVICE_CMD_INFO_1 + 4'b 1111, // index[33] SPI_DEVICE_CMD_INFO_2 + 4'b 1111, // index[34] SPI_DEVICE_CMD_INFO_3 + 4'b 1111, // index[35] SPI_DEVICE_CMD_INFO_4 + 4'b 1111, // index[36] SPI_DEVICE_CMD_INFO_5 + 4'b 1111, // index[37] SPI_DEVICE_CMD_INFO_6 + 4'b 1111, // index[38] SPI_DEVICE_CMD_INFO_7 + 4'b 1111, // index[39] SPI_DEVICE_CMD_INFO_8 + 4'b 1111, // index[40] SPI_DEVICE_CMD_INFO_9 + 4'b 1111, // index[41] SPI_DEVICE_CMD_INFO_10 + 4'b 1111, // index[42] SPI_DEVICE_CMD_INFO_11 + 4'b 1111, // index[43] SPI_DEVICE_CMD_INFO_12 + 4'b 1111, // index[44] SPI_DEVICE_CMD_INFO_13 + 4'b 1111, // index[45] SPI_DEVICE_CMD_INFO_14 + 4'b 1111, // index[46] SPI_DEVICE_CMD_INFO_15 + 4'b 1111, // index[47] SPI_DEVICE_CMD_INFO_16 + 4'b 1111, // index[48] SPI_DEVICE_CMD_INFO_17 + 4'b 1111, // index[49] SPI_DEVICE_CMD_INFO_18 + 4'b 1111, // index[50] SPI_DEVICE_CMD_INFO_19 + 4'b 1111, // index[51] SPI_DEVICE_CMD_INFO_20 + 4'b 1111, // index[52] SPI_DEVICE_CMD_INFO_21 + 4'b 1111, // index[53] SPI_DEVICE_CMD_INFO_22 + 4'b 1111, // index[54] SPI_DEVICE_CMD_INFO_23 + 4'b 1111, // index[55] SPI_DEVICE_CMD_INFO_EN4B + 4'b 1111, // index[56] SPI_DEVICE_CMD_INFO_EX4B + 4'b 1111, // index[57] SPI_DEVICE_CMD_INFO_WREN + 4'b 1111, // index[58] SPI_DEVICE_CMD_INFO_WRDI + 4'b 0111, // index[59] SPI_DEVICE_TPM_CAP + 4'b 0001, // index[60] SPI_DEVICE_TPM_CFG + 4'b 0001, // index[61] SPI_DEVICE_TPM_STATUS + 4'b 1111, // index[62] SPI_DEVICE_TPM_ACCESS_0 + 4'b 0001, // index[63] SPI_DEVICE_TPM_ACCESS_1 + 4'b 1111, // index[64] SPI_DEVICE_TPM_STS + 4'b 1111, // index[65] SPI_DEVICE_TPM_INTF_CAPABILITY + 4'b 1111, // index[66] SPI_DEVICE_TPM_INT_ENABLE + 4'b 0001, // index[67] SPI_DEVICE_TPM_INT_VECTOR + 4'b 1111, // index[68] SPI_DEVICE_TPM_INT_STATUS + 4'b 1111, // index[69] SPI_DEVICE_TPM_DID_VID + 4'b 0001, // index[70] SPI_DEVICE_TPM_RID + 4'b 1111, // index[71] SPI_DEVICE_TPM_CMD_ADDR + 4'b 1111 // index[72] SPI_DEVICE_TPM_READ_FIFO + }; + +endpackage \ No newline at end of file diff --git a/rdl2ot/tests/snapshots/spi_device_reg_top.sv b/rdl2ot/tests/snapshots/spi_device_reg_top.sv new file mode 100644 index 0000000..83644d6 --- /dev/null +++ b/rdl2ot/tests/snapshots/spi_device_reg_top.sv @@ -0,0 +1,22109 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `rdl2ot` + +`include "prim_assert.sv" + +module spi_device_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[spi_device_reg_pkg::NumRegs] = + '{spi_device_reg_pkg::NumRegs{0}} + ) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o [2], + input tlul_pkg::tl_d2h_t tl_win_i [2], + // To HW + output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write + input spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import spi_device_reg_pkg::* ; + + localparam int AW = 13; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [72:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(73) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + tlul_pkg::tl_h2d_t tl_socket_h2d [3]; + tlul_pkg::tl_d2h_t tl_socket_d2h [3]; + + logic [1:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[2]; + assign tl_socket_d2h[2] = tl_reg_d2h; + + assign tl_win_o[0] = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i[0]; + assign tl_win_o[1] = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_win_i[1]; + + // Create Socket_1n + tlul_socket_1n #( + .N (3), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({3{1'b1}}), + .DRspPass ({3{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({3{4'h0}}), + .DRspDepth ({3{4'h0}}), + .ExplicitErrs (1'b0) + ) u_socket ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = + tl_i.a_address[AW-1:0] inside {[4096:7487]} ? 2'd0 : + tl_i.a_address[AW-1:0] inside {[7680:8127]} ? 2'd1 : + // Default set to register + 2'd2; + + // Override this in case of an integrity error + if (intg_err) begin + reg_steer = 2'd2; + end + end + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_upload_cmdfifo_not_empty_qs; + logic intr_state_upload_cmdfifo_not_empty_wd; + logic intr_state_upload_payload_not_empty_qs; + logic intr_state_upload_payload_not_empty_wd; + logic intr_state_upload_payload_overflow_qs; + logic intr_state_upload_payload_overflow_wd; + logic intr_state_readbuf_watermark_qs; + logic intr_state_readbuf_watermark_wd; + logic intr_state_readbuf_flip_qs; + logic intr_state_readbuf_flip_wd; + logic intr_state_tpm_header_not_empty_qs; + logic intr_state_tpm_rdfifo_cmd_end_qs; + logic intr_state_tpm_rdfifo_cmd_end_wd; + logic intr_state_tpm_rdfifo_drop_qs; + logic intr_state_tpm_rdfifo_drop_wd; + logic intr_enable_we; + logic intr_enable_upload_cmdfifo_not_empty_qs; + logic intr_enable_upload_cmdfifo_not_empty_wd; + logic intr_enable_upload_payload_not_empty_qs; + logic intr_enable_upload_payload_not_empty_wd; + logic intr_enable_upload_payload_overflow_qs; + logic intr_enable_upload_payload_overflow_wd; + logic intr_enable_readbuf_watermark_qs; + logic intr_enable_readbuf_watermark_wd; + logic intr_enable_readbuf_flip_qs; + logic intr_enable_readbuf_flip_wd; + logic intr_enable_tpm_header_not_empty_qs; + logic intr_enable_tpm_header_not_empty_wd; + logic intr_enable_tpm_rdfifo_cmd_end_qs; + logic intr_enable_tpm_rdfifo_cmd_end_wd; + logic intr_enable_tpm_rdfifo_drop_qs; + logic intr_enable_tpm_rdfifo_drop_wd; + logic intr_test_we; + logic intr_test_upload_cmdfifo_not_empty_wd; + logic intr_test_upload_payload_not_empty_wd; + logic intr_test_upload_payload_overflow_wd; + logic intr_test_readbuf_watermark_wd; + logic intr_test_readbuf_flip_wd; + logic intr_test_tpm_header_not_empty_wd; + logic intr_test_tpm_rdfifo_cmd_end_wd; + logic intr_test_tpm_rdfifo_drop_wd; + logic alert_test_we; + logic alert_test_wd; + logic control_we; + logic control_flash_status_fifo_clr_qs; + logic control_flash_status_fifo_clr_wd; + logic control_flash_read_buffer_clr_qs; + logic control_flash_read_buffer_clr_wd; + logic [1:0] control_mode_qs; + logic [1:0] control_mode_wd; + logic cfg_we; + logic cfg_tx_order_qs; + logic cfg_tx_order_wd; + logic cfg_rx_order_qs; + logic cfg_rx_order_wd; + logic cfg_mailbox_en_qs; + logic cfg_mailbox_en_wd; + logic status_re; + logic status_csb_qs; + logic status_tpm_csb_qs; + logic intercept_en_we; + logic intercept_en_status_qs; + logic intercept_en_status_wd; + logic intercept_en_jedec_qs; + logic intercept_en_jedec_wd; + logic intercept_en_sfdp_qs; + logic intercept_en_sfdp_wd; + logic intercept_en_mbx_qs; + logic intercept_en_mbx_wd; + logic addr_mode_re; + logic addr_mode_we; + logic addr_mode_addr_4b_en_qs; + logic addr_mode_addr_4b_en_wd; + logic addr_mode_pending_qs; + logic last_read_addr_re; + logic [31:0] last_read_addr_qs; + logic flash_status_re; + logic flash_status_we; + logic flash_status_busy_qs; + logic flash_status_busy_wd; + logic flash_status_wel_qs; + logic flash_status_wel_wd; + logic [21:0] flash_status_status_qs; + logic [21:0] flash_status_status_wd; + logic jedec_cc_we; + logic [7:0] jedec_cc_cc_qs; + logic [7:0] jedec_cc_cc_wd; + logic [7:0] jedec_cc_num_cc_qs; + logic [7:0] jedec_cc_num_cc_wd; + logic jedec_id_we; + logic [15:0] jedec_id_id_qs; + logic [15:0] jedec_id_id_wd; + logic [7:0] jedec_id_mf_qs; + logic [7:0] jedec_id_mf_wd; + logic read_threshold_we; + logic [9:0] read_threshold_qs; + logic [9:0] read_threshold_wd; + logic mailbox_addr_we; + logic [31:0] mailbox_addr_qs; + logic [31:0] mailbox_addr_wd; + logic [4:0] upload_status_cmdfifo_depth_qs; + logic upload_status_cmdfifo_notempty_qs; + logic [4:0] upload_status_addrfifo_depth_qs; + logic upload_status_addrfifo_notempty_qs; + logic [8:0] upload_status2_payload_depth_qs; + logic [7:0] upload_status2_payload_start_idx_qs; + logic upload_cmdfifo_re; + logic [7:0] upload_cmdfifo_data_qs; + logic upload_cmdfifo_busy_qs; + logic upload_cmdfifo_wel_qs; + logic upload_cmdfifo_addr4b_mode_qs; + logic upload_addrfifo_re; + logic [31:0] upload_addrfifo_qs; + logic cmd_filter_0_we; + logic cmd_filter_0_filter_0_qs; + logic cmd_filter_0_filter_0_wd; + logic cmd_filter_0_filter_1_qs; + logic cmd_filter_0_filter_1_wd; + logic cmd_filter_0_filter_2_qs; + logic cmd_filter_0_filter_2_wd; + logic cmd_filter_0_filter_3_qs; + logic cmd_filter_0_filter_3_wd; + logic cmd_filter_0_filter_4_qs; + logic cmd_filter_0_filter_4_wd; + logic cmd_filter_0_filter_5_qs; + logic cmd_filter_0_filter_5_wd; + logic cmd_filter_0_filter_6_qs; + logic cmd_filter_0_filter_6_wd; + logic cmd_filter_0_filter_7_qs; + logic cmd_filter_0_filter_7_wd; + logic cmd_filter_0_filter_8_qs; + logic cmd_filter_0_filter_8_wd; + logic cmd_filter_0_filter_9_qs; + logic cmd_filter_0_filter_9_wd; + logic cmd_filter_0_filter_10_qs; + logic cmd_filter_0_filter_10_wd; + logic cmd_filter_0_filter_11_qs; + logic cmd_filter_0_filter_11_wd; + logic cmd_filter_0_filter_12_qs; + logic cmd_filter_0_filter_12_wd; + logic cmd_filter_0_filter_13_qs; + logic cmd_filter_0_filter_13_wd; + logic cmd_filter_0_filter_14_qs; + logic cmd_filter_0_filter_14_wd; + logic cmd_filter_0_filter_15_qs; + logic cmd_filter_0_filter_15_wd; + logic cmd_filter_0_filter_16_qs; + logic cmd_filter_0_filter_16_wd; + logic cmd_filter_0_filter_17_qs; + logic cmd_filter_0_filter_17_wd; + logic cmd_filter_0_filter_18_qs; + logic cmd_filter_0_filter_18_wd; + logic cmd_filter_0_filter_19_qs; + logic cmd_filter_0_filter_19_wd; + logic cmd_filter_0_filter_20_qs; + logic cmd_filter_0_filter_20_wd; + logic cmd_filter_0_filter_21_qs; + logic cmd_filter_0_filter_21_wd; + logic cmd_filter_0_filter_22_qs; + logic cmd_filter_0_filter_22_wd; + logic cmd_filter_0_filter_23_qs; + logic cmd_filter_0_filter_23_wd; + logic cmd_filter_0_filter_24_qs; + logic cmd_filter_0_filter_24_wd; + logic cmd_filter_0_filter_25_qs; + logic cmd_filter_0_filter_25_wd; + logic cmd_filter_0_filter_26_qs; + logic cmd_filter_0_filter_26_wd; + logic cmd_filter_0_filter_27_qs; + logic cmd_filter_0_filter_27_wd; + logic cmd_filter_0_filter_28_qs; + logic cmd_filter_0_filter_28_wd; + logic cmd_filter_0_filter_29_qs; + logic cmd_filter_0_filter_29_wd; + logic cmd_filter_0_filter_30_qs; + logic cmd_filter_0_filter_30_wd; + logic cmd_filter_0_filter_31_qs; + logic cmd_filter_0_filter_31_wd; + logic cmd_filter_1_we; + logic cmd_filter_1_filter_32_qs; + logic cmd_filter_1_filter_32_wd; + logic cmd_filter_1_filter_33_qs; + logic cmd_filter_1_filter_33_wd; + logic cmd_filter_1_filter_34_qs; + logic cmd_filter_1_filter_34_wd; + logic cmd_filter_1_filter_35_qs; + logic cmd_filter_1_filter_35_wd; + logic cmd_filter_1_filter_36_qs; + logic cmd_filter_1_filter_36_wd; + logic cmd_filter_1_filter_37_qs; + logic cmd_filter_1_filter_37_wd; + logic cmd_filter_1_filter_38_qs; + logic cmd_filter_1_filter_38_wd; + logic cmd_filter_1_filter_39_qs; + logic cmd_filter_1_filter_39_wd; + logic cmd_filter_1_filter_40_qs; + logic cmd_filter_1_filter_40_wd; + logic cmd_filter_1_filter_41_qs; + logic cmd_filter_1_filter_41_wd; + logic cmd_filter_1_filter_42_qs; + logic cmd_filter_1_filter_42_wd; + logic cmd_filter_1_filter_43_qs; + logic cmd_filter_1_filter_43_wd; + logic cmd_filter_1_filter_44_qs; + logic cmd_filter_1_filter_44_wd; + logic cmd_filter_1_filter_45_qs; + logic cmd_filter_1_filter_45_wd; + logic cmd_filter_1_filter_46_qs; + logic cmd_filter_1_filter_46_wd; + logic cmd_filter_1_filter_47_qs; + logic cmd_filter_1_filter_47_wd; + logic cmd_filter_1_filter_48_qs; + logic cmd_filter_1_filter_48_wd; + logic cmd_filter_1_filter_49_qs; + logic cmd_filter_1_filter_49_wd; + logic cmd_filter_1_filter_50_qs; + logic cmd_filter_1_filter_50_wd; + logic cmd_filter_1_filter_51_qs; + logic cmd_filter_1_filter_51_wd; + logic cmd_filter_1_filter_52_qs; + logic cmd_filter_1_filter_52_wd; + logic cmd_filter_1_filter_53_qs; + logic cmd_filter_1_filter_53_wd; + logic cmd_filter_1_filter_54_qs; + logic cmd_filter_1_filter_54_wd; + logic cmd_filter_1_filter_55_qs; + logic cmd_filter_1_filter_55_wd; + logic cmd_filter_1_filter_56_qs; + logic cmd_filter_1_filter_56_wd; + logic cmd_filter_1_filter_57_qs; + logic cmd_filter_1_filter_57_wd; + logic cmd_filter_1_filter_58_qs; + logic cmd_filter_1_filter_58_wd; + logic cmd_filter_1_filter_59_qs; + logic cmd_filter_1_filter_59_wd; + logic cmd_filter_1_filter_60_qs; + logic cmd_filter_1_filter_60_wd; + logic cmd_filter_1_filter_61_qs; + logic cmd_filter_1_filter_61_wd; + logic cmd_filter_1_filter_62_qs; + logic cmd_filter_1_filter_62_wd; + logic cmd_filter_1_filter_63_qs; + logic cmd_filter_1_filter_63_wd; + logic cmd_filter_2_we; + logic cmd_filter_2_filter_64_qs; + logic cmd_filter_2_filter_64_wd; + logic cmd_filter_2_filter_65_qs; + logic cmd_filter_2_filter_65_wd; + logic cmd_filter_2_filter_66_qs; + logic cmd_filter_2_filter_66_wd; + logic cmd_filter_2_filter_67_qs; + logic cmd_filter_2_filter_67_wd; + logic cmd_filter_2_filter_68_qs; + logic cmd_filter_2_filter_68_wd; + logic cmd_filter_2_filter_69_qs; + logic cmd_filter_2_filter_69_wd; + logic cmd_filter_2_filter_70_qs; + logic cmd_filter_2_filter_70_wd; + logic cmd_filter_2_filter_71_qs; + logic cmd_filter_2_filter_71_wd; + logic cmd_filter_2_filter_72_qs; + logic cmd_filter_2_filter_72_wd; + logic cmd_filter_2_filter_73_qs; + logic cmd_filter_2_filter_73_wd; + logic cmd_filter_2_filter_74_qs; + logic cmd_filter_2_filter_74_wd; + logic cmd_filter_2_filter_75_qs; + logic cmd_filter_2_filter_75_wd; + logic cmd_filter_2_filter_76_qs; + logic cmd_filter_2_filter_76_wd; + logic cmd_filter_2_filter_77_qs; + logic cmd_filter_2_filter_77_wd; + logic cmd_filter_2_filter_78_qs; + logic cmd_filter_2_filter_78_wd; + logic cmd_filter_2_filter_79_qs; + logic cmd_filter_2_filter_79_wd; + logic cmd_filter_2_filter_80_qs; + logic cmd_filter_2_filter_80_wd; + logic cmd_filter_2_filter_81_qs; + logic cmd_filter_2_filter_81_wd; + logic cmd_filter_2_filter_82_qs; + logic cmd_filter_2_filter_82_wd; + logic cmd_filter_2_filter_83_qs; + logic cmd_filter_2_filter_83_wd; + logic cmd_filter_2_filter_84_qs; + logic cmd_filter_2_filter_84_wd; + logic cmd_filter_2_filter_85_qs; + logic cmd_filter_2_filter_85_wd; + logic cmd_filter_2_filter_86_qs; + logic cmd_filter_2_filter_86_wd; + logic cmd_filter_2_filter_87_qs; + logic cmd_filter_2_filter_87_wd; + logic cmd_filter_2_filter_88_qs; + logic cmd_filter_2_filter_88_wd; + logic cmd_filter_2_filter_89_qs; + logic cmd_filter_2_filter_89_wd; + logic cmd_filter_2_filter_90_qs; + logic cmd_filter_2_filter_90_wd; + logic cmd_filter_2_filter_91_qs; + logic cmd_filter_2_filter_91_wd; + logic cmd_filter_2_filter_92_qs; + logic cmd_filter_2_filter_92_wd; + logic cmd_filter_2_filter_93_qs; + logic cmd_filter_2_filter_93_wd; + logic cmd_filter_2_filter_94_qs; + logic cmd_filter_2_filter_94_wd; + logic cmd_filter_2_filter_95_qs; + logic cmd_filter_2_filter_95_wd; + logic cmd_filter_3_we; + logic cmd_filter_3_filter_96_qs; + logic cmd_filter_3_filter_96_wd; + logic cmd_filter_3_filter_97_qs; + logic cmd_filter_3_filter_97_wd; + logic cmd_filter_3_filter_98_qs; + logic cmd_filter_3_filter_98_wd; + logic cmd_filter_3_filter_99_qs; + logic cmd_filter_3_filter_99_wd; + logic cmd_filter_3_filter_100_qs; + logic cmd_filter_3_filter_100_wd; + logic cmd_filter_3_filter_101_qs; + logic cmd_filter_3_filter_101_wd; + logic cmd_filter_3_filter_102_qs; + logic cmd_filter_3_filter_102_wd; + logic cmd_filter_3_filter_103_qs; + logic cmd_filter_3_filter_103_wd; + logic cmd_filter_3_filter_104_qs; + logic cmd_filter_3_filter_104_wd; + logic cmd_filter_3_filter_105_qs; + logic cmd_filter_3_filter_105_wd; + logic cmd_filter_3_filter_106_qs; + logic cmd_filter_3_filter_106_wd; + logic cmd_filter_3_filter_107_qs; + logic cmd_filter_3_filter_107_wd; + logic cmd_filter_3_filter_108_qs; + logic cmd_filter_3_filter_108_wd; + logic cmd_filter_3_filter_109_qs; + logic cmd_filter_3_filter_109_wd; + logic cmd_filter_3_filter_110_qs; + logic cmd_filter_3_filter_110_wd; + logic cmd_filter_3_filter_111_qs; + logic cmd_filter_3_filter_111_wd; + logic cmd_filter_3_filter_112_qs; + logic cmd_filter_3_filter_112_wd; + logic cmd_filter_3_filter_113_qs; + logic cmd_filter_3_filter_113_wd; + logic cmd_filter_3_filter_114_qs; + logic cmd_filter_3_filter_114_wd; + logic cmd_filter_3_filter_115_qs; + logic cmd_filter_3_filter_115_wd; + logic cmd_filter_3_filter_116_qs; + logic cmd_filter_3_filter_116_wd; + logic cmd_filter_3_filter_117_qs; + logic cmd_filter_3_filter_117_wd; + logic cmd_filter_3_filter_118_qs; + logic cmd_filter_3_filter_118_wd; + logic cmd_filter_3_filter_119_qs; + logic cmd_filter_3_filter_119_wd; + logic cmd_filter_3_filter_120_qs; + logic cmd_filter_3_filter_120_wd; + logic cmd_filter_3_filter_121_qs; + logic cmd_filter_3_filter_121_wd; + logic cmd_filter_3_filter_122_qs; + logic cmd_filter_3_filter_122_wd; + logic cmd_filter_3_filter_123_qs; + logic cmd_filter_3_filter_123_wd; + logic cmd_filter_3_filter_124_qs; + logic cmd_filter_3_filter_124_wd; + logic cmd_filter_3_filter_125_qs; + logic cmd_filter_3_filter_125_wd; + logic cmd_filter_3_filter_126_qs; + logic cmd_filter_3_filter_126_wd; + logic cmd_filter_3_filter_127_qs; + logic cmd_filter_3_filter_127_wd; + logic cmd_filter_4_we; + logic cmd_filter_4_filter_128_qs; + logic cmd_filter_4_filter_128_wd; + logic cmd_filter_4_filter_129_qs; + logic cmd_filter_4_filter_129_wd; + logic cmd_filter_4_filter_130_qs; + logic cmd_filter_4_filter_130_wd; + logic cmd_filter_4_filter_131_qs; + logic cmd_filter_4_filter_131_wd; + logic cmd_filter_4_filter_132_qs; + logic cmd_filter_4_filter_132_wd; + logic cmd_filter_4_filter_133_qs; + logic cmd_filter_4_filter_133_wd; + logic cmd_filter_4_filter_134_qs; + logic cmd_filter_4_filter_134_wd; + logic cmd_filter_4_filter_135_qs; + logic cmd_filter_4_filter_135_wd; + logic cmd_filter_4_filter_136_qs; + logic cmd_filter_4_filter_136_wd; + logic cmd_filter_4_filter_137_qs; + logic cmd_filter_4_filter_137_wd; + logic cmd_filter_4_filter_138_qs; + logic cmd_filter_4_filter_138_wd; + logic cmd_filter_4_filter_139_qs; + logic cmd_filter_4_filter_139_wd; + logic cmd_filter_4_filter_140_qs; + logic cmd_filter_4_filter_140_wd; + logic cmd_filter_4_filter_141_qs; + logic cmd_filter_4_filter_141_wd; + logic cmd_filter_4_filter_142_qs; + logic cmd_filter_4_filter_142_wd; + logic cmd_filter_4_filter_143_qs; + logic cmd_filter_4_filter_143_wd; + logic cmd_filter_4_filter_144_qs; + logic cmd_filter_4_filter_144_wd; + logic cmd_filter_4_filter_145_qs; + logic cmd_filter_4_filter_145_wd; + logic cmd_filter_4_filter_146_qs; + logic cmd_filter_4_filter_146_wd; + logic cmd_filter_4_filter_147_qs; + logic cmd_filter_4_filter_147_wd; + logic cmd_filter_4_filter_148_qs; + logic cmd_filter_4_filter_148_wd; + logic cmd_filter_4_filter_149_qs; + logic cmd_filter_4_filter_149_wd; + logic cmd_filter_4_filter_150_qs; + logic cmd_filter_4_filter_150_wd; + logic cmd_filter_4_filter_151_qs; + logic cmd_filter_4_filter_151_wd; + logic cmd_filter_4_filter_152_qs; + logic cmd_filter_4_filter_152_wd; + logic cmd_filter_4_filter_153_qs; + logic cmd_filter_4_filter_153_wd; + logic cmd_filter_4_filter_154_qs; + logic cmd_filter_4_filter_154_wd; + logic cmd_filter_4_filter_155_qs; + logic cmd_filter_4_filter_155_wd; + logic cmd_filter_4_filter_156_qs; + logic cmd_filter_4_filter_156_wd; + logic cmd_filter_4_filter_157_qs; + logic cmd_filter_4_filter_157_wd; + logic cmd_filter_4_filter_158_qs; + logic cmd_filter_4_filter_158_wd; + logic cmd_filter_4_filter_159_qs; + logic cmd_filter_4_filter_159_wd; + logic cmd_filter_5_we; + logic cmd_filter_5_filter_160_qs; + logic cmd_filter_5_filter_160_wd; + logic cmd_filter_5_filter_161_qs; + logic cmd_filter_5_filter_161_wd; + logic cmd_filter_5_filter_162_qs; + logic cmd_filter_5_filter_162_wd; + logic cmd_filter_5_filter_163_qs; + logic cmd_filter_5_filter_163_wd; + logic cmd_filter_5_filter_164_qs; + logic cmd_filter_5_filter_164_wd; + logic cmd_filter_5_filter_165_qs; + logic cmd_filter_5_filter_165_wd; + logic cmd_filter_5_filter_166_qs; + logic cmd_filter_5_filter_166_wd; + logic cmd_filter_5_filter_167_qs; + logic cmd_filter_5_filter_167_wd; + logic cmd_filter_5_filter_168_qs; + logic cmd_filter_5_filter_168_wd; + logic cmd_filter_5_filter_169_qs; + logic cmd_filter_5_filter_169_wd; + logic cmd_filter_5_filter_170_qs; + logic cmd_filter_5_filter_170_wd; + logic cmd_filter_5_filter_171_qs; + logic cmd_filter_5_filter_171_wd; + logic cmd_filter_5_filter_172_qs; + logic cmd_filter_5_filter_172_wd; + logic cmd_filter_5_filter_173_qs; + logic cmd_filter_5_filter_173_wd; + logic cmd_filter_5_filter_174_qs; + logic cmd_filter_5_filter_174_wd; + logic cmd_filter_5_filter_175_qs; + logic cmd_filter_5_filter_175_wd; + logic cmd_filter_5_filter_176_qs; + logic cmd_filter_5_filter_176_wd; + logic cmd_filter_5_filter_177_qs; + logic cmd_filter_5_filter_177_wd; + logic cmd_filter_5_filter_178_qs; + logic cmd_filter_5_filter_178_wd; + logic cmd_filter_5_filter_179_qs; + logic cmd_filter_5_filter_179_wd; + logic cmd_filter_5_filter_180_qs; + logic cmd_filter_5_filter_180_wd; + logic cmd_filter_5_filter_181_qs; + logic cmd_filter_5_filter_181_wd; + logic cmd_filter_5_filter_182_qs; + logic cmd_filter_5_filter_182_wd; + logic cmd_filter_5_filter_183_qs; + logic cmd_filter_5_filter_183_wd; + logic cmd_filter_5_filter_184_qs; + logic cmd_filter_5_filter_184_wd; + logic cmd_filter_5_filter_185_qs; + logic cmd_filter_5_filter_185_wd; + logic cmd_filter_5_filter_186_qs; + logic cmd_filter_5_filter_186_wd; + logic cmd_filter_5_filter_187_qs; + logic cmd_filter_5_filter_187_wd; + logic cmd_filter_5_filter_188_qs; + logic cmd_filter_5_filter_188_wd; + logic cmd_filter_5_filter_189_qs; + logic cmd_filter_5_filter_189_wd; + logic cmd_filter_5_filter_190_qs; + logic cmd_filter_5_filter_190_wd; + logic cmd_filter_5_filter_191_qs; + logic cmd_filter_5_filter_191_wd; + logic cmd_filter_6_we; + logic cmd_filter_6_filter_192_qs; + logic cmd_filter_6_filter_192_wd; + logic cmd_filter_6_filter_193_qs; + logic cmd_filter_6_filter_193_wd; + logic cmd_filter_6_filter_194_qs; + logic cmd_filter_6_filter_194_wd; + logic cmd_filter_6_filter_195_qs; + logic cmd_filter_6_filter_195_wd; + logic cmd_filter_6_filter_196_qs; + logic cmd_filter_6_filter_196_wd; + logic cmd_filter_6_filter_197_qs; + logic cmd_filter_6_filter_197_wd; + logic cmd_filter_6_filter_198_qs; + logic cmd_filter_6_filter_198_wd; + logic cmd_filter_6_filter_199_qs; + logic cmd_filter_6_filter_199_wd; + logic cmd_filter_6_filter_200_qs; + logic cmd_filter_6_filter_200_wd; + logic cmd_filter_6_filter_201_qs; + logic cmd_filter_6_filter_201_wd; + logic cmd_filter_6_filter_202_qs; + logic cmd_filter_6_filter_202_wd; + logic cmd_filter_6_filter_203_qs; + logic cmd_filter_6_filter_203_wd; + logic cmd_filter_6_filter_204_qs; + logic cmd_filter_6_filter_204_wd; + logic cmd_filter_6_filter_205_qs; + logic cmd_filter_6_filter_205_wd; + logic cmd_filter_6_filter_206_qs; + logic cmd_filter_6_filter_206_wd; + logic cmd_filter_6_filter_207_qs; + logic cmd_filter_6_filter_207_wd; + logic cmd_filter_6_filter_208_qs; + logic cmd_filter_6_filter_208_wd; + logic cmd_filter_6_filter_209_qs; + logic cmd_filter_6_filter_209_wd; + logic cmd_filter_6_filter_210_qs; + logic cmd_filter_6_filter_210_wd; + logic cmd_filter_6_filter_211_qs; + logic cmd_filter_6_filter_211_wd; + logic cmd_filter_6_filter_212_qs; + logic cmd_filter_6_filter_212_wd; + logic cmd_filter_6_filter_213_qs; + logic cmd_filter_6_filter_213_wd; + logic cmd_filter_6_filter_214_qs; + logic cmd_filter_6_filter_214_wd; + logic cmd_filter_6_filter_215_qs; + logic cmd_filter_6_filter_215_wd; + logic cmd_filter_6_filter_216_qs; + logic cmd_filter_6_filter_216_wd; + logic cmd_filter_6_filter_217_qs; + logic cmd_filter_6_filter_217_wd; + logic cmd_filter_6_filter_218_qs; + logic cmd_filter_6_filter_218_wd; + logic cmd_filter_6_filter_219_qs; + logic cmd_filter_6_filter_219_wd; + logic cmd_filter_6_filter_220_qs; + logic cmd_filter_6_filter_220_wd; + logic cmd_filter_6_filter_221_qs; + logic cmd_filter_6_filter_221_wd; + logic cmd_filter_6_filter_222_qs; + logic cmd_filter_6_filter_222_wd; + logic cmd_filter_6_filter_223_qs; + logic cmd_filter_6_filter_223_wd; + logic cmd_filter_7_we; + logic cmd_filter_7_filter_224_qs; + logic cmd_filter_7_filter_224_wd; + logic cmd_filter_7_filter_225_qs; + logic cmd_filter_7_filter_225_wd; + logic cmd_filter_7_filter_226_qs; + logic cmd_filter_7_filter_226_wd; + logic cmd_filter_7_filter_227_qs; + logic cmd_filter_7_filter_227_wd; + logic cmd_filter_7_filter_228_qs; + logic cmd_filter_7_filter_228_wd; + logic cmd_filter_7_filter_229_qs; + logic cmd_filter_7_filter_229_wd; + logic cmd_filter_7_filter_230_qs; + logic cmd_filter_7_filter_230_wd; + logic cmd_filter_7_filter_231_qs; + logic cmd_filter_7_filter_231_wd; + logic cmd_filter_7_filter_232_qs; + logic cmd_filter_7_filter_232_wd; + logic cmd_filter_7_filter_233_qs; + logic cmd_filter_7_filter_233_wd; + logic cmd_filter_7_filter_234_qs; + logic cmd_filter_7_filter_234_wd; + logic cmd_filter_7_filter_235_qs; + logic cmd_filter_7_filter_235_wd; + logic cmd_filter_7_filter_236_qs; + logic cmd_filter_7_filter_236_wd; + logic cmd_filter_7_filter_237_qs; + logic cmd_filter_7_filter_237_wd; + logic cmd_filter_7_filter_238_qs; + logic cmd_filter_7_filter_238_wd; + logic cmd_filter_7_filter_239_qs; + logic cmd_filter_7_filter_239_wd; + logic cmd_filter_7_filter_240_qs; + logic cmd_filter_7_filter_240_wd; + logic cmd_filter_7_filter_241_qs; + logic cmd_filter_7_filter_241_wd; + logic cmd_filter_7_filter_242_qs; + logic cmd_filter_7_filter_242_wd; + logic cmd_filter_7_filter_243_qs; + logic cmd_filter_7_filter_243_wd; + logic cmd_filter_7_filter_244_qs; + logic cmd_filter_7_filter_244_wd; + logic cmd_filter_7_filter_245_qs; + logic cmd_filter_7_filter_245_wd; + logic cmd_filter_7_filter_246_qs; + logic cmd_filter_7_filter_246_wd; + logic cmd_filter_7_filter_247_qs; + logic cmd_filter_7_filter_247_wd; + logic cmd_filter_7_filter_248_qs; + logic cmd_filter_7_filter_248_wd; + logic cmd_filter_7_filter_249_qs; + logic cmd_filter_7_filter_249_wd; + logic cmd_filter_7_filter_250_qs; + logic cmd_filter_7_filter_250_wd; + logic cmd_filter_7_filter_251_qs; + logic cmd_filter_7_filter_251_wd; + logic cmd_filter_7_filter_252_qs; + logic cmd_filter_7_filter_252_wd; + logic cmd_filter_7_filter_253_qs; + logic cmd_filter_7_filter_253_wd; + logic cmd_filter_7_filter_254_qs; + logic cmd_filter_7_filter_254_wd; + logic cmd_filter_7_filter_255_qs; + logic cmd_filter_7_filter_255_wd; + logic addr_swap_mask_we; + logic [31:0] addr_swap_mask_qs; + logic [31:0] addr_swap_mask_wd; + logic addr_swap_data_we; + logic [31:0] addr_swap_data_qs; + logic [31:0] addr_swap_data_wd; + logic payload_swap_mask_we; + logic [31:0] payload_swap_mask_qs; + logic [31:0] payload_swap_mask_wd; + logic payload_swap_data_we; + logic [31:0] payload_swap_data_qs; + logic [31:0] payload_swap_data_wd; + logic cmd_info_0_we; + logic [7:0] cmd_info_0_opcode_0_qs; + logic [7:0] cmd_info_0_opcode_0_wd; + logic [1:0] cmd_info_0_addr_mode_0_qs; + logic [1:0] cmd_info_0_addr_mode_0_wd; + logic cmd_info_0_addr_swap_en_0_qs; + logic cmd_info_0_addr_swap_en_0_wd; + logic cmd_info_0_mbyte_en_0_qs; + logic cmd_info_0_mbyte_en_0_wd; + logic [2:0] cmd_info_0_dummy_size_0_qs; + logic [2:0] cmd_info_0_dummy_size_0_wd; + logic cmd_info_0_dummy_en_0_qs; + logic cmd_info_0_dummy_en_0_wd; + logic [3:0] cmd_info_0_payload_en_0_qs; + logic [3:0] cmd_info_0_payload_en_0_wd; + logic cmd_info_0_payload_dir_0_qs; + logic cmd_info_0_payload_dir_0_wd; + logic cmd_info_0_payload_swap_en_0_qs; + logic cmd_info_0_payload_swap_en_0_wd; + logic [1:0] cmd_info_0_read_pipeline_mode_0_qs; + logic [1:0] cmd_info_0_read_pipeline_mode_0_wd; + logic cmd_info_0_upload_0_qs; + logic cmd_info_0_upload_0_wd; + logic cmd_info_0_busy_0_qs; + logic cmd_info_0_busy_0_wd; + logic cmd_info_0_valid_0_qs; + logic cmd_info_0_valid_0_wd; + logic cmd_info_1_we; + logic [7:0] cmd_info_1_opcode_1_qs; + logic [7:0] cmd_info_1_opcode_1_wd; + logic [1:0] cmd_info_1_addr_mode_1_qs; + logic [1:0] cmd_info_1_addr_mode_1_wd; + logic cmd_info_1_addr_swap_en_1_qs; + logic cmd_info_1_addr_swap_en_1_wd; + logic cmd_info_1_mbyte_en_1_qs; + logic cmd_info_1_mbyte_en_1_wd; + logic [2:0] cmd_info_1_dummy_size_1_qs; + logic [2:0] cmd_info_1_dummy_size_1_wd; + logic cmd_info_1_dummy_en_1_qs; + logic cmd_info_1_dummy_en_1_wd; + logic [3:0] cmd_info_1_payload_en_1_qs; + logic [3:0] cmd_info_1_payload_en_1_wd; + logic cmd_info_1_payload_dir_1_qs; + logic cmd_info_1_payload_dir_1_wd; + logic cmd_info_1_payload_swap_en_1_qs; + logic cmd_info_1_payload_swap_en_1_wd; + logic [1:0] cmd_info_1_read_pipeline_mode_1_qs; + logic [1:0] cmd_info_1_read_pipeline_mode_1_wd; + logic cmd_info_1_upload_1_qs; + logic cmd_info_1_upload_1_wd; + logic cmd_info_1_busy_1_qs; + logic cmd_info_1_busy_1_wd; + logic cmd_info_1_valid_1_qs; + logic cmd_info_1_valid_1_wd; + logic cmd_info_2_we; + logic [7:0] cmd_info_2_opcode_2_qs; + logic [7:0] cmd_info_2_opcode_2_wd; + logic [1:0] cmd_info_2_addr_mode_2_qs; + logic [1:0] cmd_info_2_addr_mode_2_wd; + logic cmd_info_2_addr_swap_en_2_qs; + logic cmd_info_2_addr_swap_en_2_wd; + logic cmd_info_2_mbyte_en_2_qs; + logic cmd_info_2_mbyte_en_2_wd; + logic [2:0] cmd_info_2_dummy_size_2_qs; + logic [2:0] cmd_info_2_dummy_size_2_wd; + logic cmd_info_2_dummy_en_2_qs; + logic cmd_info_2_dummy_en_2_wd; + logic [3:0] cmd_info_2_payload_en_2_qs; + logic [3:0] cmd_info_2_payload_en_2_wd; + logic cmd_info_2_payload_dir_2_qs; + logic cmd_info_2_payload_dir_2_wd; + logic cmd_info_2_payload_swap_en_2_qs; + logic cmd_info_2_payload_swap_en_2_wd; + logic [1:0] cmd_info_2_read_pipeline_mode_2_qs; + logic [1:0] cmd_info_2_read_pipeline_mode_2_wd; + logic cmd_info_2_upload_2_qs; + logic cmd_info_2_upload_2_wd; + logic cmd_info_2_busy_2_qs; + logic cmd_info_2_busy_2_wd; + logic cmd_info_2_valid_2_qs; + logic cmd_info_2_valid_2_wd; + logic cmd_info_3_we; + logic [7:0] cmd_info_3_opcode_3_qs; + logic [7:0] cmd_info_3_opcode_3_wd; + logic [1:0] cmd_info_3_addr_mode_3_qs; + logic [1:0] cmd_info_3_addr_mode_3_wd; + logic cmd_info_3_addr_swap_en_3_qs; + logic cmd_info_3_addr_swap_en_3_wd; + logic cmd_info_3_mbyte_en_3_qs; + logic cmd_info_3_mbyte_en_3_wd; + logic [2:0] cmd_info_3_dummy_size_3_qs; + logic [2:0] cmd_info_3_dummy_size_3_wd; + logic cmd_info_3_dummy_en_3_qs; + logic cmd_info_3_dummy_en_3_wd; + logic [3:0] cmd_info_3_payload_en_3_qs; + logic [3:0] cmd_info_3_payload_en_3_wd; + logic cmd_info_3_payload_dir_3_qs; + logic cmd_info_3_payload_dir_3_wd; + logic cmd_info_3_payload_swap_en_3_qs; + logic cmd_info_3_payload_swap_en_3_wd; + logic [1:0] cmd_info_3_read_pipeline_mode_3_qs; + logic [1:0] cmd_info_3_read_pipeline_mode_3_wd; + logic cmd_info_3_upload_3_qs; + logic cmd_info_3_upload_3_wd; + logic cmd_info_3_busy_3_qs; + logic cmd_info_3_busy_3_wd; + logic cmd_info_3_valid_3_qs; + logic cmd_info_3_valid_3_wd; + logic cmd_info_4_we; + logic [7:0] cmd_info_4_opcode_4_qs; + logic [7:0] cmd_info_4_opcode_4_wd; + logic [1:0] cmd_info_4_addr_mode_4_qs; + logic [1:0] cmd_info_4_addr_mode_4_wd; + logic cmd_info_4_addr_swap_en_4_qs; + logic cmd_info_4_addr_swap_en_4_wd; + logic cmd_info_4_mbyte_en_4_qs; + logic cmd_info_4_mbyte_en_4_wd; + logic [2:0] cmd_info_4_dummy_size_4_qs; + logic [2:0] cmd_info_4_dummy_size_4_wd; + logic cmd_info_4_dummy_en_4_qs; + logic cmd_info_4_dummy_en_4_wd; + logic [3:0] cmd_info_4_payload_en_4_qs; + logic [3:0] cmd_info_4_payload_en_4_wd; + logic cmd_info_4_payload_dir_4_qs; + logic cmd_info_4_payload_dir_4_wd; + logic cmd_info_4_payload_swap_en_4_qs; + logic cmd_info_4_payload_swap_en_4_wd; + logic [1:0] cmd_info_4_read_pipeline_mode_4_qs; + logic [1:0] cmd_info_4_read_pipeline_mode_4_wd; + logic cmd_info_4_upload_4_qs; + logic cmd_info_4_upload_4_wd; + logic cmd_info_4_busy_4_qs; + logic cmd_info_4_busy_4_wd; + logic cmd_info_4_valid_4_qs; + logic cmd_info_4_valid_4_wd; + logic cmd_info_5_we; + logic [7:0] cmd_info_5_opcode_5_qs; + logic [7:0] cmd_info_5_opcode_5_wd; + logic [1:0] cmd_info_5_addr_mode_5_qs; + logic [1:0] cmd_info_5_addr_mode_5_wd; + logic cmd_info_5_addr_swap_en_5_qs; + logic cmd_info_5_addr_swap_en_5_wd; + logic cmd_info_5_mbyte_en_5_qs; + logic cmd_info_5_mbyte_en_5_wd; + logic [2:0] cmd_info_5_dummy_size_5_qs; + logic [2:0] cmd_info_5_dummy_size_5_wd; + logic cmd_info_5_dummy_en_5_qs; + logic cmd_info_5_dummy_en_5_wd; + logic [3:0] cmd_info_5_payload_en_5_qs; + logic [3:0] cmd_info_5_payload_en_5_wd; + logic cmd_info_5_payload_dir_5_qs; + logic cmd_info_5_payload_dir_5_wd; + logic cmd_info_5_payload_swap_en_5_qs; + logic cmd_info_5_payload_swap_en_5_wd; + logic [1:0] cmd_info_5_read_pipeline_mode_5_qs; + logic [1:0] cmd_info_5_read_pipeline_mode_5_wd; + logic cmd_info_5_upload_5_qs; + logic cmd_info_5_upload_5_wd; + logic cmd_info_5_busy_5_qs; + logic cmd_info_5_busy_5_wd; + logic cmd_info_5_valid_5_qs; + logic cmd_info_5_valid_5_wd; + logic cmd_info_6_we; + logic [7:0] cmd_info_6_opcode_6_qs; + logic [7:0] cmd_info_6_opcode_6_wd; + logic [1:0] cmd_info_6_addr_mode_6_qs; + logic [1:0] cmd_info_6_addr_mode_6_wd; + logic cmd_info_6_addr_swap_en_6_qs; + logic cmd_info_6_addr_swap_en_6_wd; + logic cmd_info_6_mbyte_en_6_qs; + logic cmd_info_6_mbyte_en_6_wd; + logic [2:0] cmd_info_6_dummy_size_6_qs; + logic [2:0] cmd_info_6_dummy_size_6_wd; + logic cmd_info_6_dummy_en_6_qs; + logic cmd_info_6_dummy_en_6_wd; + logic [3:0] cmd_info_6_payload_en_6_qs; + logic [3:0] cmd_info_6_payload_en_6_wd; + logic cmd_info_6_payload_dir_6_qs; + logic cmd_info_6_payload_dir_6_wd; + logic cmd_info_6_payload_swap_en_6_qs; + logic cmd_info_6_payload_swap_en_6_wd; + logic [1:0] cmd_info_6_read_pipeline_mode_6_qs; + logic [1:0] cmd_info_6_read_pipeline_mode_6_wd; + logic cmd_info_6_upload_6_qs; + logic cmd_info_6_upload_6_wd; + logic cmd_info_6_busy_6_qs; + logic cmd_info_6_busy_6_wd; + logic cmd_info_6_valid_6_qs; + logic cmd_info_6_valid_6_wd; + logic cmd_info_7_we; + logic [7:0] cmd_info_7_opcode_7_qs; + logic [7:0] cmd_info_7_opcode_7_wd; + logic [1:0] cmd_info_7_addr_mode_7_qs; + logic [1:0] cmd_info_7_addr_mode_7_wd; + logic cmd_info_7_addr_swap_en_7_qs; + logic cmd_info_7_addr_swap_en_7_wd; + logic cmd_info_7_mbyte_en_7_qs; + logic cmd_info_7_mbyte_en_7_wd; + logic [2:0] cmd_info_7_dummy_size_7_qs; + logic [2:0] cmd_info_7_dummy_size_7_wd; + logic cmd_info_7_dummy_en_7_qs; + logic cmd_info_7_dummy_en_7_wd; + logic [3:0] cmd_info_7_payload_en_7_qs; + logic [3:0] cmd_info_7_payload_en_7_wd; + logic cmd_info_7_payload_dir_7_qs; + logic cmd_info_7_payload_dir_7_wd; + logic cmd_info_7_payload_swap_en_7_qs; + logic cmd_info_7_payload_swap_en_7_wd; + logic [1:0] cmd_info_7_read_pipeline_mode_7_qs; + logic [1:0] cmd_info_7_read_pipeline_mode_7_wd; + logic cmd_info_7_upload_7_qs; + logic cmd_info_7_upload_7_wd; + logic cmd_info_7_busy_7_qs; + logic cmd_info_7_busy_7_wd; + logic cmd_info_7_valid_7_qs; + logic cmd_info_7_valid_7_wd; + logic cmd_info_8_we; + logic [7:0] cmd_info_8_opcode_8_qs; + logic [7:0] cmd_info_8_opcode_8_wd; + logic [1:0] cmd_info_8_addr_mode_8_qs; + logic [1:0] cmd_info_8_addr_mode_8_wd; + logic cmd_info_8_addr_swap_en_8_qs; + logic cmd_info_8_addr_swap_en_8_wd; + logic cmd_info_8_mbyte_en_8_qs; + logic cmd_info_8_mbyte_en_8_wd; + logic [2:0] cmd_info_8_dummy_size_8_qs; + logic [2:0] cmd_info_8_dummy_size_8_wd; + logic cmd_info_8_dummy_en_8_qs; + logic cmd_info_8_dummy_en_8_wd; + logic [3:0] cmd_info_8_payload_en_8_qs; + logic [3:0] cmd_info_8_payload_en_8_wd; + logic cmd_info_8_payload_dir_8_qs; + logic cmd_info_8_payload_dir_8_wd; + logic cmd_info_8_payload_swap_en_8_qs; + logic cmd_info_8_payload_swap_en_8_wd; + logic [1:0] cmd_info_8_read_pipeline_mode_8_qs; + logic [1:0] cmd_info_8_read_pipeline_mode_8_wd; + logic cmd_info_8_upload_8_qs; + logic cmd_info_8_upload_8_wd; + logic cmd_info_8_busy_8_qs; + logic cmd_info_8_busy_8_wd; + logic cmd_info_8_valid_8_qs; + logic cmd_info_8_valid_8_wd; + logic cmd_info_9_we; + logic [7:0] cmd_info_9_opcode_9_qs; + logic [7:0] cmd_info_9_opcode_9_wd; + logic [1:0] cmd_info_9_addr_mode_9_qs; + logic [1:0] cmd_info_9_addr_mode_9_wd; + logic cmd_info_9_addr_swap_en_9_qs; + logic cmd_info_9_addr_swap_en_9_wd; + logic cmd_info_9_mbyte_en_9_qs; + logic cmd_info_9_mbyte_en_9_wd; + logic [2:0] cmd_info_9_dummy_size_9_qs; + logic [2:0] cmd_info_9_dummy_size_9_wd; + logic cmd_info_9_dummy_en_9_qs; + logic cmd_info_9_dummy_en_9_wd; + logic [3:0] cmd_info_9_payload_en_9_qs; + logic [3:0] cmd_info_9_payload_en_9_wd; + logic cmd_info_9_payload_dir_9_qs; + logic cmd_info_9_payload_dir_9_wd; + logic cmd_info_9_payload_swap_en_9_qs; + logic cmd_info_9_payload_swap_en_9_wd; + logic [1:0] cmd_info_9_read_pipeline_mode_9_qs; + logic [1:0] cmd_info_9_read_pipeline_mode_9_wd; + logic cmd_info_9_upload_9_qs; + logic cmd_info_9_upload_9_wd; + logic cmd_info_9_busy_9_qs; + logic cmd_info_9_busy_9_wd; + logic cmd_info_9_valid_9_qs; + logic cmd_info_9_valid_9_wd; + logic cmd_info_10_we; + logic [7:0] cmd_info_10_opcode_10_qs; + logic [7:0] cmd_info_10_opcode_10_wd; + logic [1:0] cmd_info_10_addr_mode_10_qs; + logic [1:0] cmd_info_10_addr_mode_10_wd; + logic cmd_info_10_addr_swap_en_10_qs; + logic cmd_info_10_addr_swap_en_10_wd; + logic cmd_info_10_mbyte_en_10_qs; + logic cmd_info_10_mbyte_en_10_wd; + logic [2:0] cmd_info_10_dummy_size_10_qs; + logic [2:0] cmd_info_10_dummy_size_10_wd; + logic cmd_info_10_dummy_en_10_qs; + logic cmd_info_10_dummy_en_10_wd; + logic [3:0] cmd_info_10_payload_en_10_qs; + logic [3:0] cmd_info_10_payload_en_10_wd; + logic cmd_info_10_payload_dir_10_qs; + logic cmd_info_10_payload_dir_10_wd; + logic cmd_info_10_payload_swap_en_10_qs; + logic cmd_info_10_payload_swap_en_10_wd; + logic [1:0] cmd_info_10_read_pipeline_mode_10_qs; + logic [1:0] cmd_info_10_read_pipeline_mode_10_wd; + logic cmd_info_10_upload_10_qs; + logic cmd_info_10_upload_10_wd; + logic cmd_info_10_busy_10_qs; + logic cmd_info_10_busy_10_wd; + logic cmd_info_10_valid_10_qs; + logic cmd_info_10_valid_10_wd; + logic cmd_info_11_we; + logic [7:0] cmd_info_11_opcode_11_qs; + logic [7:0] cmd_info_11_opcode_11_wd; + logic [1:0] cmd_info_11_addr_mode_11_qs; + logic [1:0] cmd_info_11_addr_mode_11_wd; + logic cmd_info_11_addr_swap_en_11_qs; + logic cmd_info_11_addr_swap_en_11_wd; + logic cmd_info_11_mbyte_en_11_qs; + logic cmd_info_11_mbyte_en_11_wd; + logic [2:0] cmd_info_11_dummy_size_11_qs; + logic [2:0] cmd_info_11_dummy_size_11_wd; + logic cmd_info_11_dummy_en_11_qs; + logic cmd_info_11_dummy_en_11_wd; + logic [3:0] cmd_info_11_payload_en_11_qs; + logic [3:0] cmd_info_11_payload_en_11_wd; + logic cmd_info_11_payload_dir_11_qs; + logic cmd_info_11_payload_dir_11_wd; + logic cmd_info_11_payload_swap_en_11_qs; + logic cmd_info_11_payload_swap_en_11_wd; + logic [1:0] cmd_info_11_read_pipeline_mode_11_qs; + logic [1:0] cmd_info_11_read_pipeline_mode_11_wd; + logic cmd_info_11_upload_11_qs; + logic cmd_info_11_upload_11_wd; + logic cmd_info_11_busy_11_qs; + logic cmd_info_11_busy_11_wd; + logic cmd_info_11_valid_11_qs; + logic cmd_info_11_valid_11_wd; + logic cmd_info_12_we; + logic [7:0] cmd_info_12_opcode_12_qs; + logic [7:0] cmd_info_12_opcode_12_wd; + logic [1:0] cmd_info_12_addr_mode_12_qs; + logic [1:0] cmd_info_12_addr_mode_12_wd; + logic cmd_info_12_addr_swap_en_12_qs; + logic cmd_info_12_addr_swap_en_12_wd; + logic cmd_info_12_mbyte_en_12_qs; + logic cmd_info_12_mbyte_en_12_wd; + logic [2:0] cmd_info_12_dummy_size_12_qs; + logic [2:0] cmd_info_12_dummy_size_12_wd; + logic cmd_info_12_dummy_en_12_qs; + logic cmd_info_12_dummy_en_12_wd; + logic [3:0] cmd_info_12_payload_en_12_qs; + logic [3:0] cmd_info_12_payload_en_12_wd; + logic cmd_info_12_payload_dir_12_qs; + logic cmd_info_12_payload_dir_12_wd; + logic cmd_info_12_payload_swap_en_12_qs; + logic cmd_info_12_payload_swap_en_12_wd; + logic [1:0] cmd_info_12_read_pipeline_mode_12_qs; + logic [1:0] cmd_info_12_read_pipeline_mode_12_wd; + logic cmd_info_12_upload_12_qs; + logic cmd_info_12_upload_12_wd; + logic cmd_info_12_busy_12_qs; + logic cmd_info_12_busy_12_wd; + logic cmd_info_12_valid_12_qs; + logic cmd_info_12_valid_12_wd; + logic cmd_info_13_we; + logic [7:0] cmd_info_13_opcode_13_qs; + logic [7:0] cmd_info_13_opcode_13_wd; + logic [1:0] cmd_info_13_addr_mode_13_qs; + logic [1:0] cmd_info_13_addr_mode_13_wd; + logic cmd_info_13_addr_swap_en_13_qs; + logic cmd_info_13_addr_swap_en_13_wd; + logic cmd_info_13_mbyte_en_13_qs; + logic cmd_info_13_mbyte_en_13_wd; + logic [2:0] cmd_info_13_dummy_size_13_qs; + logic [2:0] cmd_info_13_dummy_size_13_wd; + logic cmd_info_13_dummy_en_13_qs; + logic cmd_info_13_dummy_en_13_wd; + logic [3:0] cmd_info_13_payload_en_13_qs; + logic [3:0] cmd_info_13_payload_en_13_wd; + logic cmd_info_13_payload_dir_13_qs; + logic cmd_info_13_payload_dir_13_wd; + logic cmd_info_13_payload_swap_en_13_qs; + logic cmd_info_13_payload_swap_en_13_wd; + logic [1:0] cmd_info_13_read_pipeline_mode_13_qs; + logic [1:0] cmd_info_13_read_pipeline_mode_13_wd; + logic cmd_info_13_upload_13_qs; + logic cmd_info_13_upload_13_wd; + logic cmd_info_13_busy_13_qs; + logic cmd_info_13_busy_13_wd; + logic cmd_info_13_valid_13_qs; + logic cmd_info_13_valid_13_wd; + logic cmd_info_14_we; + logic [7:0] cmd_info_14_opcode_14_qs; + logic [7:0] cmd_info_14_opcode_14_wd; + logic [1:0] cmd_info_14_addr_mode_14_qs; + logic [1:0] cmd_info_14_addr_mode_14_wd; + logic cmd_info_14_addr_swap_en_14_qs; + logic cmd_info_14_addr_swap_en_14_wd; + logic cmd_info_14_mbyte_en_14_qs; + logic cmd_info_14_mbyte_en_14_wd; + logic [2:0] cmd_info_14_dummy_size_14_qs; + logic [2:0] cmd_info_14_dummy_size_14_wd; + logic cmd_info_14_dummy_en_14_qs; + logic cmd_info_14_dummy_en_14_wd; + logic [3:0] cmd_info_14_payload_en_14_qs; + logic [3:0] cmd_info_14_payload_en_14_wd; + logic cmd_info_14_payload_dir_14_qs; + logic cmd_info_14_payload_dir_14_wd; + logic cmd_info_14_payload_swap_en_14_qs; + logic cmd_info_14_payload_swap_en_14_wd; + logic [1:0] cmd_info_14_read_pipeline_mode_14_qs; + logic [1:0] cmd_info_14_read_pipeline_mode_14_wd; + logic cmd_info_14_upload_14_qs; + logic cmd_info_14_upload_14_wd; + logic cmd_info_14_busy_14_qs; + logic cmd_info_14_busy_14_wd; + logic cmd_info_14_valid_14_qs; + logic cmd_info_14_valid_14_wd; + logic cmd_info_15_we; + logic [7:0] cmd_info_15_opcode_15_qs; + logic [7:0] cmd_info_15_opcode_15_wd; + logic [1:0] cmd_info_15_addr_mode_15_qs; + logic [1:0] cmd_info_15_addr_mode_15_wd; + logic cmd_info_15_addr_swap_en_15_qs; + logic cmd_info_15_addr_swap_en_15_wd; + logic cmd_info_15_mbyte_en_15_qs; + logic cmd_info_15_mbyte_en_15_wd; + logic [2:0] cmd_info_15_dummy_size_15_qs; + logic [2:0] cmd_info_15_dummy_size_15_wd; + logic cmd_info_15_dummy_en_15_qs; + logic cmd_info_15_dummy_en_15_wd; + logic [3:0] cmd_info_15_payload_en_15_qs; + logic [3:0] cmd_info_15_payload_en_15_wd; + logic cmd_info_15_payload_dir_15_qs; + logic cmd_info_15_payload_dir_15_wd; + logic cmd_info_15_payload_swap_en_15_qs; + logic cmd_info_15_payload_swap_en_15_wd; + logic [1:0] cmd_info_15_read_pipeline_mode_15_qs; + logic [1:0] cmd_info_15_read_pipeline_mode_15_wd; + logic cmd_info_15_upload_15_qs; + logic cmd_info_15_upload_15_wd; + logic cmd_info_15_busy_15_qs; + logic cmd_info_15_busy_15_wd; + logic cmd_info_15_valid_15_qs; + logic cmd_info_15_valid_15_wd; + logic cmd_info_16_we; + logic [7:0] cmd_info_16_opcode_16_qs; + logic [7:0] cmd_info_16_opcode_16_wd; + logic [1:0] cmd_info_16_addr_mode_16_qs; + logic [1:0] cmd_info_16_addr_mode_16_wd; + logic cmd_info_16_addr_swap_en_16_qs; + logic cmd_info_16_addr_swap_en_16_wd; + logic cmd_info_16_mbyte_en_16_qs; + logic cmd_info_16_mbyte_en_16_wd; + logic [2:0] cmd_info_16_dummy_size_16_qs; + logic [2:0] cmd_info_16_dummy_size_16_wd; + logic cmd_info_16_dummy_en_16_qs; + logic cmd_info_16_dummy_en_16_wd; + logic [3:0] cmd_info_16_payload_en_16_qs; + logic [3:0] cmd_info_16_payload_en_16_wd; + logic cmd_info_16_payload_dir_16_qs; + logic cmd_info_16_payload_dir_16_wd; + logic cmd_info_16_payload_swap_en_16_qs; + logic cmd_info_16_payload_swap_en_16_wd; + logic [1:0] cmd_info_16_read_pipeline_mode_16_qs; + logic [1:0] cmd_info_16_read_pipeline_mode_16_wd; + logic cmd_info_16_upload_16_qs; + logic cmd_info_16_upload_16_wd; + logic cmd_info_16_busy_16_qs; + logic cmd_info_16_busy_16_wd; + logic cmd_info_16_valid_16_qs; + logic cmd_info_16_valid_16_wd; + logic cmd_info_17_we; + logic [7:0] cmd_info_17_opcode_17_qs; + logic [7:0] cmd_info_17_opcode_17_wd; + logic [1:0] cmd_info_17_addr_mode_17_qs; + logic [1:0] cmd_info_17_addr_mode_17_wd; + logic cmd_info_17_addr_swap_en_17_qs; + logic cmd_info_17_addr_swap_en_17_wd; + logic cmd_info_17_mbyte_en_17_qs; + logic cmd_info_17_mbyte_en_17_wd; + logic [2:0] cmd_info_17_dummy_size_17_qs; + logic [2:0] cmd_info_17_dummy_size_17_wd; + logic cmd_info_17_dummy_en_17_qs; + logic cmd_info_17_dummy_en_17_wd; + logic [3:0] cmd_info_17_payload_en_17_qs; + logic [3:0] cmd_info_17_payload_en_17_wd; + logic cmd_info_17_payload_dir_17_qs; + logic cmd_info_17_payload_dir_17_wd; + logic cmd_info_17_payload_swap_en_17_qs; + logic cmd_info_17_payload_swap_en_17_wd; + logic [1:0] cmd_info_17_read_pipeline_mode_17_qs; + logic [1:0] cmd_info_17_read_pipeline_mode_17_wd; + logic cmd_info_17_upload_17_qs; + logic cmd_info_17_upload_17_wd; + logic cmd_info_17_busy_17_qs; + logic cmd_info_17_busy_17_wd; + logic cmd_info_17_valid_17_qs; + logic cmd_info_17_valid_17_wd; + logic cmd_info_18_we; + logic [7:0] cmd_info_18_opcode_18_qs; + logic [7:0] cmd_info_18_opcode_18_wd; + logic [1:0] cmd_info_18_addr_mode_18_qs; + logic [1:0] cmd_info_18_addr_mode_18_wd; + logic cmd_info_18_addr_swap_en_18_qs; + logic cmd_info_18_addr_swap_en_18_wd; + logic cmd_info_18_mbyte_en_18_qs; + logic cmd_info_18_mbyte_en_18_wd; + logic [2:0] cmd_info_18_dummy_size_18_qs; + logic [2:0] cmd_info_18_dummy_size_18_wd; + logic cmd_info_18_dummy_en_18_qs; + logic cmd_info_18_dummy_en_18_wd; + logic [3:0] cmd_info_18_payload_en_18_qs; + logic [3:0] cmd_info_18_payload_en_18_wd; + logic cmd_info_18_payload_dir_18_qs; + logic cmd_info_18_payload_dir_18_wd; + logic cmd_info_18_payload_swap_en_18_qs; + logic cmd_info_18_payload_swap_en_18_wd; + logic [1:0] cmd_info_18_read_pipeline_mode_18_qs; + logic [1:0] cmd_info_18_read_pipeline_mode_18_wd; + logic cmd_info_18_upload_18_qs; + logic cmd_info_18_upload_18_wd; + logic cmd_info_18_busy_18_qs; + logic cmd_info_18_busy_18_wd; + logic cmd_info_18_valid_18_qs; + logic cmd_info_18_valid_18_wd; + logic cmd_info_19_we; + logic [7:0] cmd_info_19_opcode_19_qs; + logic [7:0] cmd_info_19_opcode_19_wd; + logic [1:0] cmd_info_19_addr_mode_19_qs; + logic [1:0] cmd_info_19_addr_mode_19_wd; + logic cmd_info_19_addr_swap_en_19_qs; + logic cmd_info_19_addr_swap_en_19_wd; + logic cmd_info_19_mbyte_en_19_qs; + logic cmd_info_19_mbyte_en_19_wd; + logic [2:0] cmd_info_19_dummy_size_19_qs; + logic [2:0] cmd_info_19_dummy_size_19_wd; + logic cmd_info_19_dummy_en_19_qs; + logic cmd_info_19_dummy_en_19_wd; + logic [3:0] cmd_info_19_payload_en_19_qs; + logic [3:0] cmd_info_19_payload_en_19_wd; + logic cmd_info_19_payload_dir_19_qs; + logic cmd_info_19_payload_dir_19_wd; + logic cmd_info_19_payload_swap_en_19_qs; + logic cmd_info_19_payload_swap_en_19_wd; + logic [1:0] cmd_info_19_read_pipeline_mode_19_qs; + logic [1:0] cmd_info_19_read_pipeline_mode_19_wd; + logic cmd_info_19_upload_19_qs; + logic cmd_info_19_upload_19_wd; + logic cmd_info_19_busy_19_qs; + logic cmd_info_19_busy_19_wd; + logic cmd_info_19_valid_19_qs; + logic cmd_info_19_valid_19_wd; + logic cmd_info_20_we; + logic [7:0] cmd_info_20_opcode_20_qs; + logic [7:0] cmd_info_20_opcode_20_wd; + logic [1:0] cmd_info_20_addr_mode_20_qs; + logic [1:0] cmd_info_20_addr_mode_20_wd; + logic cmd_info_20_addr_swap_en_20_qs; + logic cmd_info_20_addr_swap_en_20_wd; + logic cmd_info_20_mbyte_en_20_qs; + logic cmd_info_20_mbyte_en_20_wd; + logic [2:0] cmd_info_20_dummy_size_20_qs; + logic [2:0] cmd_info_20_dummy_size_20_wd; + logic cmd_info_20_dummy_en_20_qs; + logic cmd_info_20_dummy_en_20_wd; + logic [3:0] cmd_info_20_payload_en_20_qs; + logic [3:0] cmd_info_20_payload_en_20_wd; + logic cmd_info_20_payload_dir_20_qs; + logic cmd_info_20_payload_dir_20_wd; + logic cmd_info_20_payload_swap_en_20_qs; + logic cmd_info_20_payload_swap_en_20_wd; + logic [1:0] cmd_info_20_read_pipeline_mode_20_qs; + logic [1:0] cmd_info_20_read_pipeline_mode_20_wd; + logic cmd_info_20_upload_20_qs; + logic cmd_info_20_upload_20_wd; + logic cmd_info_20_busy_20_qs; + logic cmd_info_20_busy_20_wd; + logic cmd_info_20_valid_20_qs; + logic cmd_info_20_valid_20_wd; + logic cmd_info_21_we; + logic [7:0] cmd_info_21_opcode_21_qs; + logic [7:0] cmd_info_21_opcode_21_wd; + logic [1:0] cmd_info_21_addr_mode_21_qs; + logic [1:0] cmd_info_21_addr_mode_21_wd; + logic cmd_info_21_addr_swap_en_21_qs; + logic cmd_info_21_addr_swap_en_21_wd; + logic cmd_info_21_mbyte_en_21_qs; + logic cmd_info_21_mbyte_en_21_wd; + logic [2:0] cmd_info_21_dummy_size_21_qs; + logic [2:0] cmd_info_21_dummy_size_21_wd; + logic cmd_info_21_dummy_en_21_qs; + logic cmd_info_21_dummy_en_21_wd; + logic [3:0] cmd_info_21_payload_en_21_qs; + logic [3:0] cmd_info_21_payload_en_21_wd; + logic cmd_info_21_payload_dir_21_qs; + logic cmd_info_21_payload_dir_21_wd; + logic cmd_info_21_payload_swap_en_21_qs; + logic cmd_info_21_payload_swap_en_21_wd; + logic [1:0] cmd_info_21_read_pipeline_mode_21_qs; + logic [1:0] cmd_info_21_read_pipeline_mode_21_wd; + logic cmd_info_21_upload_21_qs; + logic cmd_info_21_upload_21_wd; + logic cmd_info_21_busy_21_qs; + logic cmd_info_21_busy_21_wd; + logic cmd_info_21_valid_21_qs; + logic cmd_info_21_valid_21_wd; + logic cmd_info_22_we; + logic [7:0] cmd_info_22_opcode_22_qs; + logic [7:0] cmd_info_22_opcode_22_wd; + logic [1:0] cmd_info_22_addr_mode_22_qs; + logic [1:0] cmd_info_22_addr_mode_22_wd; + logic cmd_info_22_addr_swap_en_22_qs; + logic cmd_info_22_addr_swap_en_22_wd; + logic cmd_info_22_mbyte_en_22_qs; + logic cmd_info_22_mbyte_en_22_wd; + logic [2:0] cmd_info_22_dummy_size_22_qs; + logic [2:0] cmd_info_22_dummy_size_22_wd; + logic cmd_info_22_dummy_en_22_qs; + logic cmd_info_22_dummy_en_22_wd; + logic [3:0] cmd_info_22_payload_en_22_qs; + logic [3:0] cmd_info_22_payload_en_22_wd; + logic cmd_info_22_payload_dir_22_qs; + logic cmd_info_22_payload_dir_22_wd; + logic cmd_info_22_payload_swap_en_22_qs; + logic cmd_info_22_payload_swap_en_22_wd; + logic [1:0] cmd_info_22_read_pipeline_mode_22_qs; + logic [1:0] cmd_info_22_read_pipeline_mode_22_wd; + logic cmd_info_22_upload_22_qs; + logic cmd_info_22_upload_22_wd; + logic cmd_info_22_busy_22_qs; + logic cmd_info_22_busy_22_wd; + logic cmd_info_22_valid_22_qs; + logic cmd_info_22_valid_22_wd; + logic cmd_info_23_we; + logic [7:0] cmd_info_23_opcode_23_qs; + logic [7:0] cmd_info_23_opcode_23_wd; + logic [1:0] cmd_info_23_addr_mode_23_qs; + logic [1:0] cmd_info_23_addr_mode_23_wd; + logic cmd_info_23_addr_swap_en_23_qs; + logic cmd_info_23_addr_swap_en_23_wd; + logic cmd_info_23_mbyte_en_23_qs; + logic cmd_info_23_mbyte_en_23_wd; + logic [2:0] cmd_info_23_dummy_size_23_qs; + logic [2:0] cmd_info_23_dummy_size_23_wd; + logic cmd_info_23_dummy_en_23_qs; + logic cmd_info_23_dummy_en_23_wd; + logic [3:0] cmd_info_23_payload_en_23_qs; + logic [3:0] cmd_info_23_payload_en_23_wd; + logic cmd_info_23_payload_dir_23_qs; + logic cmd_info_23_payload_dir_23_wd; + logic cmd_info_23_payload_swap_en_23_qs; + logic cmd_info_23_payload_swap_en_23_wd; + logic [1:0] cmd_info_23_read_pipeline_mode_23_qs; + logic [1:0] cmd_info_23_read_pipeline_mode_23_wd; + logic cmd_info_23_upload_23_qs; + logic cmd_info_23_upload_23_wd; + logic cmd_info_23_busy_23_qs; + logic cmd_info_23_busy_23_wd; + logic cmd_info_23_valid_23_qs; + logic cmd_info_23_valid_23_wd; + logic cmd_info_en4b_we; + logic [7:0] cmd_info_en4b_opcode_qs; + logic [7:0] cmd_info_en4b_opcode_wd; + logic cmd_info_en4b_valid_qs; + logic cmd_info_en4b_valid_wd; + logic cmd_info_ex4b_we; + logic [7:0] cmd_info_ex4b_opcode_qs; + logic [7:0] cmd_info_ex4b_opcode_wd; + logic cmd_info_ex4b_valid_qs; + logic cmd_info_ex4b_valid_wd; + logic cmd_info_wren_we; + logic [7:0] cmd_info_wren_opcode_qs; + logic [7:0] cmd_info_wren_opcode_wd; + logic cmd_info_wren_valid_qs; + logic cmd_info_wren_valid_wd; + logic cmd_info_wrdi_we; + logic [7:0] cmd_info_wrdi_opcode_qs; + logic [7:0] cmd_info_wrdi_opcode_wd; + logic cmd_info_wrdi_valid_qs; + logic cmd_info_wrdi_valid_wd; + logic [7:0] tpm_cap_rev_qs; + logic tpm_cap_locality_qs; + logic [2:0] tpm_cap_max_wr_size_qs; + logic [2:0] tpm_cap_max_rd_size_qs; + logic tpm_cfg_we; + logic tpm_cfg_en_qs; + logic tpm_cfg_en_wd; + logic tpm_cfg_tpm_mode_qs; + logic tpm_cfg_tpm_mode_wd; + logic tpm_cfg_hw_reg_dis_qs; + logic tpm_cfg_hw_reg_dis_wd; + logic tpm_cfg_tpm_reg_chk_dis_qs; + logic tpm_cfg_tpm_reg_chk_dis_wd; + logic tpm_cfg_invalid_locality_qs; + logic tpm_cfg_invalid_locality_wd; + logic tpm_status_re; + logic tpm_status_we; + logic tpm_status_cmdaddr_notempty_qs; + logic tpm_status_wrfifo_pending_qs; + logic tpm_status_wrfifo_pending_wd; + logic tpm_status_rdfifo_aborted_qs; + logic tpm_access_0_we; + logic [7:0] tpm_access_0_access_0_qs; + logic [7:0] tpm_access_0_access_0_wd; + logic [7:0] tpm_access_0_access_1_qs; + logic [7:0] tpm_access_0_access_1_wd; + logic [7:0] tpm_access_0_access_2_qs; + logic [7:0] tpm_access_0_access_2_wd; + logic [7:0] tpm_access_0_access_3_qs; + logic [7:0] tpm_access_0_access_3_wd; + logic tpm_access_1_we; + logic [7:0] tpm_access_1_qs; + logic [7:0] tpm_access_1_wd; + logic tpm_sts_we; + logic [31:0] tpm_sts_qs; + logic [31:0] tpm_sts_wd; + logic tpm_intf_capability_we; + logic [31:0] tpm_intf_capability_qs; + logic [31:0] tpm_intf_capability_wd; + logic tpm_int_enable_we; + logic [31:0] tpm_int_enable_qs; + logic [31:0] tpm_int_enable_wd; + logic tpm_int_vector_we; + logic [7:0] tpm_int_vector_qs; + logic [7:0] tpm_int_vector_wd; + logic tpm_int_status_we; + logic [31:0] tpm_int_status_qs; + logic [31:0] tpm_int_status_wd; + logic tpm_did_vid_we; + logic [15:0] tpm_did_vid_vid_qs; + logic [15:0] tpm_did_vid_vid_wd; + logic [15:0] tpm_did_vid_did_qs; + logic [15:0] tpm_did_vid_did_wd; + logic tpm_rid_we; + logic [7:0] tpm_rid_qs; + logic [7:0] tpm_rid_wd; + logic tpm_cmd_addr_re; + logic [23:0] tpm_cmd_addr_addr_qs; + logic [7:0] tpm_cmd_addr_cmd_qs; + logic tpm_read_fifo_we; + logic [31:0] tpm_read_fifo_wd; + // Register instances + // R[intr_state]: V(False) + // F[upload_cmdfifo_not_empty]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_upload_cmdfifo_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_upload_cmdfifo_not_empty_wd), + + // from internal hardware + .de (hw2reg.intr_state.upload_cmdfifo_not_empty.de), + .d (hw2reg.intr_state.upload_cmdfifo_not_empty.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.upload_cmdfifo_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_state_upload_cmdfifo_not_empty_qs) + ); + + // F[upload_payload_not_empty]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_upload_payload_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_upload_payload_not_empty_wd), + + // from internal hardware + .de (hw2reg.intr_state.upload_payload_not_empty.de), + .d (hw2reg.intr_state.upload_payload_not_empty.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.upload_payload_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_state_upload_payload_not_empty_qs) + ); + + // F[upload_payload_overflow]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_upload_payload_overflow ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_upload_payload_overflow_wd), + + // from internal hardware + .de (hw2reg.intr_state.upload_payload_overflow.de), + .d (hw2reg.intr_state.upload_payload_overflow.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.upload_payload_overflow.q), + .ds (), + + // to register interface (read) + .qs (intr_state_upload_payload_overflow_qs) + ); + + // F[readbuf_watermark]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_readbuf_watermark ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_readbuf_watermark_wd), + + // from internal hardware + .de (hw2reg.intr_state.readbuf_watermark.de), + .d (hw2reg.intr_state.readbuf_watermark.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.readbuf_watermark.q), + .ds (), + + // to register interface (read) + .qs (intr_state_readbuf_watermark_qs) + ); + + // F[readbuf_flip]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_readbuf_flip ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_readbuf_flip_wd), + + // from internal hardware + .de (hw2reg.intr_state.readbuf_flip.de), + .d (hw2reg.intr_state.readbuf_flip.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.readbuf_flip.q), + .ds (), + + // to register interface (read) + .qs (intr_state_readbuf_flip_qs) + ); + + // F[tpm_header_not_empty]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_tpm_header_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.intr_state.tpm_header_not_empty.de), + .d (hw2reg.intr_state.tpm_header_not_empty.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.tpm_header_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_state_tpm_header_not_empty_qs) + ); + + // F[tpm_rdfifo_cmd_end]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_tpm_rdfifo_cmd_end ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_tpm_rdfifo_cmd_end_wd), + + // from internal hardware + .de (hw2reg.intr_state.tpm_rdfifo_cmd_end.de), + .d (hw2reg.intr_state.tpm_rdfifo_cmd_end.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.tpm_rdfifo_cmd_end.q), + .ds (), + + // to register interface (read) + .qs (intr_state_tpm_rdfifo_cmd_end_qs) + ); + + // F[tpm_rdfifo_drop]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_tpm_rdfifo_drop ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_tpm_rdfifo_drop_wd), + + // from internal hardware + .de (hw2reg.intr_state.tpm_rdfifo_drop.de), + .d (hw2reg.intr_state.tpm_rdfifo_drop.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.tpm_rdfifo_drop.q), + .ds (), + + // to register interface (read) + .qs (intr_state_tpm_rdfifo_drop_qs) + ); + + + // R[intr_enable]: V(False) + // F[upload_cmdfifo_not_empty]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_upload_cmdfifo_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_upload_cmdfifo_not_empty_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.upload_cmdfifo_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_upload_cmdfifo_not_empty_qs) + ); + + // F[upload_payload_not_empty]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_upload_payload_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_upload_payload_not_empty_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.upload_payload_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_upload_payload_not_empty_qs) + ); + + // F[upload_payload_overflow]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_upload_payload_overflow ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_upload_payload_overflow_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.upload_payload_overflow.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_upload_payload_overflow_qs) + ); + + // F[readbuf_watermark]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_readbuf_watermark ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_readbuf_watermark_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.readbuf_watermark.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_readbuf_watermark_qs) + ); + + // F[readbuf_flip]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_readbuf_flip ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_readbuf_flip_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.readbuf_flip.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_readbuf_flip_qs) + ); + + // F[tpm_header_not_empty]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_tpm_header_not_empty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_tpm_header_not_empty_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.tpm_header_not_empty.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_tpm_header_not_empty_qs) + ); + + // F[tpm_rdfifo_cmd_end]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_tpm_rdfifo_cmd_end ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_tpm_rdfifo_cmd_end_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.tpm_rdfifo_cmd_end.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_tpm_rdfifo_cmd_end_qs) + ); + + // F[tpm_rdfifo_drop]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_tpm_rdfifo_drop ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_tpm_rdfifo_drop_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.tpm_rdfifo_drop.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_tpm_rdfifo_drop_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [7:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[upload_cmdfifo_not_empty]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_upload_cmdfifo_not_empty ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_upload_cmdfifo_not_empty_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.upload_cmdfifo_not_empty.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.upload_cmdfifo_not_empty.qe = intr_test_qe; + + // F[upload_payload_not_empty]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_upload_payload_not_empty ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_upload_payload_not_empty_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.upload_payload_not_empty.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.upload_payload_not_empty.qe = intr_test_qe; + + // F[upload_payload_overflow]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_upload_payload_overflow ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_upload_payload_overflow_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[2]), + .q (reg2hw.intr_test.upload_payload_overflow.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.upload_payload_overflow.qe = intr_test_qe; + + // F[readbuf_watermark]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_readbuf_watermark ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_readbuf_watermark_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[3]), + .q (reg2hw.intr_test.readbuf_watermark.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.readbuf_watermark.qe = intr_test_qe; + + // F[readbuf_flip]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_readbuf_flip ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_readbuf_flip_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[4]), + .q (reg2hw.intr_test.readbuf_flip.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.readbuf_flip.qe = intr_test_qe; + + // F[tpm_header_not_empty]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_tpm_header_not_empty ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_tpm_header_not_empty_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[5]), + .q (reg2hw.intr_test.tpm_header_not_empty.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.tpm_header_not_empty.qe = intr_test_qe; + + // F[tpm_rdfifo_cmd_end]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_tpm_rdfifo_cmd_end ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_tpm_rdfifo_cmd_end_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[6]), + .q (reg2hw.intr_test.tpm_rdfifo_cmd_end.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.tpm_rdfifo_cmd_end.qe = intr_test_qe; + + // F[tpm_rdfifo_drop]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_tpm_rdfifo_drop ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_tpm_rdfifo_drop_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[7]), + .q (reg2hw.intr_test.tpm_rdfifo_drop.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.tpm_rdfifo_drop.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // R[control]: V(False) + // F[flash_status_fifo_clr]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1S), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_flash_status_fifo_clr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_we), + .wd (control_flash_status_fifo_clr_wd), + + // from internal hardware + .de (hw2reg.control.flash_status_fifo_clr.de), + .d (hw2reg.control.flash_status_fifo_clr.d), + + // to internal hardware + .qe (), + .q (reg2hw.control.flash_status_fifo_clr.q), + .ds (), + + // to register interface (read) + .qs (control_flash_status_fifo_clr_qs) + ); + + // F[flash_read_buffer_clr]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1S), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_flash_read_buffer_clr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_we), + .wd (control_flash_read_buffer_clr_wd), + + // from internal hardware + .de (hw2reg.control.flash_read_buffer_clr.de), + .d (hw2reg.control.flash_read_buffer_clr.d), + + // to internal hardware + .qe (), + .q (reg2hw.control.flash_read_buffer_clr.q), + .ds (), + + // to register interface (read) + .qs (control_flash_read_buffer_clr_qs) + ); + + // F[mode]: 5:4 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_control_mode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_we), + .wd (control_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.mode.q), + .ds (), + + // to register interface (read) + .qs (control_mode_qs) + ); + + + // R[cfg]: V(False) + // F[tx_order]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_tx_order ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cfg_we), + .wd (cfg_tx_order_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.tx_order.q), + .ds (), + + // to register interface (read) + .qs (cfg_tx_order_qs) + ); + + // F[rx_order]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_rx_order ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cfg_we), + .wd (cfg_rx_order_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.rx_order.q), + .ds (), + + // to register interface (read) + .qs (cfg_rx_order_qs) + ); + + // F[mailbox_en]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_mailbox_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cfg_we), + .wd (cfg_mailbox_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.mailbox_en.q), + .ds (), + + // to register interface (read) + .qs (cfg_mailbox_en_qs) + ); + + + // R[status]: V(True) + // F[csb]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_status_csb ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.csb.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_csb_qs) + ); + + // F[tpm_csb]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_status_tpm_csb ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.tpm_csb.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_tpm_csb_qs) + ); + + + // R[intercept_en]: V(False) + // F[status]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intercept_en_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intercept_en_we), + .wd (intercept_en_status_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intercept_en.status.q), + .ds (), + + // to register interface (read) + .qs (intercept_en_status_qs) + ); + + // F[jedec]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intercept_en_jedec ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intercept_en_we), + .wd (intercept_en_jedec_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intercept_en.jedec.q), + .ds (), + + // to register interface (read) + .qs (intercept_en_jedec_qs) + ); + + // F[sfdp]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intercept_en_sfdp ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intercept_en_we), + .wd (intercept_en_sfdp_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intercept_en.sfdp.q), + .ds (), + + // to register interface (read) + .qs (intercept_en_sfdp_qs) + ); + + // F[mbx]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intercept_en_mbx ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intercept_en_we), + .wd (intercept_en_mbx_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intercept_en.mbx.q), + .ds (), + + // to register interface (read) + .qs (intercept_en_mbx_qs) + ); + + + // R[addr_mode]: V(True) + logic addr_mode_qe; + logic [1:0] addr_mode_flds_we; + // This ignores QEs that are set to constant 0 due to read-only fields. + logic unused_addr_mode_flds_we; + assign unused_addr_mode_flds_we = ^(addr_mode_flds_we & 2'h2); + assign addr_mode_qe = &(addr_mode_flds_we | 2'h2); + // F[addr_4b_en]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_addr_mode_addr_4b_en ( + .re (addr_mode_re), + .we (addr_mode_we), + .wd (addr_mode_addr_4b_en_wd), + .d (hw2reg.addr_mode.addr_4b_en.d), + .qre (), + .qe (addr_mode_flds_we[0]), + .q (reg2hw.addr_mode.addr_4b_en.q), + .ds (), + .qs (addr_mode_addr_4b_en_qs) + ); + assign reg2hw.addr_mode.addr_4b_en.qe = addr_mode_qe; + + // F[pending]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_addr_mode_pending ( + .re (addr_mode_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.addr_mode.pending.d), + .qre (), + .qe (addr_mode_flds_we[1]), + .q (), + .ds (), + .qs (addr_mode_pending_qs) + ); + + + // R[last_read_addr]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_last_read_addr ( + .re (last_read_addr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.last_read_addr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (last_read_addr_qs) + ); + + + // R[flash_status]: V(True) + logic flash_status_qe; + logic [2:0] flash_status_flds_we; + assign flash_status_qe = &flash_status_flds_we; + // F[busy]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_flash_status_busy ( + .re (flash_status_re), + .we (flash_status_we), + .wd (flash_status_busy_wd), + .d (hw2reg.flash_status.busy.d), + .qre (), + .qe (flash_status_flds_we[0]), + .q (reg2hw.flash_status.busy.q), + .ds (), + .qs (flash_status_busy_qs) + ); + assign reg2hw.flash_status.busy.qe = flash_status_qe; + + // F[wel]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_flash_status_wel ( + .re (flash_status_re), + .we (flash_status_we), + .wd (flash_status_wel_wd), + .d (hw2reg.flash_status.wel.d), + .qre (), + .qe (flash_status_flds_we[1]), + .q (reg2hw.flash_status.wel.q), + .ds (), + .qs (flash_status_wel_qs) + ); + assign reg2hw.flash_status.wel.qe = flash_status_qe; + + // F[status]: 23:2 + prim_subreg_ext #( + .DW (22) + ) u_flash_status_status ( + .re (flash_status_re), + .we (flash_status_we), + .wd (flash_status_status_wd), + .d (hw2reg.flash_status.status.d), + .qre (), + .qe (flash_status_flds_we[2]), + .q (reg2hw.flash_status.status.q), + .ds (), + .qs (flash_status_status_qs) + ); + assign reg2hw.flash_status.status.qe = flash_status_qe; + + + // R[jedec_cc]: V(False) + // F[cc]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h7f), + .Mubi (1'b0) + ) u_jedec_cc_cc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jedec_cc_we), + .wd (jedec_cc_cc_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jedec_cc.cc.q), + .ds (), + + // to register interface (read) + .qs (jedec_cc_cc_qs) + ); + + // F[num_cc]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_jedec_cc_num_cc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jedec_cc_we), + .wd (jedec_cc_num_cc_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jedec_cc.num_cc.q), + .ds (), + + // to register interface (read) + .qs (jedec_cc_num_cc_qs) + ); + + + // R[jedec_id]: V(False) + // F[id]: 15:0 + prim_subreg #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_jedec_id_id ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jedec_id_we), + .wd (jedec_id_id_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jedec_id.id.q), + .ds (), + + // to register interface (read) + .qs (jedec_id_id_qs) + ); + + // F[mf]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_jedec_id_mf ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jedec_id_we), + .wd (jedec_id_mf_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jedec_id.mf.q), + .ds (), + + // to register interface (read) + .qs (jedec_id_mf_qs) + ); + + + // R[read_threshold]: V(False) + prim_subreg #( + .DW (10), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (10'h0), + .Mubi (1'b0) + ) u_read_threshold ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (read_threshold_we), + .wd (read_threshold_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.read_threshold.q), + .ds (), + + // to register interface (read) + .qs (read_threshold_qs) + ); + + + // R[mailbox_addr]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_mailbox_addr ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mailbox_addr_we), + .wd (mailbox_addr_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mailbox_addr.q), + .ds (), + + // to register interface (read) + .qs (mailbox_addr_qs) + ); + + + // R[upload_status]: V(False) + // F[cmdfifo_depth]: 4:0 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_upload_status_cmdfifo_depth ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status.cmdfifo_depth.de), + .d (hw2reg.upload_status.cmdfifo_depth.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status_cmdfifo_depth_qs) + ); + + // F[cmdfifo_notempty]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_upload_status_cmdfifo_notempty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status.cmdfifo_notempty.de), + .d (hw2reg.upload_status.cmdfifo_notempty.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status_cmdfifo_notempty_qs) + ); + + // F[addrfifo_depth]: 12:8 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_upload_status_addrfifo_depth ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status.addrfifo_depth.de), + .d (hw2reg.upload_status.addrfifo_depth.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status_addrfifo_depth_qs) + ); + + // F[addrfifo_notempty]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_upload_status_addrfifo_notempty ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status.addrfifo_notempty.de), + .d (hw2reg.upload_status.addrfifo_notempty.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status_addrfifo_notempty_qs) + ); + + + // R[upload_status2]: V(False) + // F[payload_depth]: 8:0 + prim_subreg #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (9'h0), + .Mubi (1'b0) + ) u_upload_status2_payload_depth ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status2.payload_depth.de), + .d (hw2reg.upload_status2.payload_depth.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status2_payload_depth_qs) + ); + + // F[payload_start_idx]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_upload_status2_payload_start_idx ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.upload_status2.payload_start_idx.de), + .d (hw2reg.upload_status2.payload_start_idx.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (upload_status2_payload_start_idx_qs) + ); + + + // R[upload_cmdfifo]: V(True) + // F[data]: 7:0 + prim_subreg_ext #( + .DW (8) + ) u_upload_cmdfifo_data ( + .re (upload_cmdfifo_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.upload_cmdfifo.data.d), + .qre (reg2hw.upload_cmdfifo.data.re), + .qe (), + .q (reg2hw.upload_cmdfifo.data.q), + .ds (), + .qs (upload_cmdfifo_data_qs) + ); + + // F[busy]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_upload_cmdfifo_busy ( + .re (upload_cmdfifo_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.upload_cmdfifo.busy.d), + .qre (reg2hw.upload_cmdfifo.busy.re), + .qe (), + .q (reg2hw.upload_cmdfifo.busy.q), + .ds (), + .qs (upload_cmdfifo_busy_qs) + ); + + // F[wel]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_upload_cmdfifo_wel ( + .re (upload_cmdfifo_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.upload_cmdfifo.wel.d), + .qre (reg2hw.upload_cmdfifo.wel.re), + .qe (), + .q (reg2hw.upload_cmdfifo.wel.q), + .ds (), + .qs (upload_cmdfifo_wel_qs) + ); + + // F[addr4b_mode]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_upload_cmdfifo_addr4b_mode ( + .re (upload_cmdfifo_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.upload_cmdfifo.addr4b_mode.d), + .qre (reg2hw.upload_cmdfifo.addr4b_mode.re), + .qe (), + .q (reg2hw.upload_cmdfifo.addr4b_mode.q), + .ds (), + .qs (upload_cmdfifo_addr4b_mode_qs) + ); + + + // R[upload_addrfifo]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_upload_addrfifo ( + .re (upload_addrfifo_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.upload_addrfifo.d), + .qre (reg2hw.upload_addrfifo.re), + .qe (), + .q (reg2hw.upload_addrfifo.q), + .ds (), + .qs (upload_addrfifo_qs) + ); + + + // Subregister 0 of Multireg cmd_filter + // R[cmd_filter_0]: V(False) + // F[filter_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[0].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_0_qs) + ); + + // F[filter_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[1].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_1_qs) + ); + + // F[filter_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[2].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_2_qs) + ); + + // F[filter_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[3].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_3_qs) + ); + + // F[filter_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[4].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_4_qs) + ); + + // F[filter_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[5].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_5_qs) + ); + + // F[filter_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[6].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_6_qs) + ); + + // F[filter_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[7].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_7_qs) + ); + + // F[filter_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[8].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_8_qs) + ); + + // F[filter_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[9].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_9_qs) + ); + + // F[filter_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[10].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_10_qs) + ); + + // F[filter_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[11].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_11_qs) + ); + + // F[filter_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[12].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_12_qs) + ); + + // F[filter_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[13].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_13_qs) + ); + + // F[filter_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[14].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_14_qs) + ); + + // F[filter_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[15].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_15_qs) + ); + + // F[filter_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[16].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_16_qs) + ); + + // F[filter_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[17].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_17_qs) + ); + + // F[filter_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[18].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_18_qs) + ); + + // F[filter_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[19].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_19_qs) + ); + + // F[filter_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[20].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_20_qs) + ); + + // F[filter_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[21].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_21_qs) + ); + + // F[filter_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[22].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_22_qs) + ); + + // F[filter_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[23].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_23_qs) + ); + + // F[filter_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[24].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_24_qs) + ); + + // F[filter_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[25].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_25_qs) + ); + + // F[filter_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[26].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_26_qs) + ); + + // F[filter_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[27].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_27_qs) + ); + + // F[filter_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[28].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_28_qs) + ); + + // F[filter_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[29].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_29_qs) + ); + + // F[filter_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[30].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_30_qs) + ); + + // F[filter_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_0_filter_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_0_we), + .wd (cmd_filter_0_filter_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[31].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_0_filter_31_qs) + ); + + + // Subregister 1 of Multireg cmd_filter + // R[cmd_filter_1]: V(False) + // F[filter_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[32].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_32_qs) + ); + + // F[filter_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[33].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_33_qs) + ); + + // F[filter_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[34].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_34_qs) + ); + + // F[filter_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[35].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_35_qs) + ); + + // F[filter_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[36].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_36_qs) + ); + + // F[filter_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[37].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_37_qs) + ); + + // F[filter_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[38].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_38_qs) + ); + + // F[filter_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[39].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_39_qs) + ); + + // F[filter_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[40].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_40_qs) + ); + + // F[filter_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[41].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_41_qs) + ); + + // F[filter_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[42].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_42_qs) + ); + + // F[filter_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[43].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_43_qs) + ); + + // F[filter_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[44].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_44_qs) + ); + + // F[filter_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[45].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_45_qs) + ); + + // F[filter_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[46].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_46_qs) + ); + + // F[filter_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[47].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_47_qs) + ); + + // F[filter_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[48].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_48_qs) + ); + + // F[filter_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[49].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_49_qs) + ); + + // F[filter_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[50].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_50_qs) + ); + + // F[filter_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[51].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_51_qs) + ); + + // F[filter_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[52].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_52_qs) + ); + + // F[filter_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[53].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_53_qs) + ); + + // F[filter_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[54].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_54_qs) + ); + + // F[filter_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[55].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_55_qs) + ); + + // F[filter_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[56].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_56_qs) + ); + + // F[filter_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[57].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_57_qs) + ); + + // F[filter_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[58].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_58_qs) + ); + + // F[filter_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[59].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_59_qs) + ); + + // F[filter_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[60].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_60_qs) + ); + + // F[filter_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[61].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_61_qs) + ); + + // F[filter_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[62].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_62_qs) + ); + + // F[filter_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_1_filter_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_1_we), + .wd (cmd_filter_1_filter_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[63].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_1_filter_63_qs) + ); + + + // Subregister 2 of Multireg cmd_filter + // R[cmd_filter_2]: V(False) + // F[filter_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[64].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_64_qs) + ); + + // F[filter_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[65].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_65_qs) + ); + + // F[filter_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[66].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_66_qs) + ); + + // F[filter_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[67].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_67_qs) + ); + + // F[filter_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[68].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_68_qs) + ); + + // F[filter_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[69].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_69_qs) + ); + + // F[filter_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[70].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_70_qs) + ); + + // F[filter_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[71].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_71_qs) + ); + + // F[filter_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[72].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_72_qs) + ); + + // F[filter_73]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[73].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_73_qs) + ); + + // F[filter_74]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[74].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_74_qs) + ); + + // F[filter_75]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[75].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_75_qs) + ); + + // F[filter_76]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[76].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_76_qs) + ); + + // F[filter_77]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[77].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_77_qs) + ); + + // F[filter_78]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[78].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_78_qs) + ); + + // F[filter_79]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[79].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_79_qs) + ); + + // F[filter_80]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[80].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_80_qs) + ); + + // F[filter_81]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[81].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_81_qs) + ); + + // F[filter_82]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[82].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_82_qs) + ); + + // F[filter_83]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[83].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_83_qs) + ); + + // F[filter_84]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[84].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_84_qs) + ); + + // F[filter_85]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[85].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_85_qs) + ); + + // F[filter_86]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[86].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_86_qs) + ); + + // F[filter_87]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[87].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_87_qs) + ); + + // F[filter_88]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[88].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_88_qs) + ); + + // F[filter_89]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[89].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_89_qs) + ); + + // F[filter_90]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[90].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_90_qs) + ); + + // F[filter_91]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[91].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_91_qs) + ); + + // F[filter_92]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[92].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_92_qs) + ); + + // F[filter_93]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[93].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_93_qs) + ); + + // F[filter_94]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[94].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_94_qs) + ); + + // F[filter_95]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_2_filter_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_2_we), + .wd (cmd_filter_2_filter_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[95].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_2_filter_95_qs) + ); + + + // Subregister 3 of Multireg cmd_filter + // R[cmd_filter_3]: V(False) + // F[filter_96]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[96].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_96_qs) + ); + + // F[filter_97]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[97].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_97_qs) + ); + + // F[filter_98]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[98].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_98_qs) + ); + + // F[filter_99]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_99_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[99].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_99_qs) + ); + + // F[filter_100]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_100_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[100].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_100_qs) + ); + + // F[filter_101]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_101_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[101].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_101_qs) + ); + + // F[filter_102]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_102_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[102].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_102_qs) + ); + + // F[filter_103]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_103_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[103].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_103_qs) + ); + + // F[filter_104]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_104_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[104].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_104_qs) + ); + + // F[filter_105]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_105_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[105].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_105_qs) + ); + + // F[filter_106]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_106_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[106].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_106_qs) + ); + + // F[filter_107]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_107_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[107].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_107_qs) + ); + + // F[filter_108]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_108_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[108].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_108_qs) + ); + + // F[filter_109]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_109_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[109].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_109_qs) + ); + + // F[filter_110]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_110_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[110].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_110_qs) + ); + + // F[filter_111]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_111_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[111].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_111_qs) + ); + + // F[filter_112]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_112_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[112].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_112_qs) + ); + + // F[filter_113]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_113_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[113].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_113_qs) + ); + + // F[filter_114]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_114_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[114].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_114_qs) + ); + + // F[filter_115]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_115_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[115].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_115_qs) + ); + + // F[filter_116]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_116_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[116].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_116_qs) + ); + + // F[filter_117]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_117_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[117].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_117_qs) + ); + + // F[filter_118]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_118_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[118].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_118_qs) + ); + + // F[filter_119]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_119_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[119].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_119_qs) + ); + + // F[filter_120]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_120_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[120].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_120_qs) + ); + + // F[filter_121]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_121_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[121].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_121_qs) + ); + + // F[filter_122]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[122].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_122_qs) + ); + + // F[filter_123]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[123].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_123_qs) + ); + + // F[filter_124]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[124].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_124_qs) + ); + + // F[filter_125]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[125].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_125_qs) + ); + + // F[filter_126]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[126].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_126_qs) + ); + + // F[filter_127]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_3_filter_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_3_we), + .wd (cmd_filter_3_filter_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[127].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_3_filter_127_qs) + ); + + + // Subregister 4 of Multireg cmd_filter + // R[cmd_filter_4]: V(False) + // F[filter_128]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[128].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_128_qs) + ); + + // F[filter_129]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[129].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_129_qs) + ); + + // F[filter_130]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[130].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_130_qs) + ); + + // F[filter_131]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[131].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_131_qs) + ); + + // F[filter_132]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[132].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_132_qs) + ); + + // F[filter_133]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[133].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_133_qs) + ); + + // F[filter_134]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[134].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_134_qs) + ); + + // F[filter_135]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[135].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_135_qs) + ); + + // F[filter_136]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[136].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_136_qs) + ); + + // F[filter_137]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[137].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_137_qs) + ); + + // F[filter_138]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[138].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_138_qs) + ); + + // F[filter_139]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[139].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_139_qs) + ); + + // F[filter_140]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[140].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_140_qs) + ); + + // F[filter_141]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[141].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_141_qs) + ); + + // F[filter_142]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[142].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_142_qs) + ); + + // F[filter_143]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[143].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_143_qs) + ); + + // F[filter_144]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[144].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_144_qs) + ); + + // F[filter_145]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[145].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_145_qs) + ); + + // F[filter_146]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[146].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_146_qs) + ); + + // F[filter_147]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[147].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_147_qs) + ); + + // F[filter_148]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[148].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_148_qs) + ); + + // F[filter_149]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[149].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_149_qs) + ); + + // F[filter_150]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[150].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_150_qs) + ); + + // F[filter_151]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[151].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_151_qs) + ); + + // F[filter_152]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[152].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_152_qs) + ); + + // F[filter_153]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[153].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_153_qs) + ); + + // F[filter_154]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[154].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_154_qs) + ); + + // F[filter_155]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[155].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_155_qs) + ); + + // F[filter_156]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[156].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_156_qs) + ); + + // F[filter_157]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[157].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_157_qs) + ); + + // F[filter_158]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[158].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_158_qs) + ); + + // F[filter_159]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_4_filter_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_4_we), + .wd (cmd_filter_4_filter_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[159].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_4_filter_159_qs) + ); + + + // Subregister 5 of Multireg cmd_filter + // R[cmd_filter_5]: V(False) + // F[filter_160]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_160 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[160].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_160_qs) + ); + + // F[filter_161]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_161 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[161].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_161_qs) + ); + + // F[filter_162]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_162 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[162].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_162_qs) + ); + + // F[filter_163]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_163 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_163_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[163].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_163_qs) + ); + + // F[filter_164]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_164 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_164_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[164].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_164_qs) + ); + + // F[filter_165]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_165 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_165_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[165].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_165_qs) + ); + + // F[filter_166]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_166 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_166_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[166].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_166_qs) + ); + + // F[filter_167]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_167 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_167_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[167].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_167_qs) + ); + + // F[filter_168]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_168 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_168_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[168].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_168_qs) + ); + + // F[filter_169]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_169 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_169_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[169].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_169_qs) + ); + + // F[filter_170]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_170 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_170_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[170].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_170_qs) + ); + + // F[filter_171]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_171 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_171_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[171].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_171_qs) + ); + + // F[filter_172]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_172 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_172_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[172].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_172_qs) + ); + + // F[filter_173]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_173 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_173_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[173].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_173_qs) + ); + + // F[filter_174]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_174 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_174_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[174].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_174_qs) + ); + + // F[filter_175]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_175 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_175_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[175].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_175_qs) + ); + + // F[filter_176]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_176 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_176_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[176].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_176_qs) + ); + + // F[filter_177]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_177 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_177_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[177].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_177_qs) + ); + + // F[filter_178]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_178 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_178_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[178].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_178_qs) + ); + + // F[filter_179]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_179 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_179_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[179].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_179_qs) + ); + + // F[filter_180]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_180 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_180_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[180].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_180_qs) + ); + + // F[filter_181]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_181 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_181_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[181].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_181_qs) + ); + + // F[filter_182]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_182 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_182_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[182].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_182_qs) + ); + + // F[filter_183]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_183 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_183_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[183].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_183_qs) + ); + + // F[filter_184]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_184 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_184_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[184].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_184_qs) + ); + + // F[filter_185]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_185 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_185_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[185].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_185_qs) + ); + + // F[filter_186]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_186 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_186_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[186].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_186_qs) + ); + + // F[filter_187]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_187 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_187_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[187].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_187_qs) + ); + + // F[filter_188]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_188 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_188_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[188].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_188_qs) + ); + + // F[filter_189]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_189 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_189_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[189].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_189_qs) + ); + + // F[filter_190]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_190 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_190_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[190].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_190_qs) + ); + + // F[filter_191]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_5_filter_191 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_5_we), + .wd (cmd_filter_5_filter_191_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[191].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_5_filter_191_qs) + ); + + + // Subregister 6 of Multireg cmd_filter + // R[cmd_filter_6]: V(False) + // F[filter_192]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_192 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_192_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[192].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_192_qs) + ); + + // F[filter_193]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_193 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_193_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[193].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_193_qs) + ); + + // F[filter_194]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_194 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_194_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[194].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_194_qs) + ); + + // F[filter_195]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_195 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_195_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[195].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_195_qs) + ); + + // F[filter_196]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_196 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_196_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[196].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_196_qs) + ); + + // F[filter_197]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_197 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_197_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[197].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_197_qs) + ); + + // F[filter_198]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_198 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_198_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[198].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_198_qs) + ); + + // F[filter_199]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_199 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_199_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[199].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_199_qs) + ); + + // F[filter_200]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_200 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_200_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[200].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_200_qs) + ); + + // F[filter_201]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_201 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_201_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[201].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_201_qs) + ); + + // F[filter_202]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_202 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_202_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[202].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_202_qs) + ); + + // F[filter_203]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_203 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_203_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[203].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_203_qs) + ); + + // F[filter_204]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_204 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_204_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[204].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_204_qs) + ); + + // F[filter_205]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_205 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_205_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[205].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_205_qs) + ); + + // F[filter_206]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_206 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_206_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[206].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_206_qs) + ); + + // F[filter_207]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_207 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_207_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[207].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_207_qs) + ); + + // F[filter_208]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_208 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_208_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[208].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_208_qs) + ); + + // F[filter_209]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_209 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_209_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[209].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_209_qs) + ); + + // F[filter_210]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_210 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_210_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[210].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_210_qs) + ); + + // F[filter_211]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_211 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_211_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[211].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_211_qs) + ); + + // F[filter_212]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_212 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_212_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[212].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_212_qs) + ); + + // F[filter_213]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_213 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_213_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[213].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_213_qs) + ); + + // F[filter_214]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_214 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_214_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[214].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_214_qs) + ); + + // F[filter_215]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_215 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_215_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[215].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_215_qs) + ); + + // F[filter_216]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_216 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_216_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[216].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_216_qs) + ); + + // F[filter_217]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_217 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_217_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[217].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_217_qs) + ); + + // F[filter_218]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_218 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_218_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[218].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_218_qs) + ); + + // F[filter_219]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_219 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_219_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[219].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_219_qs) + ); + + // F[filter_220]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_220 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_220_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[220].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_220_qs) + ); + + // F[filter_221]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_221 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_221_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[221].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_221_qs) + ); + + // F[filter_222]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_222 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_222_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[222].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_222_qs) + ); + + // F[filter_223]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_6_filter_223 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_6_we), + .wd (cmd_filter_6_filter_223_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[223].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_6_filter_223_qs) + ); + + + // Subregister 7 of Multireg cmd_filter + // R[cmd_filter_7]: V(False) + // F[filter_224]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_224 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_224_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[224].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_224_qs) + ); + + // F[filter_225]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_225 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_225_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[225].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_225_qs) + ); + + // F[filter_226]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_226 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_226_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[226].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_226_qs) + ); + + // F[filter_227]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_227 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_227_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[227].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_227_qs) + ); + + // F[filter_228]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_228 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_228_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[228].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_228_qs) + ); + + // F[filter_229]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_229 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_229_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[229].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_229_qs) + ); + + // F[filter_230]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_230 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_230_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[230].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_230_qs) + ); + + // F[filter_231]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_231 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_231_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[231].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_231_qs) + ); + + // F[filter_232]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_232 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_232_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[232].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_232_qs) + ); + + // F[filter_233]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_233 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_233_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[233].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_233_qs) + ); + + // F[filter_234]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_234 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_234_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[234].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_234_qs) + ); + + // F[filter_235]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_235 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_235_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[235].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_235_qs) + ); + + // F[filter_236]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_236 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_236_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[236].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_236_qs) + ); + + // F[filter_237]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_237 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_237_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[237].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_237_qs) + ); + + // F[filter_238]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_238 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_238_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[238].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_238_qs) + ); + + // F[filter_239]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_239 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_239_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[239].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_239_qs) + ); + + // F[filter_240]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_240 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_240_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[240].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_240_qs) + ); + + // F[filter_241]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_241 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_241_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[241].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_241_qs) + ); + + // F[filter_242]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_242 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_242_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[242].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_242_qs) + ); + + // F[filter_243]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_243 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_243_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[243].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_243_qs) + ); + + // F[filter_244]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_244 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_244_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[244].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_244_qs) + ); + + // F[filter_245]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_245 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_245_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[245].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_245_qs) + ); + + // F[filter_246]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_246 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_246_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[246].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_246_qs) + ); + + // F[filter_247]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_247 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_247_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[247].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_247_qs) + ); + + // F[filter_248]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_248 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_248_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[248].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_248_qs) + ); + + // F[filter_249]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_249 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_249_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[249].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_249_qs) + ); + + // F[filter_250]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_250 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_250_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[250].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_250_qs) + ); + + // F[filter_251]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_251 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_251_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[251].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_251_qs) + ); + + // F[filter_252]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_252 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_252_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[252].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_252_qs) + ); + + // F[filter_253]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_253 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_253_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[253].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_253_qs) + ); + + // F[filter_254]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_254 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_254_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[254].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_254_qs) + ); + + // F[filter_255]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_filter_7_filter_255 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_filter_7_we), + .wd (cmd_filter_7_filter_255_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_filter[255].q), + .ds (), + + // to register interface (read) + .qs (cmd_filter_7_filter_255_qs) + ); + + + // R[addr_swap_mask]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_addr_swap_mask ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (addr_swap_mask_we), + .wd (addr_swap_mask_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.addr_swap_mask.q), + .ds (), + + // to register interface (read) + .qs (addr_swap_mask_qs) + ); + + + // R[addr_swap_data]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_addr_swap_data ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (addr_swap_data_we), + .wd (addr_swap_data_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.addr_swap_data.q), + .ds (), + + // to register interface (read) + .qs (addr_swap_data_qs) + ); + + + // R[payload_swap_mask]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_payload_swap_mask ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (payload_swap_mask_we), + .wd (payload_swap_mask_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.payload_swap_mask.q), + .ds (), + + // to register interface (read) + .qs (payload_swap_mask_qs) + ); + + + // R[payload_swap_data]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_payload_swap_data ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (payload_swap_data_we), + .wd (payload_swap_data_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.payload_swap_data.q), + .ds (), + + // to register interface (read) + .qs (payload_swap_data_qs) + ); + + + // Subregister 0 of Multireg cmd_info + // R[cmd_info_0]: V(False) + // F[opcode_0]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_0_opcode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_opcode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_opcode_0_qs) + ); + + // F[addr_mode_0]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_0_addr_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_addr_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_addr_mode_0_qs) + ); + + // F[addr_swap_en_0]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_addr_swap_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_addr_swap_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_addr_swap_en_0_qs) + ); + + // F[mbyte_en_0]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_mbyte_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_mbyte_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_mbyte_en_0_qs) + ); + + // F[dummy_size_0]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_0_dummy_size_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_dummy_size_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_dummy_size_0_qs) + ); + + // F[dummy_en_0]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_dummy_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_dummy_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_dummy_en_0_qs) + ); + + // F[payload_en_0]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_0_payload_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_payload_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_payload_en_0_qs) + ); + + // F[payload_dir_0]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_payload_dir_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_payload_dir_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_payload_dir_0_qs) + ); + + // F[payload_swap_en_0]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_payload_swap_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_payload_swap_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_payload_swap_en_0_qs) + ); + + // F[read_pipeline_mode_0]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_0_read_pipeline_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_read_pipeline_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_read_pipeline_mode_0_qs) + ); + + // F[upload_0]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_upload_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_upload_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_upload_0_qs) + ); + + // F[busy_0]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_busy_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_busy_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_busy_0_qs) + ); + + // F[valid_0]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_0_valid_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_0_we), + .wd (cmd_info_0_valid_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[0].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_0_valid_0_qs) + ); + + + // Subregister 1 of Multireg cmd_info + // R[cmd_info_1]: V(False) + // F[opcode_1]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_1_opcode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_opcode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_opcode_1_qs) + ); + + // F[addr_mode_1]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_1_addr_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_addr_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_addr_mode_1_qs) + ); + + // F[addr_swap_en_1]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_addr_swap_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_addr_swap_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_addr_swap_en_1_qs) + ); + + // F[mbyte_en_1]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_mbyte_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_mbyte_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_mbyte_en_1_qs) + ); + + // F[dummy_size_1]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_1_dummy_size_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_dummy_size_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_dummy_size_1_qs) + ); + + // F[dummy_en_1]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_dummy_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_dummy_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_dummy_en_1_qs) + ); + + // F[payload_en_1]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_1_payload_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_payload_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_payload_en_1_qs) + ); + + // F[payload_dir_1]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_payload_dir_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_payload_dir_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_payload_dir_1_qs) + ); + + // F[payload_swap_en_1]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_payload_swap_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_payload_swap_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_payload_swap_en_1_qs) + ); + + // F[read_pipeline_mode_1]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_1_read_pipeline_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_read_pipeline_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_read_pipeline_mode_1_qs) + ); + + // F[upload_1]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_upload_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_upload_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_upload_1_qs) + ); + + // F[busy_1]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_busy_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_busy_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_busy_1_qs) + ); + + // F[valid_1]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_1_valid_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_1_we), + .wd (cmd_info_1_valid_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[1].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_1_valid_1_qs) + ); + + + // Subregister 2 of Multireg cmd_info + // R[cmd_info_2]: V(False) + // F[opcode_2]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_2_opcode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_opcode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_opcode_2_qs) + ); + + // F[addr_mode_2]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_2_addr_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_addr_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_addr_mode_2_qs) + ); + + // F[addr_swap_en_2]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_addr_swap_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_addr_swap_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_addr_swap_en_2_qs) + ); + + // F[mbyte_en_2]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_mbyte_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_mbyte_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_mbyte_en_2_qs) + ); + + // F[dummy_size_2]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_2_dummy_size_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_dummy_size_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_dummy_size_2_qs) + ); + + // F[dummy_en_2]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_dummy_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_dummy_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_dummy_en_2_qs) + ); + + // F[payload_en_2]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_2_payload_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_payload_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_payload_en_2_qs) + ); + + // F[payload_dir_2]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_payload_dir_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_payload_dir_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_payload_dir_2_qs) + ); + + // F[payload_swap_en_2]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_payload_swap_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_payload_swap_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_payload_swap_en_2_qs) + ); + + // F[read_pipeline_mode_2]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_2_read_pipeline_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_read_pipeline_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_read_pipeline_mode_2_qs) + ); + + // F[upload_2]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_upload_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_upload_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_upload_2_qs) + ); + + // F[busy_2]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_busy_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_busy_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_busy_2_qs) + ); + + // F[valid_2]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_2_valid_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_2_we), + .wd (cmd_info_2_valid_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[2].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_2_valid_2_qs) + ); + + + // Subregister 3 of Multireg cmd_info + // R[cmd_info_3]: V(False) + // F[opcode_3]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_3_opcode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_opcode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_opcode_3_qs) + ); + + // F[addr_mode_3]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_3_addr_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_addr_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_addr_mode_3_qs) + ); + + // F[addr_swap_en_3]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_addr_swap_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_addr_swap_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_addr_swap_en_3_qs) + ); + + // F[mbyte_en_3]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_mbyte_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_mbyte_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_mbyte_en_3_qs) + ); + + // F[dummy_size_3]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_3_dummy_size_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_dummy_size_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_dummy_size_3_qs) + ); + + // F[dummy_en_3]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_dummy_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_dummy_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_dummy_en_3_qs) + ); + + // F[payload_en_3]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_3_payload_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_payload_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_payload_en_3_qs) + ); + + // F[payload_dir_3]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_payload_dir_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_payload_dir_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_payload_dir_3_qs) + ); + + // F[payload_swap_en_3]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_payload_swap_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_payload_swap_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_payload_swap_en_3_qs) + ); + + // F[read_pipeline_mode_3]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_3_read_pipeline_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_read_pipeline_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_read_pipeline_mode_3_qs) + ); + + // F[upload_3]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_upload_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_upload_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_upload_3_qs) + ); + + // F[busy_3]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_busy_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_busy_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_busy_3_qs) + ); + + // F[valid_3]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_3_valid_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_3_we), + .wd (cmd_info_3_valid_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[3].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_3_valid_3_qs) + ); + + + // Subregister 4 of Multireg cmd_info + // R[cmd_info_4]: V(False) + // F[opcode_4]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_4_opcode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_opcode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_opcode_4_qs) + ); + + // F[addr_mode_4]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_4_addr_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_addr_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_addr_mode_4_qs) + ); + + // F[addr_swap_en_4]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_addr_swap_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_addr_swap_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_addr_swap_en_4_qs) + ); + + // F[mbyte_en_4]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_mbyte_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_mbyte_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_mbyte_en_4_qs) + ); + + // F[dummy_size_4]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_4_dummy_size_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_dummy_size_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_dummy_size_4_qs) + ); + + // F[dummy_en_4]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_dummy_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_dummy_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_dummy_en_4_qs) + ); + + // F[payload_en_4]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_4_payload_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_payload_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_payload_en_4_qs) + ); + + // F[payload_dir_4]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_payload_dir_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_payload_dir_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_payload_dir_4_qs) + ); + + // F[payload_swap_en_4]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_payload_swap_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_payload_swap_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_payload_swap_en_4_qs) + ); + + // F[read_pipeline_mode_4]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_4_read_pipeline_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_read_pipeline_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_read_pipeline_mode_4_qs) + ); + + // F[upload_4]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_upload_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_upload_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_upload_4_qs) + ); + + // F[busy_4]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_busy_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_busy_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_busy_4_qs) + ); + + // F[valid_4]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_4_valid_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_4_we), + .wd (cmd_info_4_valid_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[4].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_4_valid_4_qs) + ); + + + // Subregister 5 of Multireg cmd_info + // R[cmd_info_5]: V(False) + // F[opcode_5]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_5_opcode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_opcode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_opcode_5_qs) + ); + + // F[addr_mode_5]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_5_addr_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_addr_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_addr_mode_5_qs) + ); + + // F[addr_swap_en_5]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_addr_swap_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_addr_swap_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_addr_swap_en_5_qs) + ); + + // F[mbyte_en_5]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_mbyte_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_mbyte_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_mbyte_en_5_qs) + ); + + // F[dummy_size_5]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_5_dummy_size_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_dummy_size_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_dummy_size_5_qs) + ); + + // F[dummy_en_5]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_dummy_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_dummy_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_dummy_en_5_qs) + ); + + // F[payload_en_5]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_5_payload_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_payload_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_payload_en_5_qs) + ); + + // F[payload_dir_5]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_payload_dir_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_payload_dir_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_payload_dir_5_qs) + ); + + // F[payload_swap_en_5]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_payload_swap_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_payload_swap_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_payload_swap_en_5_qs) + ); + + // F[read_pipeline_mode_5]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_5_read_pipeline_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_read_pipeline_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_read_pipeline_mode_5_qs) + ); + + // F[upload_5]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_upload_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_upload_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_upload_5_qs) + ); + + // F[busy_5]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_busy_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_busy_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_busy_5_qs) + ); + + // F[valid_5]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_5_valid_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_5_we), + .wd (cmd_info_5_valid_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[5].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_5_valid_5_qs) + ); + + + // Subregister 6 of Multireg cmd_info + // R[cmd_info_6]: V(False) + // F[opcode_6]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_6_opcode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_opcode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_opcode_6_qs) + ); + + // F[addr_mode_6]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_6_addr_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_addr_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_addr_mode_6_qs) + ); + + // F[addr_swap_en_6]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_addr_swap_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_addr_swap_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_addr_swap_en_6_qs) + ); + + // F[mbyte_en_6]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_mbyte_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_mbyte_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_mbyte_en_6_qs) + ); + + // F[dummy_size_6]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_6_dummy_size_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_dummy_size_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_dummy_size_6_qs) + ); + + // F[dummy_en_6]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_dummy_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_dummy_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_dummy_en_6_qs) + ); + + // F[payload_en_6]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_6_payload_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_payload_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_payload_en_6_qs) + ); + + // F[payload_dir_6]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_payload_dir_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_payload_dir_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_payload_dir_6_qs) + ); + + // F[payload_swap_en_6]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_payload_swap_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_payload_swap_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_payload_swap_en_6_qs) + ); + + // F[read_pipeline_mode_6]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_6_read_pipeline_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_read_pipeline_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_read_pipeline_mode_6_qs) + ); + + // F[upload_6]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_upload_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_upload_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_upload_6_qs) + ); + + // F[busy_6]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_busy_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_busy_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_busy_6_qs) + ); + + // F[valid_6]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_6_valid_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_6_we), + .wd (cmd_info_6_valid_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[6].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_6_valid_6_qs) + ); + + + // Subregister 7 of Multireg cmd_info + // R[cmd_info_7]: V(False) + // F[opcode_7]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_7_opcode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_opcode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_opcode_7_qs) + ); + + // F[addr_mode_7]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_7_addr_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_addr_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_addr_mode_7_qs) + ); + + // F[addr_swap_en_7]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_addr_swap_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_addr_swap_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_addr_swap_en_7_qs) + ); + + // F[mbyte_en_7]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_mbyte_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_mbyte_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_mbyte_en_7_qs) + ); + + // F[dummy_size_7]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_7_dummy_size_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_dummy_size_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_dummy_size_7_qs) + ); + + // F[dummy_en_7]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_dummy_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_dummy_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_dummy_en_7_qs) + ); + + // F[payload_en_7]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_7_payload_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_payload_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_payload_en_7_qs) + ); + + // F[payload_dir_7]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_payload_dir_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_payload_dir_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_payload_dir_7_qs) + ); + + // F[payload_swap_en_7]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_payload_swap_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_payload_swap_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_payload_swap_en_7_qs) + ); + + // F[read_pipeline_mode_7]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_7_read_pipeline_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_read_pipeline_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_read_pipeline_mode_7_qs) + ); + + // F[upload_7]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_upload_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_upload_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_upload_7_qs) + ); + + // F[busy_7]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_busy_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_busy_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_busy_7_qs) + ); + + // F[valid_7]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_7_valid_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_7_we), + .wd (cmd_info_7_valid_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[7].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_7_valid_7_qs) + ); + + + // Subregister 8 of Multireg cmd_info + // R[cmd_info_8]: V(False) + // F[opcode_8]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_8_opcode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_opcode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_opcode_8_qs) + ); + + // F[addr_mode_8]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_8_addr_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_addr_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_addr_mode_8_qs) + ); + + // F[addr_swap_en_8]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_addr_swap_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_addr_swap_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_addr_swap_en_8_qs) + ); + + // F[mbyte_en_8]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_mbyte_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_mbyte_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_mbyte_en_8_qs) + ); + + // F[dummy_size_8]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_8_dummy_size_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_dummy_size_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_dummy_size_8_qs) + ); + + // F[dummy_en_8]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_dummy_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_dummy_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_dummy_en_8_qs) + ); + + // F[payload_en_8]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_8_payload_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_payload_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_payload_en_8_qs) + ); + + // F[payload_dir_8]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_payload_dir_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_payload_dir_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_payload_dir_8_qs) + ); + + // F[payload_swap_en_8]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_payload_swap_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_payload_swap_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_payload_swap_en_8_qs) + ); + + // F[read_pipeline_mode_8]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_8_read_pipeline_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_read_pipeline_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_read_pipeline_mode_8_qs) + ); + + // F[upload_8]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_upload_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_upload_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_upload_8_qs) + ); + + // F[busy_8]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_busy_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_busy_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_busy_8_qs) + ); + + // F[valid_8]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_8_valid_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_8_we), + .wd (cmd_info_8_valid_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[8].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_8_valid_8_qs) + ); + + + // Subregister 9 of Multireg cmd_info + // R[cmd_info_9]: V(False) + // F[opcode_9]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_9_opcode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_opcode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_opcode_9_qs) + ); + + // F[addr_mode_9]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_9_addr_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_addr_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_addr_mode_9_qs) + ); + + // F[addr_swap_en_9]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_addr_swap_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_addr_swap_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_addr_swap_en_9_qs) + ); + + // F[mbyte_en_9]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_mbyte_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_mbyte_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_mbyte_en_9_qs) + ); + + // F[dummy_size_9]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_9_dummy_size_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_dummy_size_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_dummy_size_9_qs) + ); + + // F[dummy_en_9]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_dummy_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_dummy_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_dummy_en_9_qs) + ); + + // F[payload_en_9]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_9_payload_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_payload_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_payload_en_9_qs) + ); + + // F[payload_dir_9]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_payload_dir_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_payload_dir_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_payload_dir_9_qs) + ); + + // F[payload_swap_en_9]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_payload_swap_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_payload_swap_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_payload_swap_en_9_qs) + ); + + // F[read_pipeline_mode_9]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_9_read_pipeline_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_read_pipeline_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_read_pipeline_mode_9_qs) + ); + + // F[upload_9]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_upload_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_upload_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_upload_9_qs) + ); + + // F[busy_9]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_busy_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_busy_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_busy_9_qs) + ); + + // F[valid_9]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_9_valid_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_9_we), + .wd (cmd_info_9_valid_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[9].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_9_valid_9_qs) + ); + + + // Subregister 10 of Multireg cmd_info + // R[cmd_info_10]: V(False) + // F[opcode_10]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_10_opcode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_opcode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_opcode_10_qs) + ); + + // F[addr_mode_10]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_10_addr_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_addr_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_addr_mode_10_qs) + ); + + // F[addr_swap_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_addr_swap_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_addr_swap_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_addr_swap_en_10_qs) + ); + + // F[mbyte_en_10]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_mbyte_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_mbyte_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_mbyte_en_10_qs) + ); + + // F[dummy_size_10]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_10_dummy_size_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_dummy_size_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_dummy_size_10_qs) + ); + + // F[dummy_en_10]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_dummy_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_dummy_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_dummy_en_10_qs) + ); + + // F[payload_en_10]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_10_payload_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_payload_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_payload_en_10_qs) + ); + + // F[payload_dir_10]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_payload_dir_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_payload_dir_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_payload_dir_10_qs) + ); + + // F[payload_swap_en_10]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_payload_swap_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_payload_swap_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_payload_swap_en_10_qs) + ); + + // F[read_pipeline_mode_10]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_10_read_pipeline_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_read_pipeline_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_read_pipeline_mode_10_qs) + ); + + // F[upload_10]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_upload_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_upload_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_upload_10_qs) + ); + + // F[busy_10]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_busy_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_busy_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_busy_10_qs) + ); + + // F[valid_10]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_10_valid_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_10_we), + .wd (cmd_info_10_valid_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[10].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_10_valid_10_qs) + ); + + + // Subregister 11 of Multireg cmd_info + // R[cmd_info_11]: V(False) + // F[opcode_11]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_11_opcode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_opcode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_opcode_11_qs) + ); + + // F[addr_mode_11]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_11_addr_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_addr_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_addr_mode_11_qs) + ); + + // F[addr_swap_en_11]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_addr_swap_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_addr_swap_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_addr_swap_en_11_qs) + ); + + // F[mbyte_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_mbyte_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_mbyte_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_mbyte_en_11_qs) + ); + + // F[dummy_size_11]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_11_dummy_size_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_dummy_size_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_dummy_size_11_qs) + ); + + // F[dummy_en_11]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_dummy_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_dummy_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_dummy_en_11_qs) + ); + + // F[payload_en_11]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_11_payload_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_payload_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_payload_en_11_qs) + ); + + // F[payload_dir_11]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_payload_dir_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_payload_dir_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_payload_dir_11_qs) + ); + + // F[payload_swap_en_11]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_payload_swap_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_payload_swap_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_payload_swap_en_11_qs) + ); + + // F[read_pipeline_mode_11]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_11_read_pipeline_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_read_pipeline_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_read_pipeline_mode_11_qs) + ); + + // F[upload_11]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_upload_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_upload_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_upload_11_qs) + ); + + // F[busy_11]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_busy_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_busy_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_busy_11_qs) + ); + + // F[valid_11]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_11_valid_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_11_we), + .wd (cmd_info_11_valid_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[11].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_11_valid_11_qs) + ); + + + // Subregister 12 of Multireg cmd_info + // R[cmd_info_12]: V(False) + // F[opcode_12]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_12_opcode_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_opcode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_opcode_12_qs) + ); + + // F[addr_mode_12]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_12_addr_mode_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_addr_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_addr_mode_12_qs) + ); + + // F[addr_swap_en_12]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_addr_swap_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_addr_swap_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_addr_swap_en_12_qs) + ); + + // F[mbyte_en_12]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_mbyte_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_mbyte_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_mbyte_en_12_qs) + ); + + // F[dummy_size_12]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_12_dummy_size_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_dummy_size_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_dummy_size_12_qs) + ); + + // F[dummy_en_12]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_dummy_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_dummy_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_dummy_en_12_qs) + ); + + // F[payload_en_12]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_12_payload_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_payload_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_payload_en_12_qs) + ); + + // F[payload_dir_12]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_payload_dir_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_payload_dir_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_payload_dir_12_qs) + ); + + // F[payload_swap_en_12]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_payload_swap_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_payload_swap_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_payload_swap_en_12_qs) + ); + + // F[read_pipeline_mode_12]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_12_read_pipeline_mode_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_read_pipeline_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_read_pipeline_mode_12_qs) + ); + + // F[upload_12]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_upload_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_upload_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_upload_12_qs) + ); + + // F[busy_12]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_busy_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_busy_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_busy_12_qs) + ); + + // F[valid_12]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_12_valid_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_12_we), + .wd (cmd_info_12_valid_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[12].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_12_valid_12_qs) + ); + + + // Subregister 13 of Multireg cmd_info + // R[cmd_info_13]: V(False) + // F[opcode_13]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_13_opcode_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_opcode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_opcode_13_qs) + ); + + // F[addr_mode_13]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_13_addr_mode_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_addr_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_addr_mode_13_qs) + ); + + // F[addr_swap_en_13]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_addr_swap_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_addr_swap_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_addr_swap_en_13_qs) + ); + + // F[mbyte_en_13]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_mbyte_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_mbyte_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_mbyte_en_13_qs) + ); + + // F[dummy_size_13]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_13_dummy_size_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_dummy_size_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_dummy_size_13_qs) + ); + + // F[dummy_en_13]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_dummy_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_dummy_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_dummy_en_13_qs) + ); + + // F[payload_en_13]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_13_payload_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_payload_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_payload_en_13_qs) + ); + + // F[payload_dir_13]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_payload_dir_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_payload_dir_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_payload_dir_13_qs) + ); + + // F[payload_swap_en_13]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_payload_swap_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_payload_swap_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_payload_swap_en_13_qs) + ); + + // F[read_pipeline_mode_13]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_13_read_pipeline_mode_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_read_pipeline_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_read_pipeline_mode_13_qs) + ); + + // F[upload_13]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_upload_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_upload_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_upload_13_qs) + ); + + // F[busy_13]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_busy_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_busy_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_busy_13_qs) + ); + + // F[valid_13]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_13_valid_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_13_we), + .wd (cmd_info_13_valid_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[13].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_13_valid_13_qs) + ); + + + // Subregister 14 of Multireg cmd_info + // R[cmd_info_14]: V(False) + // F[opcode_14]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_14_opcode_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_opcode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_opcode_14_qs) + ); + + // F[addr_mode_14]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_14_addr_mode_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_addr_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_addr_mode_14_qs) + ); + + // F[addr_swap_en_14]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_addr_swap_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_addr_swap_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_addr_swap_en_14_qs) + ); + + // F[mbyte_en_14]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_mbyte_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_mbyte_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_mbyte_en_14_qs) + ); + + // F[dummy_size_14]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_14_dummy_size_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_dummy_size_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_dummy_size_14_qs) + ); + + // F[dummy_en_14]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_dummy_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_dummy_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_dummy_en_14_qs) + ); + + // F[payload_en_14]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_14_payload_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_payload_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_payload_en_14_qs) + ); + + // F[payload_dir_14]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_payload_dir_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_payload_dir_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_payload_dir_14_qs) + ); + + // F[payload_swap_en_14]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_payload_swap_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_payload_swap_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_payload_swap_en_14_qs) + ); + + // F[read_pipeline_mode_14]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_14_read_pipeline_mode_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_read_pipeline_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_read_pipeline_mode_14_qs) + ); + + // F[upload_14]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_upload_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_upload_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_upload_14_qs) + ); + + // F[busy_14]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_busy_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_busy_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_busy_14_qs) + ); + + // F[valid_14]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_14_valid_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_14_we), + .wd (cmd_info_14_valid_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[14].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_14_valid_14_qs) + ); + + + // Subregister 15 of Multireg cmd_info + // R[cmd_info_15]: V(False) + // F[opcode_15]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_15_opcode_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_opcode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_opcode_15_qs) + ); + + // F[addr_mode_15]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_15_addr_mode_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_addr_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_addr_mode_15_qs) + ); + + // F[addr_swap_en_15]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_addr_swap_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_addr_swap_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_addr_swap_en_15_qs) + ); + + // F[mbyte_en_15]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_mbyte_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_mbyte_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_mbyte_en_15_qs) + ); + + // F[dummy_size_15]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_15_dummy_size_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_dummy_size_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_dummy_size_15_qs) + ); + + // F[dummy_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_dummy_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_dummy_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_dummy_en_15_qs) + ); + + // F[payload_en_15]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_15_payload_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_payload_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_payload_en_15_qs) + ); + + // F[payload_dir_15]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_payload_dir_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_payload_dir_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_payload_dir_15_qs) + ); + + // F[payload_swap_en_15]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_payload_swap_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_payload_swap_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_payload_swap_en_15_qs) + ); + + // F[read_pipeline_mode_15]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_15_read_pipeline_mode_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_read_pipeline_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_read_pipeline_mode_15_qs) + ); + + // F[upload_15]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_upload_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_upload_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_upload_15_qs) + ); + + // F[busy_15]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_busy_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_busy_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_busy_15_qs) + ); + + // F[valid_15]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_15_valid_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_15_we), + .wd (cmd_info_15_valid_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[15].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_15_valid_15_qs) + ); + + + // Subregister 16 of Multireg cmd_info + // R[cmd_info_16]: V(False) + // F[opcode_16]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_16_opcode_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_opcode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_opcode_16_qs) + ); + + // F[addr_mode_16]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_16_addr_mode_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_addr_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_addr_mode_16_qs) + ); + + // F[addr_swap_en_16]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_addr_swap_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_addr_swap_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_addr_swap_en_16_qs) + ); + + // F[mbyte_en_16]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_mbyte_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_mbyte_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_mbyte_en_16_qs) + ); + + // F[dummy_size_16]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_16_dummy_size_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_dummy_size_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_dummy_size_16_qs) + ); + + // F[dummy_en_16]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_dummy_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_dummy_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_dummy_en_16_qs) + ); + + // F[payload_en_16]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_16_payload_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_payload_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_payload_en_16_qs) + ); + + // F[payload_dir_16]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_payload_dir_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_payload_dir_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_payload_dir_16_qs) + ); + + // F[payload_swap_en_16]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_payload_swap_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_payload_swap_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_payload_swap_en_16_qs) + ); + + // F[read_pipeline_mode_16]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_16_read_pipeline_mode_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_read_pipeline_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_read_pipeline_mode_16_qs) + ); + + // F[upload_16]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_upload_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_upload_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_upload_16_qs) + ); + + // F[busy_16]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_busy_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_busy_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_busy_16_qs) + ); + + // F[valid_16]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_16_valid_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_16_we), + .wd (cmd_info_16_valid_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[16].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_16_valid_16_qs) + ); + + + // Subregister 17 of Multireg cmd_info + // R[cmd_info_17]: V(False) + // F[opcode_17]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_17_opcode_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_opcode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_opcode_17_qs) + ); + + // F[addr_mode_17]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_17_addr_mode_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_addr_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_addr_mode_17_qs) + ); + + // F[addr_swap_en_17]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_addr_swap_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_addr_swap_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_addr_swap_en_17_qs) + ); + + // F[mbyte_en_17]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_mbyte_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_mbyte_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_mbyte_en_17_qs) + ); + + // F[dummy_size_17]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_17_dummy_size_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_dummy_size_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_dummy_size_17_qs) + ); + + // F[dummy_en_17]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_dummy_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_dummy_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_dummy_en_17_qs) + ); + + // F[payload_en_17]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_17_payload_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_payload_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_payload_en_17_qs) + ); + + // F[payload_dir_17]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_payload_dir_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_payload_dir_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_payload_dir_17_qs) + ); + + // F[payload_swap_en_17]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_payload_swap_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_payload_swap_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_payload_swap_en_17_qs) + ); + + // F[read_pipeline_mode_17]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_17_read_pipeline_mode_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_read_pipeline_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_read_pipeline_mode_17_qs) + ); + + // F[upload_17]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_upload_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_upload_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_upload_17_qs) + ); + + // F[busy_17]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_busy_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_busy_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_busy_17_qs) + ); + + // F[valid_17]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_17_valid_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_17_we), + .wd (cmd_info_17_valid_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[17].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_17_valid_17_qs) + ); + + + // Subregister 18 of Multireg cmd_info + // R[cmd_info_18]: V(False) + // F[opcode_18]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_18_opcode_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_opcode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_opcode_18_qs) + ); + + // F[addr_mode_18]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_18_addr_mode_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_addr_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_addr_mode_18_qs) + ); + + // F[addr_swap_en_18]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_addr_swap_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_addr_swap_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_addr_swap_en_18_qs) + ); + + // F[mbyte_en_18]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_mbyte_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_mbyte_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_mbyte_en_18_qs) + ); + + // F[dummy_size_18]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_18_dummy_size_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_dummy_size_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_dummy_size_18_qs) + ); + + // F[dummy_en_18]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_dummy_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_dummy_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_dummy_en_18_qs) + ); + + // F[payload_en_18]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_18_payload_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_payload_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_payload_en_18_qs) + ); + + // F[payload_dir_18]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_payload_dir_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_payload_dir_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_payload_dir_18_qs) + ); + + // F[payload_swap_en_18]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_payload_swap_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_payload_swap_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_payload_swap_en_18_qs) + ); + + // F[read_pipeline_mode_18]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_18_read_pipeline_mode_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_read_pipeline_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_read_pipeline_mode_18_qs) + ); + + // F[upload_18]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_upload_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_upload_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_upload_18_qs) + ); + + // F[busy_18]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_busy_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_busy_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_busy_18_qs) + ); + + // F[valid_18]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_18_valid_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_18_we), + .wd (cmd_info_18_valid_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[18].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_18_valid_18_qs) + ); + + + // Subregister 19 of Multireg cmd_info + // R[cmd_info_19]: V(False) + // F[opcode_19]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_19_opcode_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_opcode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_opcode_19_qs) + ); + + // F[addr_mode_19]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_19_addr_mode_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_addr_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_addr_mode_19_qs) + ); + + // F[addr_swap_en_19]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_addr_swap_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_addr_swap_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_addr_swap_en_19_qs) + ); + + // F[mbyte_en_19]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_mbyte_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_mbyte_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_mbyte_en_19_qs) + ); + + // F[dummy_size_19]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_19_dummy_size_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_dummy_size_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_dummy_size_19_qs) + ); + + // F[dummy_en_19]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_dummy_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_dummy_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_dummy_en_19_qs) + ); + + // F[payload_en_19]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_19_payload_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_payload_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_payload_en_19_qs) + ); + + // F[payload_dir_19]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_payload_dir_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_payload_dir_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_payload_dir_19_qs) + ); + + // F[payload_swap_en_19]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_payload_swap_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_payload_swap_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_payload_swap_en_19_qs) + ); + + // F[read_pipeline_mode_19]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_19_read_pipeline_mode_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_read_pipeline_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_read_pipeline_mode_19_qs) + ); + + // F[upload_19]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_upload_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_upload_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_upload_19_qs) + ); + + // F[busy_19]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_busy_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_busy_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_busy_19_qs) + ); + + // F[valid_19]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_19_valid_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_19_we), + .wd (cmd_info_19_valid_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[19].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_19_valid_19_qs) + ); + + + // Subregister 20 of Multireg cmd_info + // R[cmd_info_20]: V(False) + // F[opcode_20]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_20_opcode_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_opcode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_opcode_20_qs) + ); + + // F[addr_mode_20]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_20_addr_mode_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_addr_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_addr_mode_20_qs) + ); + + // F[addr_swap_en_20]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_addr_swap_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_addr_swap_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_addr_swap_en_20_qs) + ); + + // F[mbyte_en_20]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_mbyte_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_mbyte_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_mbyte_en_20_qs) + ); + + // F[dummy_size_20]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_20_dummy_size_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_dummy_size_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_dummy_size_20_qs) + ); + + // F[dummy_en_20]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_dummy_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_dummy_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_dummy_en_20_qs) + ); + + // F[payload_en_20]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_20_payload_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_payload_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_payload_en_20_qs) + ); + + // F[payload_dir_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_payload_dir_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_payload_dir_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_payload_dir_20_qs) + ); + + // F[payload_swap_en_20]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_payload_swap_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_payload_swap_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_payload_swap_en_20_qs) + ); + + // F[read_pipeline_mode_20]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_20_read_pipeline_mode_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_read_pipeline_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_read_pipeline_mode_20_qs) + ); + + // F[upload_20]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_upload_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_upload_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_upload_20_qs) + ); + + // F[busy_20]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_busy_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_busy_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_busy_20_qs) + ); + + // F[valid_20]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_20_valid_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_20_we), + .wd (cmd_info_20_valid_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[20].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_20_valid_20_qs) + ); + + + // Subregister 21 of Multireg cmd_info + // R[cmd_info_21]: V(False) + // F[opcode_21]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_21_opcode_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_opcode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_opcode_21_qs) + ); + + // F[addr_mode_21]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_21_addr_mode_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_addr_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_addr_mode_21_qs) + ); + + // F[addr_swap_en_21]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_addr_swap_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_addr_swap_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_addr_swap_en_21_qs) + ); + + // F[mbyte_en_21]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_mbyte_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_mbyte_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_mbyte_en_21_qs) + ); + + // F[dummy_size_21]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_21_dummy_size_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_dummy_size_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_dummy_size_21_qs) + ); + + // F[dummy_en_21]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_dummy_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_dummy_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_dummy_en_21_qs) + ); + + // F[payload_en_21]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_21_payload_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_payload_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_payload_en_21_qs) + ); + + // F[payload_dir_21]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_payload_dir_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_payload_dir_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_payload_dir_21_qs) + ); + + // F[payload_swap_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_payload_swap_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_payload_swap_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_payload_swap_en_21_qs) + ); + + // F[read_pipeline_mode_21]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_21_read_pipeline_mode_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_read_pipeline_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_read_pipeline_mode_21_qs) + ); + + // F[upload_21]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_upload_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_upload_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_upload_21_qs) + ); + + // F[busy_21]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_busy_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_busy_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_busy_21_qs) + ); + + // F[valid_21]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_21_valid_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_21_we), + .wd (cmd_info_21_valid_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[21].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_21_valid_21_qs) + ); + + + // Subregister 22 of Multireg cmd_info + // R[cmd_info_22]: V(False) + // F[opcode_22]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_22_opcode_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_opcode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_opcode_22_qs) + ); + + // F[addr_mode_22]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_22_addr_mode_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_addr_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_addr_mode_22_qs) + ); + + // F[addr_swap_en_22]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_addr_swap_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_addr_swap_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_addr_swap_en_22_qs) + ); + + // F[mbyte_en_22]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_mbyte_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_mbyte_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_mbyte_en_22_qs) + ); + + // F[dummy_size_22]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_22_dummy_size_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_dummy_size_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_dummy_size_22_qs) + ); + + // F[dummy_en_22]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_dummy_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_dummy_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_dummy_en_22_qs) + ); + + // F[payload_en_22]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_22_payload_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_payload_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_payload_en_22_qs) + ); + + // F[payload_dir_22]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_payload_dir_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_payload_dir_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_payload_dir_22_qs) + ); + + // F[payload_swap_en_22]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_payload_swap_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_payload_swap_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_payload_swap_en_22_qs) + ); + + // F[read_pipeline_mode_22]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_22_read_pipeline_mode_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_read_pipeline_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_read_pipeline_mode_22_qs) + ); + + // F[upload_22]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_upload_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_upload_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_upload_22_qs) + ); + + // F[busy_22]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_busy_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_busy_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_busy_22_qs) + ); + + // F[valid_22]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_22_valid_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_22_we), + .wd (cmd_info_22_valid_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[22].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_22_valid_22_qs) + ); + + + // Subregister 23 of Multireg cmd_info + // R[cmd_info_23]: V(False) + // F[opcode_23]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_23_opcode_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_opcode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_opcode_23_qs) + ); + + // F[addr_mode_23]: 9:8 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_23_addr_mode_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_addr_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].addr_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_addr_mode_23_qs) + ); + + // F[addr_swap_en_23]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_addr_swap_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_addr_swap_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].addr_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_addr_swap_en_23_qs) + ); + + // F[mbyte_en_23]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_mbyte_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_mbyte_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].mbyte_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_mbyte_en_23_qs) + ); + + // F[dummy_size_23]: 14:12 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h7), + .Mubi (1'b0) + ) u_cmd_info_23_dummy_size_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_dummy_size_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].dummy_size.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_dummy_size_23_qs) + ); + + // F[dummy_en_23]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_dummy_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_dummy_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].dummy_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_dummy_en_23_qs) + ); + + // F[payload_en_23]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cmd_info_23_payload_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_payload_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].payload_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_payload_en_23_qs) + ); + + // F[payload_dir_23]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_payload_dir_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_payload_dir_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].payload_dir.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_payload_dir_23_qs) + ); + + // F[payload_swap_en_23]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_payload_swap_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_payload_swap_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].payload_swap_en.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_payload_swap_en_23_qs) + ); + + // F[read_pipeline_mode_23]: 23:22 + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_cmd_info_23_read_pipeline_mode_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_read_pipeline_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].read_pipeline_mode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_read_pipeline_mode_23_qs) + ); + + // F[upload_23]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_upload_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_upload_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].upload.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_upload_23_qs) + ); + + // F[busy_23]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_busy_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_busy_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].busy.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_busy_23_qs) + ); + + // F[valid_23]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_23_valid_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_23_we), + .wd (cmd_info_23_valid_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info[23].valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_23_valid_23_qs) + ); + + + // R[cmd_info_en4b]: V(False) + // F[opcode]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_en4b_opcode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_en4b_we), + .wd (cmd_info_en4b_opcode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_en4b.opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_en4b_opcode_qs) + ); + + // F[valid]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_en4b_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_en4b_we), + .wd (cmd_info_en4b_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_en4b.valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_en4b_valid_qs) + ); + + + // R[cmd_info_ex4b]: V(False) + // F[opcode]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_ex4b_opcode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_ex4b_we), + .wd (cmd_info_ex4b_opcode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_ex4b.opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_ex4b_opcode_qs) + ); + + // F[valid]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_ex4b_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_ex4b_we), + .wd (cmd_info_ex4b_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_ex4b.valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_ex4b_valid_qs) + ); + + + // R[cmd_info_wren]: V(False) + // F[opcode]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_wren_opcode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_wren_we), + .wd (cmd_info_wren_opcode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_wren.opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_wren_opcode_qs) + ); + + // F[valid]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_wren_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_wren_we), + .wd (cmd_info_wren_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_wren.valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_wren_valid_qs) + ); + + + // R[cmd_info_wrdi]: V(False) + // F[opcode]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_cmd_info_wrdi_opcode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_wrdi_we), + .wd (cmd_info_wrdi_opcode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_wrdi.opcode.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_wrdi_opcode_qs) + ); + + // F[valid]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cmd_info_wrdi_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cmd_info_wrdi_we), + .wd (cmd_info_wrdi_valid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cmd_info_wrdi.valid.q), + .ds (), + + // to register interface (read) + .qs (cmd_info_wrdi_valid_qs) + ); + + + // R[tpm_cap]: V(False) + // F[rev]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_cap_rev ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.tpm_cap.rev.de), + .d (hw2reg.tpm_cap.rev.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (tpm_cap_rev_qs) + ); + + // F[locality]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_tpm_cap_locality ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.tpm_cap.locality.de), + .d (hw2reg.tpm_cap.locality.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (tpm_cap_locality_qs) + ); + + // F[max_wr_size]: 18:16 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (3'h6), + .Mubi (1'b0) + ) u_tpm_cap_max_wr_size ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.tpm_cap.max_wr_size.de), + .d (hw2reg.tpm_cap.max_wr_size.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (tpm_cap_max_wr_size_qs) + ); + + // F[max_rd_size]: 22:20 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (3'h6), + .Mubi (1'b0) + ) u_tpm_cap_max_rd_size ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.tpm_cap.max_rd_size.de), + .d (hw2reg.tpm_cap.max_rd_size.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (tpm_cap_max_rd_size_qs) + ); + + + // R[tpm_cfg]: V(False) + // F[en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_tpm_cfg_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_cfg_we), + .wd (tpm_cfg_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_cfg.en.q), + .ds (), + + // to register interface (read) + .qs (tpm_cfg_en_qs) + ); + + // F[tpm_mode]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_tpm_cfg_tpm_mode ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_cfg_we), + .wd (tpm_cfg_tpm_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_cfg.tpm_mode.q), + .ds (), + + // to register interface (read) + .qs (tpm_cfg_tpm_mode_qs) + ); + + // F[hw_reg_dis]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_tpm_cfg_hw_reg_dis ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_cfg_we), + .wd (tpm_cfg_hw_reg_dis_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_cfg.hw_reg_dis.q), + .ds (), + + // to register interface (read) + .qs (tpm_cfg_hw_reg_dis_qs) + ); + + // F[tpm_reg_chk_dis]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_tpm_cfg_tpm_reg_chk_dis ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_cfg_we), + .wd (tpm_cfg_tpm_reg_chk_dis_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_cfg.tpm_reg_chk_dis.q), + .ds (), + + // to register interface (read) + .qs (tpm_cfg_tpm_reg_chk_dis_qs) + ); + + // F[invalid_locality]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_tpm_cfg_invalid_locality ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_cfg_we), + .wd (tpm_cfg_invalid_locality_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_cfg.invalid_locality.q), + .ds (), + + // to register interface (read) + .qs (tpm_cfg_invalid_locality_qs) + ); + + + // R[tpm_status]: V(True) + logic tpm_status_qe; + logic [2:0] tpm_status_flds_we; + // This ignores QEs that are set to constant 0 due to read-only fields. + logic unused_tpm_status_flds_we; + assign unused_tpm_status_flds_we = ^(tpm_status_flds_we & 3'h5); + assign tpm_status_qe = &(tpm_status_flds_we | 3'h5); + // F[cmdaddr_notempty]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_tpm_status_cmdaddr_notempty ( + .re (tpm_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tpm_status.cmdaddr_notempty.d), + .qre (), + .qe (tpm_status_flds_we[0]), + .q (), + .ds (), + .qs (tpm_status_cmdaddr_notempty_qs) + ); + + // F[wrfifo_pending]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_tpm_status_wrfifo_pending ( + .re (tpm_status_re), + .we (tpm_status_we), + .wd (tpm_status_wrfifo_pending_wd), + .d (hw2reg.tpm_status.wrfifo_pending.d), + .qre (), + .qe (tpm_status_flds_we[1]), + .q (reg2hw.tpm_status.wrfifo_pending.q), + .ds (), + .qs (tpm_status_wrfifo_pending_qs) + ); + assign reg2hw.tpm_status.wrfifo_pending.qe = tpm_status_qe; + + // F[rdfifo_aborted]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_tpm_status_rdfifo_aborted ( + .re (tpm_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tpm_status.rdfifo_aborted.d), + .qre (), + .qe (tpm_status_flds_we[2]), + .q (), + .ds (), + .qs (tpm_status_rdfifo_aborted_qs) + ); + + + // R[tpm_access_0]: V(False) + // F[access_0]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_access_0_access_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_access_0_we), + .wd (tpm_access_0_access_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_access_0[0].q), + .ds (), + + // to register interface (read) + .qs (tpm_access_0_access_0_qs) + ); + + // F[access_1]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_access_0_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_access_0_we), + .wd (tpm_access_0_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_access_0[1].q), + .ds (), + + // to register interface (read) + .qs (tpm_access_0_access_1_qs) + ); + + // F[access_2]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_access_0_access_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_access_0_we), + .wd (tpm_access_0_access_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_access_0[2].q), + .ds (), + + // to register interface (read) + .qs (tpm_access_0_access_2_qs) + ); + + // F[access_3]: 31:24 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_access_0_access_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_access_0_we), + .wd (tpm_access_0_access_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_access_0[3].q), + .ds (), + + // to register interface (read) + .qs (tpm_access_0_access_3_qs) + ); + + + // R[tpm_access_1]: V(False) + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_access_1_we), + .wd (tpm_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_access_1.q), + .ds (), + + // to register interface (read) + .qs (tpm_access_1_qs) + ); + + + // R[tpm_sts]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_tpm_sts ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_sts_we), + .wd (tpm_sts_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_sts.q), + .ds (), + + // to register interface (read) + .qs (tpm_sts_qs) + ); + + + // R[tpm_intf_capability]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_tpm_intf_capability ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_intf_capability_we), + .wd (tpm_intf_capability_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_intf_capability.q), + .ds (), + + // to register interface (read) + .qs (tpm_intf_capability_qs) + ); + + + // R[tpm_int_enable]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_tpm_int_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_int_enable_we), + .wd (tpm_int_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_int_enable.q), + .ds (), + + // to register interface (read) + .qs (tpm_int_enable_qs) + ); + + + // R[tpm_int_vector]: V(False) + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_int_vector ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_int_vector_we), + .wd (tpm_int_vector_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_int_vector.q), + .ds (), + + // to register interface (read) + .qs (tpm_int_vector_qs) + ); + + + // R[tpm_int_status]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_tpm_int_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_int_status_we), + .wd (tpm_int_status_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_int_status.q), + .ds (), + + // to register interface (read) + .qs (tpm_int_status_qs) + ); + + + // R[tpm_did_vid]: V(False) + // F[vid]: 15:0 + prim_subreg #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_tpm_did_vid_vid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_did_vid_we), + .wd (tpm_did_vid_vid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_did_vid.vid.q), + .ds (), + + // to register interface (read) + .qs (tpm_did_vid_vid_qs) + ); + + // F[did]: 31:16 + prim_subreg #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_tpm_did_vid_did ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_did_vid_we), + .wd (tpm_did_vid_did_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_did_vid.did.q), + .ds (), + + // to register interface (read) + .qs (tpm_did_vid_did_qs) + ); + + + // R[tpm_rid]: V(False) + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_tpm_rid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (tpm_rid_we), + .wd (tpm_rid_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.tpm_rid.q), + .ds (), + + // to register interface (read) + .qs (tpm_rid_qs) + ); + + + // R[tpm_cmd_addr]: V(True) + logic tpm_cmd_addr_qe; + logic [1:0] tpm_cmd_addr_flds_we; + // In case all fields are read-only the aggregated register QE will be zero as well. + assign tpm_cmd_addr_qe = &tpm_cmd_addr_flds_we; + // F[addr]: 23:0 + prim_subreg_ext #( + .DW (24) + ) u_tpm_cmd_addr_addr ( + .re (tpm_cmd_addr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tpm_cmd_addr.addr.d), + .qre (reg2hw.tpm_cmd_addr.addr.re), + .qe (tpm_cmd_addr_flds_we[0]), + .q (reg2hw.tpm_cmd_addr.addr.q), + .ds (), + .qs (tpm_cmd_addr_addr_qs) + ); + assign reg2hw.tpm_cmd_addr.addr.qe = tpm_cmd_addr_qe; + + // F[cmd]: 31:24 + prim_subreg_ext #( + .DW (8) + ) u_tpm_cmd_addr_cmd ( + .re (tpm_cmd_addr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tpm_cmd_addr.cmd.d), + .qre (reg2hw.tpm_cmd_addr.cmd.re), + .qe (tpm_cmd_addr_flds_we[1]), + .q (reg2hw.tpm_cmd_addr.cmd.q), + .ds (), + .qs (tpm_cmd_addr_cmd_qs) + ); + assign reg2hw.tpm_cmd_addr.cmd.qe = tpm_cmd_addr_qe; + + + // R[tpm_read_fifo]: V(True) + logic tpm_read_fifo_qe; + logic [0:0] tpm_read_fifo_flds_we; + assign tpm_read_fifo_qe = &tpm_read_fifo_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_tpm_read_fifo ( + .re (1'b0), + .we (tpm_read_fifo_we), + .wd (tpm_read_fifo_wd), + .d ('0), + .qre (), + .qe (tpm_read_fifo_flds_we[0]), + .q (reg2hw.tpm_read_fifo.q), + .ds (), + .qs () + ); + assign reg2hw.tpm_read_fifo.qe = tpm_read_fifo_qe; + + + + logic [72:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [72:0] racl_addr_hit_read; + logic [72:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == SPI_DEVICE_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == SPI_DEVICE_CFG_OFFSET); + addr_hit[ 6] = (reg_addr == SPI_DEVICE_STATUS_OFFSET); + addr_hit[ 7] = (reg_addr == SPI_DEVICE_INTERCEPT_EN_OFFSET); + addr_hit[ 8] = (reg_addr == SPI_DEVICE_ADDR_MODE_OFFSET); + addr_hit[ 9] = (reg_addr == SPI_DEVICE_LAST_READ_ADDR_OFFSET); + addr_hit[10] = (reg_addr == SPI_DEVICE_FLASH_STATUS_OFFSET); + addr_hit[11] = (reg_addr == SPI_DEVICE_JEDEC_CC_OFFSET); + addr_hit[12] = (reg_addr == SPI_DEVICE_JEDEC_ID_OFFSET); + addr_hit[13] = (reg_addr == SPI_DEVICE_READ_THRESHOLD_OFFSET); + addr_hit[14] = (reg_addr == SPI_DEVICE_MAILBOX_ADDR_OFFSET); + addr_hit[15] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS_OFFSET); + addr_hit[16] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS2_OFFSET); + addr_hit[17] = (reg_addr == SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET); + addr_hit[18] = (reg_addr == SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET); + addr_hit[19] = (reg_addr == SPI_DEVICE_CMD_FILTER_0_OFFSET); + addr_hit[20] = (reg_addr == SPI_DEVICE_CMD_FILTER_1_OFFSET); + addr_hit[21] = (reg_addr == SPI_DEVICE_CMD_FILTER_2_OFFSET); + addr_hit[22] = (reg_addr == SPI_DEVICE_CMD_FILTER_3_OFFSET); + addr_hit[23] = (reg_addr == SPI_DEVICE_CMD_FILTER_4_OFFSET); + addr_hit[24] = (reg_addr == SPI_DEVICE_CMD_FILTER_5_OFFSET); + addr_hit[25] = (reg_addr == SPI_DEVICE_CMD_FILTER_6_OFFSET); + addr_hit[26] = (reg_addr == SPI_DEVICE_CMD_FILTER_7_OFFSET); + addr_hit[27] = (reg_addr == SPI_DEVICE_ADDR_SWAP_MASK_OFFSET); + addr_hit[28] = (reg_addr == SPI_DEVICE_ADDR_SWAP_DATA_OFFSET); + addr_hit[29] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_MASK_OFFSET); + addr_hit[30] = (reg_addr == SPI_DEVICE_PAYLOAD_SWAP_DATA_OFFSET); + addr_hit[31] = (reg_addr == SPI_DEVICE_CMD_INFO_0_OFFSET); + addr_hit[32] = (reg_addr == SPI_DEVICE_CMD_INFO_1_OFFSET); + addr_hit[33] = (reg_addr == SPI_DEVICE_CMD_INFO_2_OFFSET); + addr_hit[34] = (reg_addr == SPI_DEVICE_CMD_INFO_3_OFFSET); + addr_hit[35] = (reg_addr == SPI_DEVICE_CMD_INFO_4_OFFSET); + addr_hit[36] = (reg_addr == SPI_DEVICE_CMD_INFO_5_OFFSET); + addr_hit[37] = (reg_addr == SPI_DEVICE_CMD_INFO_6_OFFSET); + addr_hit[38] = (reg_addr == SPI_DEVICE_CMD_INFO_7_OFFSET); + addr_hit[39] = (reg_addr == SPI_DEVICE_CMD_INFO_8_OFFSET); + addr_hit[40] = (reg_addr == SPI_DEVICE_CMD_INFO_9_OFFSET); + addr_hit[41] = (reg_addr == SPI_DEVICE_CMD_INFO_10_OFFSET); + addr_hit[42] = (reg_addr == SPI_DEVICE_CMD_INFO_11_OFFSET); + addr_hit[43] = (reg_addr == SPI_DEVICE_CMD_INFO_12_OFFSET); + addr_hit[44] = (reg_addr == SPI_DEVICE_CMD_INFO_13_OFFSET); + addr_hit[45] = (reg_addr == SPI_DEVICE_CMD_INFO_14_OFFSET); + addr_hit[46] = (reg_addr == SPI_DEVICE_CMD_INFO_15_OFFSET); + addr_hit[47] = (reg_addr == SPI_DEVICE_CMD_INFO_16_OFFSET); + addr_hit[48] = (reg_addr == SPI_DEVICE_CMD_INFO_17_OFFSET); + addr_hit[49] = (reg_addr == SPI_DEVICE_CMD_INFO_18_OFFSET); + addr_hit[50] = (reg_addr == SPI_DEVICE_CMD_INFO_19_OFFSET); + addr_hit[51] = (reg_addr == SPI_DEVICE_CMD_INFO_20_OFFSET); + addr_hit[52] = (reg_addr == SPI_DEVICE_CMD_INFO_21_OFFSET); + addr_hit[53] = (reg_addr == SPI_DEVICE_CMD_INFO_22_OFFSET); + addr_hit[54] = (reg_addr == SPI_DEVICE_CMD_INFO_23_OFFSET); + addr_hit[55] = (reg_addr == SPI_DEVICE_CMD_INFO_EN4B_OFFSET); + addr_hit[56] = (reg_addr == SPI_DEVICE_CMD_INFO_EX4B_OFFSET); + addr_hit[57] = (reg_addr == SPI_DEVICE_CMD_INFO_WREN_OFFSET); + addr_hit[58] = (reg_addr == SPI_DEVICE_CMD_INFO_WRDI_OFFSET); + addr_hit[59] = (reg_addr == SPI_DEVICE_TPM_CAP_OFFSET); + addr_hit[60] = (reg_addr == SPI_DEVICE_TPM_CFG_OFFSET); + addr_hit[61] = (reg_addr == SPI_DEVICE_TPM_STATUS_OFFSET); + addr_hit[62] = (reg_addr == SPI_DEVICE_TPM_ACCESS_0_OFFSET); + addr_hit[63] = (reg_addr == SPI_DEVICE_TPM_ACCESS_1_OFFSET); + addr_hit[64] = (reg_addr == SPI_DEVICE_TPM_STS_OFFSET); + addr_hit[65] = (reg_addr == SPI_DEVICE_TPM_INTF_CAPABILITY_OFFSET); + addr_hit[66] = (reg_addr == SPI_DEVICE_TPM_INT_ENABLE_OFFSET); + addr_hit[67] = (reg_addr == SPI_DEVICE_TPM_INT_VECTOR_OFFSET); + addr_hit[68] = (reg_addr == SPI_DEVICE_TPM_INT_STATUS_OFFSET); + addr_hit[69] = (reg_addr == SPI_DEVICE_TPM_DID_VID_OFFSET); + addr_hit[70] = (reg_addr == SPI_DEVICE_TPM_RID_OFFSET); + addr_hit[71] = (reg_addr == SPI_DEVICE_TPM_CMD_ADDR_OFFSET); + addr_hit[72] = (reg_addr == SPI_DEVICE_TPM_READ_FIFO_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 73; slice_idx++) begin + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[ 0] & (|(SPI_DEVICE_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(SPI_DEVICE_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(SPI_DEVICE_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(SPI_DEVICE_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(SPI_DEVICE_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(SPI_DEVICE_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(SPI_DEVICE_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(SPI_DEVICE_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(SPI_DEVICE_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(SPI_DEVICE_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[10] & (|(SPI_DEVICE_PERMIT[10] & ~reg_be))) | + (racl_addr_hit_write[11] & (|(SPI_DEVICE_PERMIT[11] & ~reg_be))) | + (racl_addr_hit_write[12] & (|(SPI_DEVICE_PERMIT[12] & ~reg_be))) | + (racl_addr_hit_write[13] & (|(SPI_DEVICE_PERMIT[13] & ~reg_be))) | + (racl_addr_hit_write[14] & (|(SPI_DEVICE_PERMIT[14] & ~reg_be))) | + (racl_addr_hit_write[15] & (|(SPI_DEVICE_PERMIT[15] & ~reg_be))) | + (racl_addr_hit_write[16] & (|(SPI_DEVICE_PERMIT[16] & ~reg_be))) | + (racl_addr_hit_write[17] & (|(SPI_DEVICE_PERMIT[17] & ~reg_be))) | + (racl_addr_hit_write[18] & (|(SPI_DEVICE_PERMIT[18] & ~reg_be))) | + (racl_addr_hit_write[19] & (|(SPI_DEVICE_PERMIT[19] & ~reg_be))) | + (racl_addr_hit_write[20] & (|(SPI_DEVICE_PERMIT[20] & ~reg_be))) | + (racl_addr_hit_write[21] & (|(SPI_DEVICE_PERMIT[21] & ~reg_be))) | + (racl_addr_hit_write[22] & (|(SPI_DEVICE_PERMIT[22] & ~reg_be))) | + (racl_addr_hit_write[23] & (|(SPI_DEVICE_PERMIT[23] & ~reg_be))) | + (racl_addr_hit_write[24] & (|(SPI_DEVICE_PERMIT[24] & ~reg_be))) | + (racl_addr_hit_write[25] & (|(SPI_DEVICE_PERMIT[25] & ~reg_be))) | + (racl_addr_hit_write[26] & (|(SPI_DEVICE_PERMIT[26] & ~reg_be))) | + (racl_addr_hit_write[27] & (|(SPI_DEVICE_PERMIT[27] & ~reg_be))) | + (racl_addr_hit_write[28] & (|(SPI_DEVICE_PERMIT[28] & ~reg_be))) | + (racl_addr_hit_write[29] & (|(SPI_DEVICE_PERMIT[29] & ~reg_be))) | + (racl_addr_hit_write[30] & (|(SPI_DEVICE_PERMIT[30] & ~reg_be))) | + (racl_addr_hit_write[31] & (|(SPI_DEVICE_PERMIT[31] & ~reg_be))) | + (racl_addr_hit_write[32] & (|(SPI_DEVICE_PERMIT[32] & ~reg_be))) | + (racl_addr_hit_write[33] & (|(SPI_DEVICE_PERMIT[33] & ~reg_be))) | + (racl_addr_hit_write[34] & (|(SPI_DEVICE_PERMIT[34] & ~reg_be))) | + (racl_addr_hit_write[35] & (|(SPI_DEVICE_PERMIT[35] & ~reg_be))) | + (racl_addr_hit_write[36] & (|(SPI_DEVICE_PERMIT[36] & ~reg_be))) | + (racl_addr_hit_write[37] & (|(SPI_DEVICE_PERMIT[37] & ~reg_be))) | + (racl_addr_hit_write[38] & (|(SPI_DEVICE_PERMIT[38] & ~reg_be))) | + (racl_addr_hit_write[39] & (|(SPI_DEVICE_PERMIT[39] & ~reg_be))) | + (racl_addr_hit_write[40] & (|(SPI_DEVICE_PERMIT[40] & ~reg_be))) | + (racl_addr_hit_write[41] & (|(SPI_DEVICE_PERMIT[41] & ~reg_be))) | + (racl_addr_hit_write[42] & (|(SPI_DEVICE_PERMIT[42] & ~reg_be))) | + (racl_addr_hit_write[43] & (|(SPI_DEVICE_PERMIT[43] & ~reg_be))) | + (racl_addr_hit_write[44] & (|(SPI_DEVICE_PERMIT[44] & ~reg_be))) | + (racl_addr_hit_write[45] & (|(SPI_DEVICE_PERMIT[45] & ~reg_be))) | + (racl_addr_hit_write[46] & (|(SPI_DEVICE_PERMIT[46] & ~reg_be))) | + (racl_addr_hit_write[47] & (|(SPI_DEVICE_PERMIT[47] & ~reg_be))) | + (racl_addr_hit_write[48] & (|(SPI_DEVICE_PERMIT[48] & ~reg_be))) | + (racl_addr_hit_write[49] & (|(SPI_DEVICE_PERMIT[49] & ~reg_be))) | + (racl_addr_hit_write[50] & (|(SPI_DEVICE_PERMIT[50] & ~reg_be))) | + (racl_addr_hit_write[51] & (|(SPI_DEVICE_PERMIT[51] & ~reg_be))) | + (racl_addr_hit_write[52] & (|(SPI_DEVICE_PERMIT[52] & ~reg_be))) | + (racl_addr_hit_write[53] & (|(SPI_DEVICE_PERMIT[53] & ~reg_be))) | + (racl_addr_hit_write[54] & (|(SPI_DEVICE_PERMIT[54] & ~reg_be))) | + (racl_addr_hit_write[55] & (|(SPI_DEVICE_PERMIT[55] & ~reg_be))) | + (racl_addr_hit_write[56] & (|(SPI_DEVICE_PERMIT[56] & ~reg_be))) | + (racl_addr_hit_write[57] & (|(SPI_DEVICE_PERMIT[57] & ~reg_be))) | + (racl_addr_hit_write[58] & (|(SPI_DEVICE_PERMIT[58] & ~reg_be))) | + (racl_addr_hit_write[59] & (|(SPI_DEVICE_PERMIT[59] & ~reg_be))) | + (racl_addr_hit_write[60] & (|(SPI_DEVICE_PERMIT[60] & ~reg_be))) | + (racl_addr_hit_write[61] & (|(SPI_DEVICE_PERMIT[61] & ~reg_be))) | + (racl_addr_hit_write[62] & (|(SPI_DEVICE_PERMIT[62] & ~reg_be))) | + (racl_addr_hit_write[63] & (|(SPI_DEVICE_PERMIT[63] & ~reg_be))) | + (racl_addr_hit_write[64] & (|(SPI_DEVICE_PERMIT[64] & ~reg_be))) | + (racl_addr_hit_write[65] & (|(SPI_DEVICE_PERMIT[65] & ~reg_be))) | + (racl_addr_hit_write[66] & (|(SPI_DEVICE_PERMIT[66] & ~reg_be))) | + (racl_addr_hit_write[67] & (|(SPI_DEVICE_PERMIT[67] & ~reg_be))) | + (racl_addr_hit_write[68] & (|(SPI_DEVICE_PERMIT[68] & ~reg_be))) | + (racl_addr_hit_write[69] & (|(SPI_DEVICE_PERMIT[69] & ~reg_be))) | + (racl_addr_hit_write[70] & (|(SPI_DEVICE_PERMIT[70] & ~reg_be))) | + (racl_addr_hit_write[71] & (|(SPI_DEVICE_PERMIT[71] & ~reg_be))) | + (racl_addr_hit_write[72] & (|(SPI_DEVICE_PERMIT[72] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = racl_addr_hit_write[0] & reg_we & !reg_error; + + assign intr_state_upload_cmdfifo_not_empty_wd = reg_wdata[0]; + + assign intr_state_upload_payload_not_empty_wd = reg_wdata[1]; + + assign intr_state_upload_payload_overflow_wd = reg_wdata[2]; + + assign intr_state_readbuf_watermark_wd = reg_wdata[3]; + + assign intr_state_readbuf_flip_wd = reg_wdata[4]; + + assign intr_state_tpm_rdfifo_cmd_end_wd = reg_wdata[6]; + + assign intr_state_tpm_rdfifo_drop_wd = reg_wdata[7]; + + assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign intr_enable_upload_cmdfifo_not_empty_wd = reg_wdata[0]; + + assign intr_enable_upload_payload_not_empty_wd = reg_wdata[1]; + + assign intr_enable_upload_payload_overflow_wd = reg_wdata[2]; + + assign intr_enable_readbuf_watermark_wd = reg_wdata[3]; + + assign intr_enable_readbuf_flip_wd = reg_wdata[4]; + + assign intr_enable_tpm_header_not_empty_wd = reg_wdata[5]; + + assign intr_enable_tpm_rdfifo_cmd_end_wd = reg_wdata[6]; + + assign intr_enable_tpm_rdfifo_drop_wd = reg_wdata[7]; + + assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign intr_test_upload_cmdfifo_not_empty_wd = reg_wdata[0]; + + assign intr_test_upload_payload_not_empty_wd = reg_wdata[1]; + + assign intr_test_upload_payload_overflow_wd = reg_wdata[2]; + + assign intr_test_readbuf_watermark_wd = reg_wdata[3]; + + assign intr_test_readbuf_flip_wd = reg_wdata[4]; + + assign intr_test_tpm_header_not_empty_wd = reg_wdata[5]; + + assign intr_test_tpm_rdfifo_cmd_end_wd = reg_wdata[6]; + + assign intr_test_tpm_rdfifo_drop_wd = reg_wdata[7]; + + assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + + assign control_we = racl_addr_hit_write[4] & reg_we & !reg_error; + + assign control_flash_status_fifo_clr_wd = reg_wdata[0]; + + assign control_flash_read_buffer_clr_wd = reg_wdata[1]; + + assign control_mode_wd = reg_wdata[5:4]; + + assign cfg_we = racl_addr_hit_write[5] & reg_we & !reg_error; + + assign cfg_tx_order_wd = reg_wdata[2]; + + assign cfg_rx_order_wd = reg_wdata[3]; + + assign cfg_mailbox_en_wd = reg_wdata[24]; + + assign status_re = racl_addr_hit_read[6] & reg_re & !reg_error; + assign intercept_en_we = racl_addr_hit_write[7] & reg_we & !reg_error; + + assign intercept_en_status_wd = reg_wdata[0]; + + assign intercept_en_jedec_wd = reg_wdata[1]; + + assign intercept_en_sfdp_wd = reg_wdata[2]; + + assign intercept_en_mbx_wd = reg_wdata[3]; + + assign addr_mode_re = racl_addr_hit_read[8] & reg_re & !reg_error; + assign addr_mode_we = racl_addr_hit_write[8] & reg_we & !reg_error; + + assign addr_mode_addr_4b_en_wd = reg_wdata[0]; + + assign last_read_addr_re = racl_addr_hit_read[9] & reg_re & !reg_error; + assign flash_status_re = racl_addr_hit_read[10] & reg_re & !reg_error; + assign flash_status_we = racl_addr_hit_write[10] & reg_we & !reg_error; + + assign flash_status_busy_wd = reg_wdata[0]; + + assign flash_status_wel_wd = reg_wdata[1]; + + assign flash_status_status_wd = reg_wdata[23:2]; + + assign jedec_cc_we = racl_addr_hit_write[11] & reg_we & !reg_error; + + assign jedec_cc_cc_wd = reg_wdata[7:0]; + + assign jedec_cc_num_cc_wd = reg_wdata[15:8]; + + assign jedec_id_we = racl_addr_hit_write[12] & reg_we & !reg_error; + + assign jedec_id_id_wd = reg_wdata[15:0]; + + assign jedec_id_mf_wd = reg_wdata[23:16]; + + assign read_threshold_we = racl_addr_hit_write[13] & reg_we & !reg_error; + + assign read_threshold_wd = reg_wdata[9:0]; + + assign mailbox_addr_we = racl_addr_hit_write[14] & reg_we & !reg_error; + + assign mailbox_addr_wd = reg_wdata[31:0]; + + assign upload_cmdfifo_re = racl_addr_hit_read[17] & reg_re & !reg_error; + assign upload_addrfifo_re = racl_addr_hit_read[18] & reg_re & !reg_error; + assign cmd_filter_0_we = racl_addr_hit_write[19] & reg_we & !reg_error; + + assign cmd_filter_0_filter_0_wd = reg_wdata[0]; + + assign cmd_filter_0_filter_1_wd = reg_wdata[1]; + + assign cmd_filter_0_filter_2_wd = reg_wdata[2]; + + assign cmd_filter_0_filter_3_wd = reg_wdata[3]; + + assign cmd_filter_0_filter_4_wd = reg_wdata[4]; + + assign cmd_filter_0_filter_5_wd = reg_wdata[5]; + + assign cmd_filter_0_filter_6_wd = reg_wdata[6]; + + assign cmd_filter_0_filter_7_wd = reg_wdata[7]; + + assign cmd_filter_0_filter_8_wd = reg_wdata[8]; + + assign cmd_filter_0_filter_9_wd = reg_wdata[9]; + + assign cmd_filter_0_filter_10_wd = reg_wdata[10]; + + assign cmd_filter_0_filter_11_wd = reg_wdata[11]; + + assign cmd_filter_0_filter_12_wd = reg_wdata[12]; + + assign cmd_filter_0_filter_13_wd = reg_wdata[13]; + + assign cmd_filter_0_filter_14_wd = reg_wdata[14]; + + assign cmd_filter_0_filter_15_wd = reg_wdata[15]; + + assign cmd_filter_0_filter_16_wd = reg_wdata[16]; + + assign cmd_filter_0_filter_17_wd = reg_wdata[17]; + + assign cmd_filter_0_filter_18_wd = reg_wdata[18]; + + assign cmd_filter_0_filter_19_wd = reg_wdata[19]; + + assign cmd_filter_0_filter_20_wd = reg_wdata[20]; + + assign cmd_filter_0_filter_21_wd = reg_wdata[21]; + + assign cmd_filter_0_filter_22_wd = reg_wdata[22]; + + assign cmd_filter_0_filter_23_wd = reg_wdata[23]; + + assign cmd_filter_0_filter_24_wd = reg_wdata[24]; + + assign cmd_filter_0_filter_25_wd = reg_wdata[25]; + + assign cmd_filter_0_filter_26_wd = reg_wdata[26]; + + assign cmd_filter_0_filter_27_wd = reg_wdata[27]; + + assign cmd_filter_0_filter_28_wd = reg_wdata[28]; + + assign cmd_filter_0_filter_29_wd = reg_wdata[29]; + + assign cmd_filter_0_filter_30_wd = reg_wdata[30]; + + assign cmd_filter_0_filter_31_wd = reg_wdata[31]; + + assign cmd_filter_1_we = racl_addr_hit_write[20] & reg_we & !reg_error; + + assign cmd_filter_1_filter_32_wd = reg_wdata[0]; + + assign cmd_filter_1_filter_33_wd = reg_wdata[1]; + + assign cmd_filter_1_filter_34_wd = reg_wdata[2]; + + assign cmd_filter_1_filter_35_wd = reg_wdata[3]; + + assign cmd_filter_1_filter_36_wd = reg_wdata[4]; + + assign cmd_filter_1_filter_37_wd = reg_wdata[5]; + + assign cmd_filter_1_filter_38_wd = reg_wdata[6]; + + assign cmd_filter_1_filter_39_wd = reg_wdata[7]; + + assign cmd_filter_1_filter_40_wd = reg_wdata[8]; + + assign cmd_filter_1_filter_41_wd = reg_wdata[9]; + + assign cmd_filter_1_filter_42_wd = reg_wdata[10]; + + assign cmd_filter_1_filter_43_wd = reg_wdata[11]; + + assign cmd_filter_1_filter_44_wd = reg_wdata[12]; + + assign cmd_filter_1_filter_45_wd = reg_wdata[13]; + + assign cmd_filter_1_filter_46_wd = reg_wdata[14]; + + assign cmd_filter_1_filter_47_wd = reg_wdata[15]; + + assign cmd_filter_1_filter_48_wd = reg_wdata[16]; + + assign cmd_filter_1_filter_49_wd = reg_wdata[17]; + + assign cmd_filter_1_filter_50_wd = reg_wdata[18]; + + assign cmd_filter_1_filter_51_wd = reg_wdata[19]; + + assign cmd_filter_1_filter_52_wd = reg_wdata[20]; + + assign cmd_filter_1_filter_53_wd = reg_wdata[21]; + + assign cmd_filter_1_filter_54_wd = reg_wdata[22]; + + assign cmd_filter_1_filter_55_wd = reg_wdata[23]; + + assign cmd_filter_1_filter_56_wd = reg_wdata[24]; + + assign cmd_filter_1_filter_57_wd = reg_wdata[25]; + + assign cmd_filter_1_filter_58_wd = reg_wdata[26]; + + assign cmd_filter_1_filter_59_wd = reg_wdata[27]; + + assign cmd_filter_1_filter_60_wd = reg_wdata[28]; + + assign cmd_filter_1_filter_61_wd = reg_wdata[29]; + + assign cmd_filter_1_filter_62_wd = reg_wdata[30]; + + assign cmd_filter_1_filter_63_wd = reg_wdata[31]; + + assign cmd_filter_2_we = racl_addr_hit_write[21] & reg_we & !reg_error; + + assign cmd_filter_2_filter_64_wd = reg_wdata[0]; + + assign cmd_filter_2_filter_65_wd = reg_wdata[1]; + + assign cmd_filter_2_filter_66_wd = reg_wdata[2]; + + assign cmd_filter_2_filter_67_wd = reg_wdata[3]; + + assign cmd_filter_2_filter_68_wd = reg_wdata[4]; + + assign cmd_filter_2_filter_69_wd = reg_wdata[5]; + + assign cmd_filter_2_filter_70_wd = reg_wdata[6]; + + assign cmd_filter_2_filter_71_wd = reg_wdata[7]; + + assign cmd_filter_2_filter_72_wd = reg_wdata[8]; + + assign cmd_filter_2_filter_73_wd = reg_wdata[9]; + + assign cmd_filter_2_filter_74_wd = reg_wdata[10]; + + assign cmd_filter_2_filter_75_wd = reg_wdata[11]; + + assign cmd_filter_2_filter_76_wd = reg_wdata[12]; + + assign cmd_filter_2_filter_77_wd = reg_wdata[13]; + + assign cmd_filter_2_filter_78_wd = reg_wdata[14]; + + assign cmd_filter_2_filter_79_wd = reg_wdata[15]; + + assign cmd_filter_2_filter_80_wd = reg_wdata[16]; + + assign cmd_filter_2_filter_81_wd = reg_wdata[17]; + + assign cmd_filter_2_filter_82_wd = reg_wdata[18]; + + assign cmd_filter_2_filter_83_wd = reg_wdata[19]; + + assign cmd_filter_2_filter_84_wd = reg_wdata[20]; + + assign cmd_filter_2_filter_85_wd = reg_wdata[21]; + + assign cmd_filter_2_filter_86_wd = reg_wdata[22]; + + assign cmd_filter_2_filter_87_wd = reg_wdata[23]; + + assign cmd_filter_2_filter_88_wd = reg_wdata[24]; + + assign cmd_filter_2_filter_89_wd = reg_wdata[25]; + + assign cmd_filter_2_filter_90_wd = reg_wdata[26]; + + assign cmd_filter_2_filter_91_wd = reg_wdata[27]; + + assign cmd_filter_2_filter_92_wd = reg_wdata[28]; + + assign cmd_filter_2_filter_93_wd = reg_wdata[29]; + + assign cmd_filter_2_filter_94_wd = reg_wdata[30]; + + assign cmd_filter_2_filter_95_wd = reg_wdata[31]; + + assign cmd_filter_3_we = racl_addr_hit_write[22] & reg_we & !reg_error; + + assign cmd_filter_3_filter_96_wd = reg_wdata[0]; + + assign cmd_filter_3_filter_97_wd = reg_wdata[1]; + + assign cmd_filter_3_filter_98_wd = reg_wdata[2]; + + assign cmd_filter_3_filter_99_wd = reg_wdata[3]; + + assign cmd_filter_3_filter_100_wd = reg_wdata[4]; + + assign cmd_filter_3_filter_101_wd = reg_wdata[5]; + + assign cmd_filter_3_filter_102_wd = reg_wdata[6]; + + assign cmd_filter_3_filter_103_wd = reg_wdata[7]; + + assign cmd_filter_3_filter_104_wd = reg_wdata[8]; + + assign cmd_filter_3_filter_105_wd = reg_wdata[9]; + + assign cmd_filter_3_filter_106_wd = reg_wdata[10]; + + assign cmd_filter_3_filter_107_wd = reg_wdata[11]; + + assign cmd_filter_3_filter_108_wd = reg_wdata[12]; + + assign cmd_filter_3_filter_109_wd = reg_wdata[13]; + + assign cmd_filter_3_filter_110_wd = reg_wdata[14]; + + assign cmd_filter_3_filter_111_wd = reg_wdata[15]; + + assign cmd_filter_3_filter_112_wd = reg_wdata[16]; + + assign cmd_filter_3_filter_113_wd = reg_wdata[17]; + + assign cmd_filter_3_filter_114_wd = reg_wdata[18]; + + assign cmd_filter_3_filter_115_wd = reg_wdata[19]; + + assign cmd_filter_3_filter_116_wd = reg_wdata[20]; + + assign cmd_filter_3_filter_117_wd = reg_wdata[21]; + + assign cmd_filter_3_filter_118_wd = reg_wdata[22]; + + assign cmd_filter_3_filter_119_wd = reg_wdata[23]; + + assign cmd_filter_3_filter_120_wd = reg_wdata[24]; + + assign cmd_filter_3_filter_121_wd = reg_wdata[25]; + + assign cmd_filter_3_filter_122_wd = reg_wdata[26]; + + assign cmd_filter_3_filter_123_wd = reg_wdata[27]; + + assign cmd_filter_3_filter_124_wd = reg_wdata[28]; + + assign cmd_filter_3_filter_125_wd = reg_wdata[29]; + + assign cmd_filter_3_filter_126_wd = reg_wdata[30]; + + assign cmd_filter_3_filter_127_wd = reg_wdata[31]; + + assign cmd_filter_4_we = racl_addr_hit_write[23] & reg_we & !reg_error; + + assign cmd_filter_4_filter_128_wd = reg_wdata[0]; + + assign cmd_filter_4_filter_129_wd = reg_wdata[1]; + + assign cmd_filter_4_filter_130_wd = reg_wdata[2]; + + assign cmd_filter_4_filter_131_wd = reg_wdata[3]; + + assign cmd_filter_4_filter_132_wd = reg_wdata[4]; + + assign cmd_filter_4_filter_133_wd = reg_wdata[5]; + + assign cmd_filter_4_filter_134_wd = reg_wdata[6]; + + assign cmd_filter_4_filter_135_wd = reg_wdata[7]; + + assign cmd_filter_4_filter_136_wd = reg_wdata[8]; + + assign cmd_filter_4_filter_137_wd = reg_wdata[9]; + + assign cmd_filter_4_filter_138_wd = reg_wdata[10]; + + assign cmd_filter_4_filter_139_wd = reg_wdata[11]; + + assign cmd_filter_4_filter_140_wd = reg_wdata[12]; + + assign cmd_filter_4_filter_141_wd = reg_wdata[13]; + + assign cmd_filter_4_filter_142_wd = reg_wdata[14]; + + assign cmd_filter_4_filter_143_wd = reg_wdata[15]; + + assign cmd_filter_4_filter_144_wd = reg_wdata[16]; + + assign cmd_filter_4_filter_145_wd = reg_wdata[17]; + + assign cmd_filter_4_filter_146_wd = reg_wdata[18]; + + assign cmd_filter_4_filter_147_wd = reg_wdata[19]; + + assign cmd_filter_4_filter_148_wd = reg_wdata[20]; + + assign cmd_filter_4_filter_149_wd = reg_wdata[21]; + + assign cmd_filter_4_filter_150_wd = reg_wdata[22]; + + assign cmd_filter_4_filter_151_wd = reg_wdata[23]; + + assign cmd_filter_4_filter_152_wd = reg_wdata[24]; + + assign cmd_filter_4_filter_153_wd = reg_wdata[25]; + + assign cmd_filter_4_filter_154_wd = reg_wdata[26]; + + assign cmd_filter_4_filter_155_wd = reg_wdata[27]; + + assign cmd_filter_4_filter_156_wd = reg_wdata[28]; + + assign cmd_filter_4_filter_157_wd = reg_wdata[29]; + + assign cmd_filter_4_filter_158_wd = reg_wdata[30]; + + assign cmd_filter_4_filter_159_wd = reg_wdata[31]; + + assign cmd_filter_5_we = racl_addr_hit_write[24] & reg_we & !reg_error; + + assign cmd_filter_5_filter_160_wd = reg_wdata[0]; + + assign cmd_filter_5_filter_161_wd = reg_wdata[1]; + + assign cmd_filter_5_filter_162_wd = reg_wdata[2]; + + assign cmd_filter_5_filter_163_wd = reg_wdata[3]; + + assign cmd_filter_5_filter_164_wd = reg_wdata[4]; + + assign cmd_filter_5_filter_165_wd = reg_wdata[5]; + + assign cmd_filter_5_filter_166_wd = reg_wdata[6]; + + assign cmd_filter_5_filter_167_wd = reg_wdata[7]; + + assign cmd_filter_5_filter_168_wd = reg_wdata[8]; + + assign cmd_filter_5_filter_169_wd = reg_wdata[9]; + + assign cmd_filter_5_filter_170_wd = reg_wdata[10]; + + assign cmd_filter_5_filter_171_wd = reg_wdata[11]; + + assign cmd_filter_5_filter_172_wd = reg_wdata[12]; + + assign cmd_filter_5_filter_173_wd = reg_wdata[13]; + + assign cmd_filter_5_filter_174_wd = reg_wdata[14]; + + assign cmd_filter_5_filter_175_wd = reg_wdata[15]; + + assign cmd_filter_5_filter_176_wd = reg_wdata[16]; + + assign cmd_filter_5_filter_177_wd = reg_wdata[17]; + + assign cmd_filter_5_filter_178_wd = reg_wdata[18]; + + assign cmd_filter_5_filter_179_wd = reg_wdata[19]; + + assign cmd_filter_5_filter_180_wd = reg_wdata[20]; + + assign cmd_filter_5_filter_181_wd = reg_wdata[21]; + + assign cmd_filter_5_filter_182_wd = reg_wdata[22]; + + assign cmd_filter_5_filter_183_wd = reg_wdata[23]; + + assign cmd_filter_5_filter_184_wd = reg_wdata[24]; + + assign cmd_filter_5_filter_185_wd = reg_wdata[25]; + + assign cmd_filter_5_filter_186_wd = reg_wdata[26]; + + assign cmd_filter_5_filter_187_wd = reg_wdata[27]; + + assign cmd_filter_5_filter_188_wd = reg_wdata[28]; + + assign cmd_filter_5_filter_189_wd = reg_wdata[29]; + + assign cmd_filter_5_filter_190_wd = reg_wdata[30]; + + assign cmd_filter_5_filter_191_wd = reg_wdata[31]; + + assign cmd_filter_6_we = racl_addr_hit_write[25] & reg_we & !reg_error; + + assign cmd_filter_6_filter_192_wd = reg_wdata[0]; + + assign cmd_filter_6_filter_193_wd = reg_wdata[1]; + + assign cmd_filter_6_filter_194_wd = reg_wdata[2]; + + assign cmd_filter_6_filter_195_wd = reg_wdata[3]; + + assign cmd_filter_6_filter_196_wd = reg_wdata[4]; + + assign cmd_filter_6_filter_197_wd = reg_wdata[5]; + + assign cmd_filter_6_filter_198_wd = reg_wdata[6]; + + assign cmd_filter_6_filter_199_wd = reg_wdata[7]; + + assign cmd_filter_6_filter_200_wd = reg_wdata[8]; + + assign cmd_filter_6_filter_201_wd = reg_wdata[9]; + + assign cmd_filter_6_filter_202_wd = reg_wdata[10]; + + assign cmd_filter_6_filter_203_wd = reg_wdata[11]; + + assign cmd_filter_6_filter_204_wd = reg_wdata[12]; + + assign cmd_filter_6_filter_205_wd = reg_wdata[13]; + + assign cmd_filter_6_filter_206_wd = reg_wdata[14]; + + assign cmd_filter_6_filter_207_wd = reg_wdata[15]; + + assign cmd_filter_6_filter_208_wd = reg_wdata[16]; + + assign cmd_filter_6_filter_209_wd = reg_wdata[17]; + + assign cmd_filter_6_filter_210_wd = reg_wdata[18]; + + assign cmd_filter_6_filter_211_wd = reg_wdata[19]; + + assign cmd_filter_6_filter_212_wd = reg_wdata[20]; + + assign cmd_filter_6_filter_213_wd = reg_wdata[21]; + + assign cmd_filter_6_filter_214_wd = reg_wdata[22]; + + assign cmd_filter_6_filter_215_wd = reg_wdata[23]; + + assign cmd_filter_6_filter_216_wd = reg_wdata[24]; + + assign cmd_filter_6_filter_217_wd = reg_wdata[25]; + + assign cmd_filter_6_filter_218_wd = reg_wdata[26]; + + assign cmd_filter_6_filter_219_wd = reg_wdata[27]; + + assign cmd_filter_6_filter_220_wd = reg_wdata[28]; + + assign cmd_filter_6_filter_221_wd = reg_wdata[29]; + + assign cmd_filter_6_filter_222_wd = reg_wdata[30]; + + assign cmd_filter_6_filter_223_wd = reg_wdata[31]; + + assign cmd_filter_7_we = racl_addr_hit_write[26] & reg_we & !reg_error; + + assign cmd_filter_7_filter_224_wd = reg_wdata[0]; + + assign cmd_filter_7_filter_225_wd = reg_wdata[1]; + + assign cmd_filter_7_filter_226_wd = reg_wdata[2]; + + assign cmd_filter_7_filter_227_wd = reg_wdata[3]; + + assign cmd_filter_7_filter_228_wd = reg_wdata[4]; + + assign cmd_filter_7_filter_229_wd = reg_wdata[5]; + + assign cmd_filter_7_filter_230_wd = reg_wdata[6]; + + assign cmd_filter_7_filter_231_wd = reg_wdata[7]; + + assign cmd_filter_7_filter_232_wd = reg_wdata[8]; + + assign cmd_filter_7_filter_233_wd = reg_wdata[9]; + + assign cmd_filter_7_filter_234_wd = reg_wdata[10]; + + assign cmd_filter_7_filter_235_wd = reg_wdata[11]; + + assign cmd_filter_7_filter_236_wd = reg_wdata[12]; + + assign cmd_filter_7_filter_237_wd = reg_wdata[13]; + + assign cmd_filter_7_filter_238_wd = reg_wdata[14]; + + assign cmd_filter_7_filter_239_wd = reg_wdata[15]; + + assign cmd_filter_7_filter_240_wd = reg_wdata[16]; + + assign cmd_filter_7_filter_241_wd = reg_wdata[17]; + + assign cmd_filter_7_filter_242_wd = reg_wdata[18]; + + assign cmd_filter_7_filter_243_wd = reg_wdata[19]; + + assign cmd_filter_7_filter_244_wd = reg_wdata[20]; + + assign cmd_filter_7_filter_245_wd = reg_wdata[21]; + + assign cmd_filter_7_filter_246_wd = reg_wdata[22]; + + assign cmd_filter_7_filter_247_wd = reg_wdata[23]; + + assign cmd_filter_7_filter_248_wd = reg_wdata[24]; + + assign cmd_filter_7_filter_249_wd = reg_wdata[25]; + + assign cmd_filter_7_filter_250_wd = reg_wdata[26]; + + assign cmd_filter_7_filter_251_wd = reg_wdata[27]; + + assign cmd_filter_7_filter_252_wd = reg_wdata[28]; + + assign cmd_filter_7_filter_253_wd = reg_wdata[29]; + + assign cmd_filter_7_filter_254_wd = reg_wdata[30]; + + assign cmd_filter_7_filter_255_wd = reg_wdata[31]; + + assign addr_swap_mask_we = racl_addr_hit_write[27] & reg_we & !reg_error; + + assign addr_swap_mask_wd = reg_wdata[31:0]; + + assign addr_swap_data_we = racl_addr_hit_write[28] & reg_we & !reg_error; + + assign addr_swap_data_wd = reg_wdata[31:0]; + + assign payload_swap_mask_we = racl_addr_hit_write[29] & reg_we & !reg_error; + + assign payload_swap_mask_wd = reg_wdata[31:0]; + + assign payload_swap_data_we = racl_addr_hit_write[30] & reg_we & !reg_error; + + assign payload_swap_data_wd = reg_wdata[31:0]; + + assign cmd_info_0_we = racl_addr_hit_write[31] & reg_we & !reg_error; + + assign cmd_info_0_opcode_0_wd = reg_wdata[7:0]; + + assign cmd_info_0_addr_mode_0_wd = reg_wdata[9:8]; + + assign cmd_info_0_addr_swap_en_0_wd = reg_wdata[10]; + + assign cmd_info_0_mbyte_en_0_wd = reg_wdata[11]; + + assign cmd_info_0_dummy_size_0_wd = reg_wdata[14:12]; + + assign cmd_info_0_dummy_en_0_wd = reg_wdata[15]; + + assign cmd_info_0_payload_en_0_wd = reg_wdata[19:16]; + + assign cmd_info_0_payload_dir_0_wd = reg_wdata[20]; + + assign cmd_info_0_payload_swap_en_0_wd = reg_wdata[21]; + + assign cmd_info_0_read_pipeline_mode_0_wd = reg_wdata[23:22]; + + assign cmd_info_0_upload_0_wd = reg_wdata[24]; + + assign cmd_info_0_busy_0_wd = reg_wdata[25]; + + assign cmd_info_0_valid_0_wd = reg_wdata[31]; + + assign cmd_info_1_we = racl_addr_hit_write[32] & reg_we & !reg_error; + + assign cmd_info_1_opcode_1_wd = reg_wdata[7:0]; + + assign cmd_info_1_addr_mode_1_wd = reg_wdata[9:8]; + + assign cmd_info_1_addr_swap_en_1_wd = reg_wdata[10]; + + assign cmd_info_1_mbyte_en_1_wd = reg_wdata[11]; + + assign cmd_info_1_dummy_size_1_wd = reg_wdata[14:12]; + + assign cmd_info_1_dummy_en_1_wd = reg_wdata[15]; + + assign cmd_info_1_payload_en_1_wd = reg_wdata[19:16]; + + assign cmd_info_1_payload_dir_1_wd = reg_wdata[20]; + + assign cmd_info_1_payload_swap_en_1_wd = reg_wdata[21]; + + assign cmd_info_1_read_pipeline_mode_1_wd = reg_wdata[23:22]; + + assign cmd_info_1_upload_1_wd = reg_wdata[24]; + + assign cmd_info_1_busy_1_wd = reg_wdata[25]; + + assign cmd_info_1_valid_1_wd = reg_wdata[31]; + + assign cmd_info_2_we = racl_addr_hit_write[33] & reg_we & !reg_error; + + assign cmd_info_2_opcode_2_wd = reg_wdata[7:0]; + + assign cmd_info_2_addr_mode_2_wd = reg_wdata[9:8]; + + assign cmd_info_2_addr_swap_en_2_wd = reg_wdata[10]; + + assign cmd_info_2_mbyte_en_2_wd = reg_wdata[11]; + + assign cmd_info_2_dummy_size_2_wd = reg_wdata[14:12]; + + assign cmd_info_2_dummy_en_2_wd = reg_wdata[15]; + + assign cmd_info_2_payload_en_2_wd = reg_wdata[19:16]; + + assign cmd_info_2_payload_dir_2_wd = reg_wdata[20]; + + assign cmd_info_2_payload_swap_en_2_wd = reg_wdata[21]; + + assign cmd_info_2_read_pipeline_mode_2_wd = reg_wdata[23:22]; + + assign cmd_info_2_upload_2_wd = reg_wdata[24]; + + assign cmd_info_2_busy_2_wd = reg_wdata[25]; + + assign cmd_info_2_valid_2_wd = reg_wdata[31]; + + assign cmd_info_3_we = racl_addr_hit_write[34] & reg_we & !reg_error; + + assign cmd_info_3_opcode_3_wd = reg_wdata[7:0]; + + assign cmd_info_3_addr_mode_3_wd = reg_wdata[9:8]; + + assign cmd_info_3_addr_swap_en_3_wd = reg_wdata[10]; + + assign cmd_info_3_mbyte_en_3_wd = reg_wdata[11]; + + assign cmd_info_3_dummy_size_3_wd = reg_wdata[14:12]; + + assign cmd_info_3_dummy_en_3_wd = reg_wdata[15]; + + assign cmd_info_3_payload_en_3_wd = reg_wdata[19:16]; + + assign cmd_info_3_payload_dir_3_wd = reg_wdata[20]; + + assign cmd_info_3_payload_swap_en_3_wd = reg_wdata[21]; + + assign cmd_info_3_read_pipeline_mode_3_wd = reg_wdata[23:22]; + + assign cmd_info_3_upload_3_wd = reg_wdata[24]; + + assign cmd_info_3_busy_3_wd = reg_wdata[25]; + + assign cmd_info_3_valid_3_wd = reg_wdata[31]; + + assign cmd_info_4_we = racl_addr_hit_write[35] & reg_we & !reg_error; + + assign cmd_info_4_opcode_4_wd = reg_wdata[7:0]; + + assign cmd_info_4_addr_mode_4_wd = reg_wdata[9:8]; + + assign cmd_info_4_addr_swap_en_4_wd = reg_wdata[10]; + + assign cmd_info_4_mbyte_en_4_wd = reg_wdata[11]; + + assign cmd_info_4_dummy_size_4_wd = reg_wdata[14:12]; + + assign cmd_info_4_dummy_en_4_wd = reg_wdata[15]; + + assign cmd_info_4_payload_en_4_wd = reg_wdata[19:16]; + + assign cmd_info_4_payload_dir_4_wd = reg_wdata[20]; + + assign cmd_info_4_payload_swap_en_4_wd = reg_wdata[21]; + + assign cmd_info_4_read_pipeline_mode_4_wd = reg_wdata[23:22]; + + assign cmd_info_4_upload_4_wd = reg_wdata[24]; + + assign cmd_info_4_busy_4_wd = reg_wdata[25]; + + assign cmd_info_4_valid_4_wd = reg_wdata[31]; + + assign cmd_info_5_we = racl_addr_hit_write[36] & reg_we & !reg_error; + + assign cmd_info_5_opcode_5_wd = reg_wdata[7:0]; + + assign cmd_info_5_addr_mode_5_wd = reg_wdata[9:8]; + + assign cmd_info_5_addr_swap_en_5_wd = reg_wdata[10]; + + assign cmd_info_5_mbyte_en_5_wd = reg_wdata[11]; + + assign cmd_info_5_dummy_size_5_wd = reg_wdata[14:12]; + + assign cmd_info_5_dummy_en_5_wd = reg_wdata[15]; + + assign cmd_info_5_payload_en_5_wd = reg_wdata[19:16]; + + assign cmd_info_5_payload_dir_5_wd = reg_wdata[20]; + + assign cmd_info_5_payload_swap_en_5_wd = reg_wdata[21]; + + assign cmd_info_5_read_pipeline_mode_5_wd = reg_wdata[23:22]; + + assign cmd_info_5_upload_5_wd = reg_wdata[24]; + + assign cmd_info_5_busy_5_wd = reg_wdata[25]; + + assign cmd_info_5_valid_5_wd = reg_wdata[31]; + + assign cmd_info_6_we = racl_addr_hit_write[37] & reg_we & !reg_error; + + assign cmd_info_6_opcode_6_wd = reg_wdata[7:0]; + + assign cmd_info_6_addr_mode_6_wd = reg_wdata[9:8]; + + assign cmd_info_6_addr_swap_en_6_wd = reg_wdata[10]; + + assign cmd_info_6_mbyte_en_6_wd = reg_wdata[11]; + + assign cmd_info_6_dummy_size_6_wd = reg_wdata[14:12]; + + assign cmd_info_6_dummy_en_6_wd = reg_wdata[15]; + + assign cmd_info_6_payload_en_6_wd = reg_wdata[19:16]; + + assign cmd_info_6_payload_dir_6_wd = reg_wdata[20]; + + assign cmd_info_6_payload_swap_en_6_wd = reg_wdata[21]; + + assign cmd_info_6_read_pipeline_mode_6_wd = reg_wdata[23:22]; + + assign cmd_info_6_upload_6_wd = reg_wdata[24]; + + assign cmd_info_6_busy_6_wd = reg_wdata[25]; + + assign cmd_info_6_valid_6_wd = reg_wdata[31]; + + assign cmd_info_7_we = racl_addr_hit_write[38] & reg_we & !reg_error; + + assign cmd_info_7_opcode_7_wd = reg_wdata[7:0]; + + assign cmd_info_7_addr_mode_7_wd = reg_wdata[9:8]; + + assign cmd_info_7_addr_swap_en_7_wd = reg_wdata[10]; + + assign cmd_info_7_mbyte_en_7_wd = reg_wdata[11]; + + assign cmd_info_7_dummy_size_7_wd = reg_wdata[14:12]; + + assign cmd_info_7_dummy_en_7_wd = reg_wdata[15]; + + assign cmd_info_7_payload_en_7_wd = reg_wdata[19:16]; + + assign cmd_info_7_payload_dir_7_wd = reg_wdata[20]; + + assign cmd_info_7_payload_swap_en_7_wd = reg_wdata[21]; + + assign cmd_info_7_read_pipeline_mode_7_wd = reg_wdata[23:22]; + + assign cmd_info_7_upload_7_wd = reg_wdata[24]; + + assign cmd_info_7_busy_7_wd = reg_wdata[25]; + + assign cmd_info_7_valid_7_wd = reg_wdata[31]; + + assign cmd_info_8_we = racl_addr_hit_write[39] & reg_we & !reg_error; + + assign cmd_info_8_opcode_8_wd = reg_wdata[7:0]; + + assign cmd_info_8_addr_mode_8_wd = reg_wdata[9:8]; + + assign cmd_info_8_addr_swap_en_8_wd = reg_wdata[10]; + + assign cmd_info_8_mbyte_en_8_wd = reg_wdata[11]; + + assign cmd_info_8_dummy_size_8_wd = reg_wdata[14:12]; + + assign cmd_info_8_dummy_en_8_wd = reg_wdata[15]; + + assign cmd_info_8_payload_en_8_wd = reg_wdata[19:16]; + + assign cmd_info_8_payload_dir_8_wd = reg_wdata[20]; + + assign cmd_info_8_payload_swap_en_8_wd = reg_wdata[21]; + + assign cmd_info_8_read_pipeline_mode_8_wd = reg_wdata[23:22]; + + assign cmd_info_8_upload_8_wd = reg_wdata[24]; + + assign cmd_info_8_busy_8_wd = reg_wdata[25]; + + assign cmd_info_8_valid_8_wd = reg_wdata[31]; + + assign cmd_info_9_we = racl_addr_hit_write[40] & reg_we & !reg_error; + + assign cmd_info_9_opcode_9_wd = reg_wdata[7:0]; + + assign cmd_info_9_addr_mode_9_wd = reg_wdata[9:8]; + + assign cmd_info_9_addr_swap_en_9_wd = reg_wdata[10]; + + assign cmd_info_9_mbyte_en_9_wd = reg_wdata[11]; + + assign cmd_info_9_dummy_size_9_wd = reg_wdata[14:12]; + + assign cmd_info_9_dummy_en_9_wd = reg_wdata[15]; + + assign cmd_info_9_payload_en_9_wd = reg_wdata[19:16]; + + assign cmd_info_9_payload_dir_9_wd = reg_wdata[20]; + + assign cmd_info_9_payload_swap_en_9_wd = reg_wdata[21]; + + assign cmd_info_9_read_pipeline_mode_9_wd = reg_wdata[23:22]; + + assign cmd_info_9_upload_9_wd = reg_wdata[24]; + + assign cmd_info_9_busy_9_wd = reg_wdata[25]; + + assign cmd_info_9_valid_9_wd = reg_wdata[31]; + + assign cmd_info_10_we = racl_addr_hit_write[41] & reg_we & !reg_error; + + assign cmd_info_10_opcode_10_wd = reg_wdata[7:0]; + + assign cmd_info_10_addr_mode_10_wd = reg_wdata[9:8]; + + assign cmd_info_10_addr_swap_en_10_wd = reg_wdata[10]; + + assign cmd_info_10_mbyte_en_10_wd = reg_wdata[11]; + + assign cmd_info_10_dummy_size_10_wd = reg_wdata[14:12]; + + assign cmd_info_10_dummy_en_10_wd = reg_wdata[15]; + + assign cmd_info_10_payload_en_10_wd = reg_wdata[19:16]; + + assign cmd_info_10_payload_dir_10_wd = reg_wdata[20]; + + assign cmd_info_10_payload_swap_en_10_wd = reg_wdata[21]; + + assign cmd_info_10_read_pipeline_mode_10_wd = reg_wdata[23:22]; + + assign cmd_info_10_upload_10_wd = reg_wdata[24]; + + assign cmd_info_10_busy_10_wd = reg_wdata[25]; + + assign cmd_info_10_valid_10_wd = reg_wdata[31]; + + assign cmd_info_11_we = racl_addr_hit_write[42] & reg_we & !reg_error; + + assign cmd_info_11_opcode_11_wd = reg_wdata[7:0]; + + assign cmd_info_11_addr_mode_11_wd = reg_wdata[9:8]; + + assign cmd_info_11_addr_swap_en_11_wd = reg_wdata[10]; + + assign cmd_info_11_mbyte_en_11_wd = reg_wdata[11]; + + assign cmd_info_11_dummy_size_11_wd = reg_wdata[14:12]; + + assign cmd_info_11_dummy_en_11_wd = reg_wdata[15]; + + assign cmd_info_11_payload_en_11_wd = reg_wdata[19:16]; + + assign cmd_info_11_payload_dir_11_wd = reg_wdata[20]; + + assign cmd_info_11_payload_swap_en_11_wd = reg_wdata[21]; + + assign cmd_info_11_read_pipeline_mode_11_wd = reg_wdata[23:22]; + + assign cmd_info_11_upload_11_wd = reg_wdata[24]; + + assign cmd_info_11_busy_11_wd = reg_wdata[25]; + + assign cmd_info_11_valid_11_wd = reg_wdata[31]; + + assign cmd_info_12_we = racl_addr_hit_write[43] & reg_we & !reg_error; + + assign cmd_info_12_opcode_12_wd = reg_wdata[7:0]; + + assign cmd_info_12_addr_mode_12_wd = reg_wdata[9:8]; + + assign cmd_info_12_addr_swap_en_12_wd = reg_wdata[10]; + + assign cmd_info_12_mbyte_en_12_wd = reg_wdata[11]; + + assign cmd_info_12_dummy_size_12_wd = reg_wdata[14:12]; + + assign cmd_info_12_dummy_en_12_wd = reg_wdata[15]; + + assign cmd_info_12_payload_en_12_wd = reg_wdata[19:16]; + + assign cmd_info_12_payload_dir_12_wd = reg_wdata[20]; + + assign cmd_info_12_payload_swap_en_12_wd = reg_wdata[21]; + + assign cmd_info_12_read_pipeline_mode_12_wd = reg_wdata[23:22]; + + assign cmd_info_12_upload_12_wd = reg_wdata[24]; + + assign cmd_info_12_busy_12_wd = reg_wdata[25]; + + assign cmd_info_12_valid_12_wd = reg_wdata[31]; + + assign cmd_info_13_we = racl_addr_hit_write[44] & reg_we & !reg_error; + + assign cmd_info_13_opcode_13_wd = reg_wdata[7:0]; + + assign cmd_info_13_addr_mode_13_wd = reg_wdata[9:8]; + + assign cmd_info_13_addr_swap_en_13_wd = reg_wdata[10]; + + assign cmd_info_13_mbyte_en_13_wd = reg_wdata[11]; + + assign cmd_info_13_dummy_size_13_wd = reg_wdata[14:12]; + + assign cmd_info_13_dummy_en_13_wd = reg_wdata[15]; + + assign cmd_info_13_payload_en_13_wd = reg_wdata[19:16]; + + assign cmd_info_13_payload_dir_13_wd = reg_wdata[20]; + + assign cmd_info_13_payload_swap_en_13_wd = reg_wdata[21]; + + assign cmd_info_13_read_pipeline_mode_13_wd = reg_wdata[23:22]; + + assign cmd_info_13_upload_13_wd = reg_wdata[24]; + + assign cmd_info_13_busy_13_wd = reg_wdata[25]; + + assign cmd_info_13_valid_13_wd = reg_wdata[31]; + + assign cmd_info_14_we = racl_addr_hit_write[45] & reg_we & !reg_error; + + assign cmd_info_14_opcode_14_wd = reg_wdata[7:0]; + + assign cmd_info_14_addr_mode_14_wd = reg_wdata[9:8]; + + assign cmd_info_14_addr_swap_en_14_wd = reg_wdata[10]; + + assign cmd_info_14_mbyte_en_14_wd = reg_wdata[11]; + + assign cmd_info_14_dummy_size_14_wd = reg_wdata[14:12]; + + assign cmd_info_14_dummy_en_14_wd = reg_wdata[15]; + + assign cmd_info_14_payload_en_14_wd = reg_wdata[19:16]; + + assign cmd_info_14_payload_dir_14_wd = reg_wdata[20]; + + assign cmd_info_14_payload_swap_en_14_wd = reg_wdata[21]; + + assign cmd_info_14_read_pipeline_mode_14_wd = reg_wdata[23:22]; + + assign cmd_info_14_upload_14_wd = reg_wdata[24]; + + assign cmd_info_14_busy_14_wd = reg_wdata[25]; + + assign cmd_info_14_valid_14_wd = reg_wdata[31]; + + assign cmd_info_15_we = racl_addr_hit_write[46] & reg_we & !reg_error; + + assign cmd_info_15_opcode_15_wd = reg_wdata[7:0]; + + assign cmd_info_15_addr_mode_15_wd = reg_wdata[9:8]; + + assign cmd_info_15_addr_swap_en_15_wd = reg_wdata[10]; + + assign cmd_info_15_mbyte_en_15_wd = reg_wdata[11]; + + assign cmd_info_15_dummy_size_15_wd = reg_wdata[14:12]; + + assign cmd_info_15_dummy_en_15_wd = reg_wdata[15]; + + assign cmd_info_15_payload_en_15_wd = reg_wdata[19:16]; + + assign cmd_info_15_payload_dir_15_wd = reg_wdata[20]; + + assign cmd_info_15_payload_swap_en_15_wd = reg_wdata[21]; + + assign cmd_info_15_read_pipeline_mode_15_wd = reg_wdata[23:22]; + + assign cmd_info_15_upload_15_wd = reg_wdata[24]; + + assign cmd_info_15_busy_15_wd = reg_wdata[25]; + + assign cmd_info_15_valid_15_wd = reg_wdata[31]; + + assign cmd_info_16_we = racl_addr_hit_write[47] & reg_we & !reg_error; + + assign cmd_info_16_opcode_16_wd = reg_wdata[7:0]; + + assign cmd_info_16_addr_mode_16_wd = reg_wdata[9:8]; + + assign cmd_info_16_addr_swap_en_16_wd = reg_wdata[10]; + + assign cmd_info_16_mbyte_en_16_wd = reg_wdata[11]; + + assign cmd_info_16_dummy_size_16_wd = reg_wdata[14:12]; + + assign cmd_info_16_dummy_en_16_wd = reg_wdata[15]; + + assign cmd_info_16_payload_en_16_wd = reg_wdata[19:16]; + + assign cmd_info_16_payload_dir_16_wd = reg_wdata[20]; + + assign cmd_info_16_payload_swap_en_16_wd = reg_wdata[21]; + + assign cmd_info_16_read_pipeline_mode_16_wd = reg_wdata[23:22]; + + assign cmd_info_16_upload_16_wd = reg_wdata[24]; + + assign cmd_info_16_busy_16_wd = reg_wdata[25]; + + assign cmd_info_16_valid_16_wd = reg_wdata[31]; + + assign cmd_info_17_we = racl_addr_hit_write[48] & reg_we & !reg_error; + + assign cmd_info_17_opcode_17_wd = reg_wdata[7:0]; + + assign cmd_info_17_addr_mode_17_wd = reg_wdata[9:8]; + + assign cmd_info_17_addr_swap_en_17_wd = reg_wdata[10]; + + assign cmd_info_17_mbyte_en_17_wd = reg_wdata[11]; + + assign cmd_info_17_dummy_size_17_wd = reg_wdata[14:12]; + + assign cmd_info_17_dummy_en_17_wd = reg_wdata[15]; + + assign cmd_info_17_payload_en_17_wd = reg_wdata[19:16]; + + assign cmd_info_17_payload_dir_17_wd = reg_wdata[20]; + + assign cmd_info_17_payload_swap_en_17_wd = reg_wdata[21]; + + assign cmd_info_17_read_pipeline_mode_17_wd = reg_wdata[23:22]; + + assign cmd_info_17_upload_17_wd = reg_wdata[24]; + + assign cmd_info_17_busy_17_wd = reg_wdata[25]; + + assign cmd_info_17_valid_17_wd = reg_wdata[31]; + + assign cmd_info_18_we = racl_addr_hit_write[49] & reg_we & !reg_error; + + assign cmd_info_18_opcode_18_wd = reg_wdata[7:0]; + + assign cmd_info_18_addr_mode_18_wd = reg_wdata[9:8]; + + assign cmd_info_18_addr_swap_en_18_wd = reg_wdata[10]; + + assign cmd_info_18_mbyte_en_18_wd = reg_wdata[11]; + + assign cmd_info_18_dummy_size_18_wd = reg_wdata[14:12]; + + assign cmd_info_18_dummy_en_18_wd = reg_wdata[15]; + + assign cmd_info_18_payload_en_18_wd = reg_wdata[19:16]; + + assign cmd_info_18_payload_dir_18_wd = reg_wdata[20]; + + assign cmd_info_18_payload_swap_en_18_wd = reg_wdata[21]; + + assign cmd_info_18_read_pipeline_mode_18_wd = reg_wdata[23:22]; + + assign cmd_info_18_upload_18_wd = reg_wdata[24]; + + assign cmd_info_18_busy_18_wd = reg_wdata[25]; + + assign cmd_info_18_valid_18_wd = reg_wdata[31]; + + assign cmd_info_19_we = racl_addr_hit_write[50] & reg_we & !reg_error; + + assign cmd_info_19_opcode_19_wd = reg_wdata[7:0]; + + assign cmd_info_19_addr_mode_19_wd = reg_wdata[9:8]; + + assign cmd_info_19_addr_swap_en_19_wd = reg_wdata[10]; + + assign cmd_info_19_mbyte_en_19_wd = reg_wdata[11]; + + assign cmd_info_19_dummy_size_19_wd = reg_wdata[14:12]; + + assign cmd_info_19_dummy_en_19_wd = reg_wdata[15]; + + assign cmd_info_19_payload_en_19_wd = reg_wdata[19:16]; + + assign cmd_info_19_payload_dir_19_wd = reg_wdata[20]; + + assign cmd_info_19_payload_swap_en_19_wd = reg_wdata[21]; + + assign cmd_info_19_read_pipeline_mode_19_wd = reg_wdata[23:22]; + + assign cmd_info_19_upload_19_wd = reg_wdata[24]; + + assign cmd_info_19_busy_19_wd = reg_wdata[25]; + + assign cmd_info_19_valid_19_wd = reg_wdata[31]; + + assign cmd_info_20_we = racl_addr_hit_write[51] & reg_we & !reg_error; + + assign cmd_info_20_opcode_20_wd = reg_wdata[7:0]; + + assign cmd_info_20_addr_mode_20_wd = reg_wdata[9:8]; + + assign cmd_info_20_addr_swap_en_20_wd = reg_wdata[10]; + + assign cmd_info_20_mbyte_en_20_wd = reg_wdata[11]; + + assign cmd_info_20_dummy_size_20_wd = reg_wdata[14:12]; + + assign cmd_info_20_dummy_en_20_wd = reg_wdata[15]; + + assign cmd_info_20_payload_en_20_wd = reg_wdata[19:16]; + + assign cmd_info_20_payload_dir_20_wd = reg_wdata[20]; + + assign cmd_info_20_payload_swap_en_20_wd = reg_wdata[21]; + + assign cmd_info_20_read_pipeline_mode_20_wd = reg_wdata[23:22]; + + assign cmd_info_20_upload_20_wd = reg_wdata[24]; + + assign cmd_info_20_busy_20_wd = reg_wdata[25]; + + assign cmd_info_20_valid_20_wd = reg_wdata[31]; + + assign cmd_info_21_we = racl_addr_hit_write[52] & reg_we & !reg_error; + + assign cmd_info_21_opcode_21_wd = reg_wdata[7:0]; + + assign cmd_info_21_addr_mode_21_wd = reg_wdata[9:8]; + + assign cmd_info_21_addr_swap_en_21_wd = reg_wdata[10]; + + assign cmd_info_21_mbyte_en_21_wd = reg_wdata[11]; + + assign cmd_info_21_dummy_size_21_wd = reg_wdata[14:12]; + + assign cmd_info_21_dummy_en_21_wd = reg_wdata[15]; + + assign cmd_info_21_payload_en_21_wd = reg_wdata[19:16]; + + assign cmd_info_21_payload_dir_21_wd = reg_wdata[20]; + + assign cmd_info_21_payload_swap_en_21_wd = reg_wdata[21]; + + assign cmd_info_21_read_pipeline_mode_21_wd = reg_wdata[23:22]; + + assign cmd_info_21_upload_21_wd = reg_wdata[24]; + + assign cmd_info_21_busy_21_wd = reg_wdata[25]; + + assign cmd_info_21_valid_21_wd = reg_wdata[31]; + + assign cmd_info_22_we = racl_addr_hit_write[53] & reg_we & !reg_error; + + assign cmd_info_22_opcode_22_wd = reg_wdata[7:0]; + + assign cmd_info_22_addr_mode_22_wd = reg_wdata[9:8]; + + assign cmd_info_22_addr_swap_en_22_wd = reg_wdata[10]; + + assign cmd_info_22_mbyte_en_22_wd = reg_wdata[11]; + + assign cmd_info_22_dummy_size_22_wd = reg_wdata[14:12]; + + assign cmd_info_22_dummy_en_22_wd = reg_wdata[15]; + + assign cmd_info_22_payload_en_22_wd = reg_wdata[19:16]; + + assign cmd_info_22_payload_dir_22_wd = reg_wdata[20]; + + assign cmd_info_22_payload_swap_en_22_wd = reg_wdata[21]; + + assign cmd_info_22_read_pipeline_mode_22_wd = reg_wdata[23:22]; + + assign cmd_info_22_upload_22_wd = reg_wdata[24]; + + assign cmd_info_22_busy_22_wd = reg_wdata[25]; + + assign cmd_info_22_valid_22_wd = reg_wdata[31]; + + assign cmd_info_23_we = racl_addr_hit_write[54] & reg_we & !reg_error; + + assign cmd_info_23_opcode_23_wd = reg_wdata[7:0]; + + assign cmd_info_23_addr_mode_23_wd = reg_wdata[9:8]; + + assign cmd_info_23_addr_swap_en_23_wd = reg_wdata[10]; + + assign cmd_info_23_mbyte_en_23_wd = reg_wdata[11]; + + assign cmd_info_23_dummy_size_23_wd = reg_wdata[14:12]; + + assign cmd_info_23_dummy_en_23_wd = reg_wdata[15]; + + assign cmd_info_23_payload_en_23_wd = reg_wdata[19:16]; + + assign cmd_info_23_payload_dir_23_wd = reg_wdata[20]; + + assign cmd_info_23_payload_swap_en_23_wd = reg_wdata[21]; + + assign cmd_info_23_read_pipeline_mode_23_wd = reg_wdata[23:22]; + + assign cmd_info_23_upload_23_wd = reg_wdata[24]; + + assign cmd_info_23_busy_23_wd = reg_wdata[25]; + + assign cmd_info_23_valid_23_wd = reg_wdata[31]; + + assign cmd_info_en4b_we = racl_addr_hit_write[55] & reg_we & !reg_error; + + assign cmd_info_en4b_opcode_wd = reg_wdata[7:0]; + + assign cmd_info_en4b_valid_wd = reg_wdata[31]; + + assign cmd_info_ex4b_we = racl_addr_hit_write[56] & reg_we & !reg_error; + + assign cmd_info_ex4b_opcode_wd = reg_wdata[7:0]; + + assign cmd_info_ex4b_valid_wd = reg_wdata[31]; + + assign cmd_info_wren_we = racl_addr_hit_write[57] & reg_we & !reg_error; + + assign cmd_info_wren_opcode_wd = reg_wdata[7:0]; + + assign cmd_info_wren_valid_wd = reg_wdata[31]; + + assign cmd_info_wrdi_we = racl_addr_hit_write[58] & reg_we & !reg_error; + + assign cmd_info_wrdi_opcode_wd = reg_wdata[7:0]; + + assign cmd_info_wrdi_valid_wd = reg_wdata[31]; + + assign tpm_cfg_we = racl_addr_hit_write[60] & reg_we & !reg_error; + + assign tpm_cfg_en_wd = reg_wdata[0]; + + assign tpm_cfg_tpm_mode_wd = reg_wdata[1]; + + assign tpm_cfg_hw_reg_dis_wd = reg_wdata[2]; + + assign tpm_cfg_tpm_reg_chk_dis_wd = reg_wdata[3]; + + assign tpm_cfg_invalid_locality_wd = reg_wdata[4]; + + assign tpm_status_re = racl_addr_hit_read[61] & reg_re & !reg_error; + assign tpm_status_we = racl_addr_hit_write[61] & reg_we & !reg_error; + + assign tpm_status_wrfifo_pending_wd = reg_wdata[1]; + + assign tpm_access_0_we = racl_addr_hit_write[62] & reg_we & !reg_error; + + assign tpm_access_0_access_0_wd = reg_wdata[7:0]; + + assign tpm_access_0_access_1_wd = reg_wdata[15:8]; + + assign tpm_access_0_access_2_wd = reg_wdata[23:16]; + + assign tpm_access_0_access_3_wd = reg_wdata[31:24]; + + assign tpm_access_1_we = racl_addr_hit_write[63] & reg_we & !reg_error; + + assign tpm_access_1_wd = reg_wdata[7:0]; + + assign tpm_sts_we = racl_addr_hit_write[64] & reg_we & !reg_error; + + assign tpm_sts_wd = reg_wdata[31:0]; + + assign tpm_intf_capability_we = racl_addr_hit_write[65] & reg_we & !reg_error; + + assign tpm_intf_capability_wd = reg_wdata[31:0]; + + assign tpm_int_enable_we = racl_addr_hit_write[66] & reg_we & !reg_error; + + assign tpm_int_enable_wd = reg_wdata[31:0]; + + assign tpm_int_vector_we = racl_addr_hit_write[67] & reg_we & !reg_error; + + assign tpm_int_vector_wd = reg_wdata[7:0]; + + assign tpm_int_status_we = racl_addr_hit_write[68] & reg_we & !reg_error; + + assign tpm_int_status_wd = reg_wdata[31:0]; + + assign tpm_did_vid_we = racl_addr_hit_write[69] & reg_we & !reg_error; + + assign tpm_did_vid_vid_wd = reg_wdata[15:0]; + + assign tpm_did_vid_did_wd = reg_wdata[31:16]; + + assign tpm_rid_we = racl_addr_hit_write[70] & reg_we & !reg_error; + + assign tpm_rid_wd = reg_wdata[7:0]; + + assign tpm_cmd_addr_re = racl_addr_hit_read[71] & reg_re & !reg_error; + assign tpm_read_fifo_we = racl_addr_hit_write[72] & reg_we & !reg_error; + + assign tpm_read_fifo_wd = reg_wdata[31:0]; + + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = control_we; + reg_we_check[5] = cfg_we; + reg_we_check[6] = 1'b0; + reg_we_check[7] = intercept_en_we; + reg_we_check[8] = addr_mode_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = flash_status_we; + reg_we_check[11] = jedec_cc_we; + reg_we_check[12] = jedec_id_we; + reg_we_check[13] = read_threshold_we; + reg_we_check[14] = mailbox_addr_we; + reg_we_check[15] = 1'b0; + reg_we_check[16] = 1'b0; + reg_we_check[17] = 1'b0; + reg_we_check[18] = 1'b0; + reg_we_check[19] = cmd_filter_0_we; + reg_we_check[20] = cmd_filter_1_we; + reg_we_check[21] = cmd_filter_2_we; + reg_we_check[22] = cmd_filter_3_we; + reg_we_check[23] = cmd_filter_4_we; + reg_we_check[24] = cmd_filter_5_we; + reg_we_check[25] = cmd_filter_6_we; + reg_we_check[26] = cmd_filter_7_we; + reg_we_check[27] = addr_swap_mask_we; + reg_we_check[28] = addr_swap_data_we; + reg_we_check[29] = payload_swap_mask_we; + reg_we_check[30] = payload_swap_data_we; + reg_we_check[31] = cmd_info_0_we; + reg_we_check[32] = cmd_info_1_we; + reg_we_check[33] = cmd_info_2_we; + reg_we_check[34] = cmd_info_3_we; + reg_we_check[35] = cmd_info_4_we; + reg_we_check[36] = cmd_info_5_we; + reg_we_check[37] = cmd_info_6_we; + reg_we_check[38] = cmd_info_7_we; + reg_we_check[39] = cmd_info_8_we; + reg_we_check[40] = cmd_info_9_we; + reg_we_check[41] = cmd_info_10_we; + reg_we_check[42] = cmd_info_11_we; + reg_we_check[43] = cmd_info_12_we; + reg_we_check[44] = cmd_info_13_we; + reg_we_check[45] = cmd_info_14_we; + reg_we_check[46] = cmd_info_15_we; + reg_we_check[47] = cmd_info_16_we; + reg_we_check[48] = cmd_info_17_we; + reg_we_check[49] = cmd_info_18_we; + reg_we_check[50] = cmd_info_19_we; + reg_we_check[51] = cmd_info_20_we; + reg_we_check[52] = cmd_info_21_we; + reg_we_check[53] = cmd_info_22_we; + reg_we_check[54] = cmd_info_23_we; + reg_we_check[55] = cmd_info_en4b_we; + reg_we_check[56] = cmd_info_ex4b_we; + reg_we_check[57] = cmd_info_wren_we; + reg_we_check[58] = cmd_info_wrdi_we; + reg_we_check[59] = 1'b0; + reg_we_check[60] = tpm_cfg_we; + reg_we_check[61] = tpm_status_we; + reg_we_check[62] = tpm_access_0_we; + reg_we_check[63] = tpm_access_1_we; + reg_we_check[64] = tpm_sts_we; + reg_we_check[65] = tpm_intf_capability_we; + reg_we_check[66] = tpm_int_enable_we; + reg_we_check[67] = tpm_int_vector_we; + reg_we_check[68] = tpm_int_status_we; + reg_we_check[69] = tpm_did_vid_we; + reg_we_check[70] = tpm_rid_we; + reg_we_check[71] = 1'b0; + reg_we_check[72] = tpm_read_fifo_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[0] = intr_state_upload_cmdfifo_not_empty_qs; + reg_rdata_next[1] = intr_state_upload_payload_not_empty_qs; + reg_rdata_next[2] = intr_state_upload_payload_overflow_qs; + reg_rdata_next[3] = intr_state_readbuf_watermark_qs; + reg_rdata_next[4] = intr_state_readbuf_flip_qs; + reg_rdata_next[5] = intr_state_tpm_header_not_empty_qs; + reg_rdata_next[6] = intr_state_tpm_rdfifo_cmd_end_qs; + reg_rdata_next[7] = intr_state_tpm_rdfifo_drop_qs; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[0] = intr_enable_upload_cmdfifo_not_empty_qs; + reg_rdata_next[1] = intr_enable_upload_payload_not_empty_qs; + reg_rdata_next[2] = intr_enable_upload_payload_overflow_qs; + reg_rdata_next[3] = intr_enable_readbuf_watermark_qs; + reg_rdata_next[4] = intr_enable_readbuf_flip_qs; + reg_rdata_next[5] = intr_enable_tpm_header_not_empty_qs; + reg_rdata_next[6] = intr_enable_tpm_rdfifo_cmd_end_qs; + reg_rdata_next[7] = intr_enable_tpm_rdfifo_drop_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[0] = '0; + end + + racl_addr_hit_read[4]: begin + reg_rdata_next[0] = control_flash_status_fifo_clr_qs; + reg_rdata_next[1] = control_flash_read_buffer_clr_qs; + reg_rdata_next[5:4] = control_mode_qs; + end + + racl_addr_hit_read[5]: begin + reg_rdata_next[2] = cfg_tx_order_qs; + reg_rdata_next[3] = cfg_rx_order_qs; + reg_rdata_next[24] = cfg_mailbox_en_qs; + end + + racl_addr_hit_read[6]: begin + reg_rdata_next[5] = status_csb_qs; + reg_rdata_next[6] = status_tpm_csb_qs; + end + + racl_addr_hit_read[7]: begin + reg_rdata_next[0] = intercept_en_status_qs; + reg_rdata_next[1] = intercept_en_jedec_qs; + reg_rdata_next[2] = intercept_en_sfdp_qs; + reg_rdata_next[3] = intercept_en_mbx_qs; + end + + racl_addr_hit_read[8]: begin + reg_rdata_next[0] = addr_mode_addr_4b_en_qs; + reg_rdata_next[31] = addr_mode_pending_qs; + end + + racl_addr_hit_read[9]: begin + reg_rdata_next[31:0] = last_read_addr_qs; + end + + racl_addr_hit_read[10]: begin + reg_rdata_next[0] = flash_status_busy_qs; + reg_rdata_next[1] = flash_status_wel_qs; + reg_rdata_next[23:2] = flash_status_status_qs; + end + + racl_addr_hit_read[11]: begin + reg_rdata_next[7:0] = jedec_cc_cc_qs; + reg_rdata_next[15:8] = jedec_cc_num_cc_qs; + end + + racl_addr_hit_read[12]: begin + reg_rdata_next[15:0] = jedec_id_id_qs; + reg_rdata_next[23:16] = jedec_id_mf_qs; + end + + racl_addr_hit_read[13]: begin + reg_rdata_next[9:0] = read_threshold_qs; + end + + racl_addr_hit_read[14]: begin + reg_rdata_next[31:0] = mailbox_addr_qs; + end + + racl_addr_hit_read[15]: begin + reg_rdata_next[4:0] = upload_status_cmdfifo_depth_qs; + reg_rdata_next[7] = upload_status_cmdfifo_notempty_qs; + reg_rdata_next[12:8] = upload_status_addrfifo_depth_qs; + reg_rdata_next[15] = upload_status_addrfifo_notempty_qs; + end + + racl_addr_hit_read[16]: begin + reg_rdata_next[8:0] = upload_status2_payload_depth_qs; + reg_rdata_next[23:16] = upload_status2_payload_start_idx_qs; + end + + racl_addr_hit_read[17]: begin + reg_rdata_next[7:0] = upload_cmdfifo_data_qs; + reg_rdata_next[13] = upload_cmdfifo_busy_qs; + reg_rdata_next[14] = upload_cmdfifo_wel_qs; + reg_rdata_next[15] = upload_cmdfifo_addr4b_mode_qs; + end + + racl_addr_hit_read[18]: begin + reg_rdata_next[31:0] = upload_addrfifo_qs; + end + + racl_addr_hit_read[19]: begin + reg_rdata_next[0] = cmd_filter_0_filter_0_qs; + reg_rdata_next[1] = cmd_filter_0_filter_1_qs; + reg_rdata_next[2] = cmd_filter_0_filter_2_qs; + reg_rdata_next[3] = cmd_filter_0_filter_3_qs; + reg_rdata_next[4] = cmd_filter_0_filter_4_qs; + reg_rdata_next[5] = cmd_filter_0_filter_5_qs; + reg_rdata_next[6] = cmd_filter_0_filter_6_qs; + reg_rdata_next[7] = cmd_filter_0_filter_7_qs; + reg_rdata_next[8] = cmd_filter_0_filter_8_qs; + reg_rdata_next[9] = cmd_filter_0_filter_9_qs; + reg_rdata_next[10] = cmd_filter_0_filter_10_qs; + reg_rdata_next[11] = cmd_filter_0_filter_11_qs; + reg_rdata_next[12] = cmd_filter_0_filter_12_qs; + reg_rdata_next[13] = cmd_filter_0_filter_13_qs; + reg_rdata_next[14] = cmd_filter_0_filter_14_qs; + reg_rdata_next[15] = cmd_filter_0_filter_15_qs; + reg_rdata_next[16] = cmd_filter_0_filter_16_qs; + reg_rdata_next[17] = cmd_filter_0_filter_17_qs; + reg_rdata_next[18] = cmd_filter_0_filter_18_qs; + reg_rdata_next[19] = cmd_filter_0_filter_19_qs; + reg_rdata_next[20] = cmd_filter_0_filter_20_qs; + reg_rdata_next[21] = cmd_filter_0_filter_21_qs; + reg_rdata_next[22] = cmd_filter_0_filter_22_qs; + reg_rdata_next[23] = cmd_filter_0_filter_23_qs; + reg_rdata_next[24] = cmd_filter_0_filter_24_qs; + reg_rdata_next[25] = cmd_filter_0_filter_25_qs; + reg_rdata_next[26] = cmd_filter_0_filter_26_qs; + reg_rdata_next[27] = cmd_filter_0_filter_27_qs; + reg_rdata_next[28] = cmd_filter_0_filter_28_qs; + reg_rdata_next[29] = cmd_filter_0_filter_29_qs; + reg_rdata_next[30] = cmd_filter_0_filter_30_qs; + reg_rdata_next[31] = cmd_filter_0_filter_31_qs; + end + + racl_addr_hit_read[20]: begin + reg_rdata_next[0] = cmd_filter_1_filter_32_qs; + reg_rdata_next[1] = cmd_filter_1_filter_33_qs; + reg_rdata_next[2] = cmd_filter_1_filter_34_qs; + reg_rdata_next[3] = cmd_filter_1_filter_35_qs; + reg_rdata_next[4] = cmd_filter_1_filter_36_qs; + reg_rdata_next[5] = cmd_filter_1_filter_37_qs; + reg_rdata_next[6] = cmd_filter_1_filter_38_qs; + reg_rdata_next[7] = cmd_filter_1_filter_39_qs; + reg_rdata_next[8] = cmd_filter_1_filter_40_qs; + reg_rdata_next[9] = cmd_filter_1_filter_41_qs; + reg_rdata_next[10] = cmd_filter_1_filter_42_qs; + reg_rdata_next[11] = cmd_filter_1_filter_43_qs; + reg_rdata_next[12] = cmd_filter_1_filter_44_qs; + reg_rdata_next[13] = cmd_filter_1_filter_45_qs; + reg_rdata_next[14] = cmd_filter_1_filter_46_qs; + reg_rdata_next[15] = cmd_filter_1_filter_47_qs; + reg_rdata_next[16] = cmd_filter_1_filter_48_qs; + reg_rdata_next[17] = cmd_filter_1_filter_49_qs; + reg_rdata_next[18] = cmd_filter_1_filter_50_qs; + reg_rdata_next[19] = cmd_filter_1_filter_51_qs; + reg_rdata_next[20] = cmd_filter_1_filter_52_qs; + reg_rdata_next[21] = cmd_filter_1_filter_53_qs; + reg_rdata_next[22] = cmd_filter_1_filter_54_qs; + reg_rdata_next[23] = cmd_filter_1_filter_55_qs; + reg_rdata_next[24] = cmd_filter_1_filter_56_qs; + reg_rdata_next[25] = cmd_filter_1_filter_57_qs; + reg_rdata_next[26] = cmd_filter_1_filter_58_qs; + reg_rdata_next[27] = cmd_filter_1_filter_59_qs; + reg_rdata_next[28] = cmd_filter_1_filter_60_qs; + reg_rdata_next[29] = cmd_filter_1_filter_61_qs; + reg_rdata_next[30] = cmd_filter_1_filter_62_qs; + reg_rdata_next[31] = cmd_filter_1_filter_63_qs; + end + + racl_addr_hit_read[21]: begin + reg_rdata_next[0] = cmd_filter_2_filter_64_qs; + reg_rdata_next[1] = cmd_filter_2_filter_65_qs; + reg_rdata_next[2] = cmd_filter_2_filter_66_qs; + reg_rdata_next[3] = cmd_filter_2_filter_67_qs; + reg_rdata_next[4] = cmd_filter_2_filter_68_qs; + reg_rdata_next[5] = cmd_filter_2_filter_69_qs; + reg_rdata_next[6] = cmd_filter_2_filter_70_qs; + reg_rdata_next[7] = cmd_filter_2_filter_71_qs; + reg_rdata_next[8] = cmd_filter_2_filter_72_qs; + reg_rdata_next[9] = cmd_filter_2_filter_73_qs; + reg_rdata_next[10] = cmd_filter_2_filter_74_qs; + reg_rdata_next[11] = cmd_filter_2_filter_75_qs; + reg_rdata_next[12] = cmd_filter_2_filter_76_qs; + reg_rdata_next[13] = cmd_filter_2_filter_77_qs; + reg_rdata_next[14] = cmd_filter_2_filter_78_qs; + reg_rdata_next[15] = cmd_filter_2_filter_79_qs; + reg_rdata_next[16] = cmd_filter_2_filter_80_qs; + reg_rdata_next[17] = cmd_filter_2_filter_81_qs; + reg_rdata_next[18] = cmd_filter_2_filter_82_qs; + reg_rdata_next[19] = cmd_filter_2_filter_83_qs; + reg_rdata_next[20] = cmd_filter_2_filter_84_qs; + reg_rdata_next[21] = cmd_filter_2_filter_85_qs; + reg_rdata_next[22] = cmd_filter_2_filter_86_qs; + reg_rdata_next[23] = cmd_filter_2_filter_87_qs; + reg_rdata_next[24] = cmd_filter_2_filter_88_qs; + reg_rdata_next[25] = cmd_filter_2_filter_89_qs; + reg_rdata_next[26] = cmd_filter_2_filter_90_qs; + reg_rdata_next[27] = cmd_filter_2_filter_91_qs; + reg_rdata_next[28] = cmd_filter_2_filter_92_qs; + reg_rdata_next[29] = cmd_filter_2_filter_93_qs; + reg_rdata_next[30] = cmd_filter_2_filter_94_qs; + reg_rdata_next[31] = cmd_filter_2_filter_95_qs; + end + + racl_addr_hit_read[22]: begin + reg_rdata_next[0] = cmd_filter_3_filter_96_qs; + reg_rdata_next[1] = cmd_filter_3_filter_97_qs; + reg_rdata_next[2] = cmd_filter_3_filter_98_qs; + reg_rdata_next[3] = cmd_filter_3_filter_99_qs; + reg_rdata_next[4] = cmd_filter_3_filter_100_qs; + reg_rdata_next[5] = cmd_filter_3_filter_101_qs; + reg_rdata_next[6] = cmd_filter_3_filter_102_qs; + reg_rdata_next[7] = cmd_filter_3_filter_103_qs; + reg_rdata_next[8] = cmd_filter_3_filter_104_qs; + reg_rdata_next[9] = cmd_filter_3_filter_105_qs; + reg_rdata_next[10] = cmd_filter_3_filter_106_qs; + reg_rdata_next[11] = cmd_filter_3_filter_107_qs; + reg_rdata_next[12] = cmd_filter_3_filter_108_qs; + reg_rdata_next[13] = cmd_filter_3_filter_109_qs; + reg_rdata_next[14] = cmd_filter_3_filter_110_qs; + reg_rdata_next[15] = cmd_filter_3_filter_111_qs; + reg_rdata_next[16] = cmd_filter_3_filter_112_qs; + reg_rdata_next[17] = cmd_filter_3_filter_113_qs; + reg_rdata_next[18] = cmd_filter_3_filter_114_qs; + reg_rdata_next[19] = cmd_filter_3_filter_115_qs; + reg_rdata_next[20] = cmd_filter_3_filter_116_qs; + reg_rdata_next[21] = cmd_filter_3_filter_117_qs; + reg_rdata_next[22] = cmd_filter_3_filter_118_qs; + reg_rdata_next[23] = cmd_filter_3_filter_119_qs; + reg_rdata_next[24] = cmd_filter_3_filter_120_qs; + reg_rdata_next[25] = cmd_filter_3_filter_121_qs; + reg_rdata_next[26] = cmd_filter_3_filter_122_qs; + reg_rdata_next[27] = cmd_filter_3_filter_123_qs; + reg_rdata_next[28] = cmd_filter_3_filter_124_qs; + reg_rdata_next[29] = cmd_filter_3_filter_125_qs; + reg_rdata_next[30] = cmd_filter_3_filter_126_qs; + reg_rdata_next[31] = cmd_filter_3_filter_127_qs; + end + + racl_addr_hit_read[23]: begin + reg_rdata_next[0] = cmd_filter_4_filter_128_qs; + reg_rdata_next[1] = cmd_filter_4_filter_129_qs; + reg_rdata_next[2] = cmd_filter_4_filter_130_qs; + reg_rdata_next[3] = cmd_filter_4_filter_131_qs; + reg_rdata_next[4] = cmd_filter_4_filter_132_qs; + reg_rdata_next[5] = cmd_filter_4_filter_133_qs; + reg_rdata_next[6] = cmd_filter_4_filter_134_qs; + reg_rdata_next[7] = cmd_filter_4_filter_135_qs; + reg_rdata_next[8] = cmd_filter_4_filter_136_qs; + reg_rdata_next[9] = cmd_filter_4_filter_137_qs; + reg_rdata_next[10] = cmd_filter_4_filter_138_qs; + reg_rdata_next[11] = cmd_filter_4_filter_139_qs; + reg_rdata_next[12] = cmd_filter_4_filter_140_qs; + reg_rdata_next[13] = cmd_filter_4_filter_141_qs; + reg_rdata_next[14] = cmd_filter_4_filter_142_qs; + reg_rdata_next[15] = cmd_filter_4_filter_143_qs; + reg_rdata_next[16] = cmd_filter_4_filter_144_qs; + reg_rdata_next[17] = cmd_filter_4_filter_145_qs; + reg_rdata_next[18] = cmd_filter_4_filter_146_qs; + reg_rdata_next[19] = cmd_filter_4_filter_147_qs; + reg_rdata_next[20] = cmd_filter_4_filter_148_qs; + reg_rdata_next[21] = cmd_filter_4_filter_149_qs; + reg_rdata_next[22] = cmd_filter_4_filter_150_qs; + reg_rdata_next[23] = cmd_filter_4_filter_151_qs; + reg_rdata_next[24] = cmd_filter_4_filter_152_qs; + reg_rdata_next[25] = cmd_filter_4_filter_153_qs; + reg_rdata_next[26] = cmd_filter_4_filter_154_qs; + reg_rdata_next[27] = cmd_filter_4_filter_155_qs; + reg_rdata_next[28] = cmd_filter_4_filter_156_qs; + reg_rdata_next[29] = cmd_filter_4_filter_157_qs; + reg_rdata_next[30] = cmd_filter_4_filter_158_qs; + reg_rdata_next[31] = cmd_filter_4_filter_159_qs; + end + + racl_addr_hit_read[24]: begin + reg_rdata_next[0] = cmd_filter_5_filter_160_qs; + reg_rdata_next[1] = cmd_filter_5_filter_161_qs; + reg_rdata_next[2] = cmd_filter_5_filter_162_qs; + reg_rdata_next[3] = cmd_filter_5_filter_163_qs; + reg_rdata_next[4] = cmd_filter_5_filter_164_qs; + reg_rdata_next[5] = cmd_filter_5_filter_165_qs; + reg_rdata_next[6] = cmd_filter_5_filter_166_qs; + reg_rdata_next[7] = cmd_filter_5_filter_167_qs; + reg_rdata_next[8] = cmd_filter_5_filter_168_qs; + reg_rdata_next[9] = cmd_filter_5_filter_169_qs; + reg_rdata_next[10] = cmd_filter_5_filter_170_qs; + reg_rdata_next[11] = cmd_filter_5_filter_171_qs; + reg_rdata_next[12] = cmd_filter_5_filter_172_qs; + reg_rdata_next[13] = cmd_filter_5_filter_173_qs; + reg_rdata_next[14] = cmd_filter_5_filter_174_qs; + reg_rdata_next[15] = cmd_filter_5_filter_175_qs; + reg_rdata_next[16] = cmd_filter_5_filter_176_qs; + reg_rdata_next[17] = cmd_filter_5_filter_177_qs; + reg_rdata_next[18] = cmd_filter_5_filter_178_qs; + reg_rdata_next[19] = cmd_filter_5_filter_179_qs; + reg_rdata_next[20] = cmd_filter_5_filter_180_qs; + reg_rdata_next[21] = cmd_filter_5_filter_181_qs; + reg_rdata_next[22] = cmd_filter_5_filter_182_qs; + reg_rdata_next[23] = cmd_filter_5_filter_183_qs; + reg_rdata_next[24] = cmd_filter_5_filter_184_qs; + reg_rdata_next[25] = cmd_filter_5_filter_185_qs; + reg_rdata_next[26] = cmd_filter_5_filter_186_qs; + reg_rdata_next[27] = cmd_filter_5_filter_187_qs; + reg_rdata_next[28] = cmd_filter_5_filter_188_qs; + reg_rdata_next[29] = cmd_filter_5_filter_189_qs; + reg_rdata_next[30] = cmd_filter_5_filter_190_qs; + reg_rdata_next[31] = cmd_filter_5_filter_191_qs; + end + + racl_addr_hit_read[25]: begin + reg_rdata_next[0] = cmd_filter_6_filter_192_qs; + reg_rdata_next[1] = cmd_filter_6_filter_193_qs; + reg_rdata_next[2] = cmd_filter_6_filter_194_qs; + reg_rdata_next[3] = cmd_filter_6_filter_195_qs; + reg_rdata_next[4] = cmd_filter_6_filter_196_qs; + reg_rdata_next[5] = cmd_filter_6_filter_197_qs; + reg_rdata_next[6] = cmd_filter_6_filter_198_qs; + reg_rdata_next[7] = cmd_filter_6_filter_199_qs; + reg_rdata_next[8] = cmd_filter_6_filter_200_qs; + reg_rdata_next[9] = cmd_filter_6_filter_201_qs; + reg_rdata_next[10] = cmd_filter_6_filter_202_qs; + reg_rdata_next[11] = cmd_filter_6_filter_203_qs; + reg_rdata_next[12] = cmd_filter_6_filter_204_qs; + reg_rdata_next[13] = cmd_filter_6_filter_205_qs; + reg_rdata_next[14] = cmd_filter_6_filter_206_qs; + reg_rdata_next[15] = cmd_filter_6_filter_207_qs; + reg_rdata_next[16] = cmd_filter_6_filter_208_qs; + reg_rdata_next[17] = cmd_filter_6_filter_209_qs; + reg_rdata_next[18] = cmd_filter_6_filter_210_qs; + reg_rdata_next[19] = cmd_filter_6_filter_211_qs; + reg_rdata_next[20] = cmd_filter_6_filter_212_qs; + reg_rdata_next[21] = cmd_filter_6_filter_213_qs; + reg_rdata_next[22] = cmd_filter_6_filter_214_qs; + reg_rdata_next[23] = cmd_filter_6_filter_215_qs; + reg_rdata_next[24] = cmd_filter_6_filter_216_qs; + reg_rdata_next[25] = cmd_filter_6_filter_217_qs; + reg_rdata_next[26] = cmd_filter_6_filter_218_qs; + reg_rdata_next[27] = cmd_filter_6_filter_219_qs; + reg_rdata_next[28] = cmd_filter_6_filter_220_qs; + reg_rdata_next[29] = cmd_filter_6_filter_221_qs; + reg_rdata_next[30] = cmd_filter_6_filter_222_qs; + reg_rdata_next[31] = cmd_filter_6_filter_223_qs; + end + + racl_addr_hit_read[26]: begin + reg_rdata_next[0] = cmd_filter_7_filter_224_qs; + reg_rdata_next[1] = cmd_filter_7_filter_225_qs; + reg_rdata_next[2] = cmd_filter_7_filter_226_qs; + reg_rdata_next[3] = cmd_filter_7_filter_227_qs; + reg_rdata_next[4] = cmd_filter_7_filter_228_qs; + reg_rdata_next[5] = cmd_filter_7_filter_229_qs; + reg_rdata_next[6] = cmd_filter_7_filter_230_qs; + reg_rdata_next[7] = cmd_filter_7_filter_231_qs; + reg_rdata_next[8] = cmd_filter_7_filter_232_qs; + reg_rdata_next[9] = cmd_filter_7_filter_233_qs; + reg_rdata_next[10] = cmd_filter_7_filter_234_qs; + reg_rdata_next[11] = cmd_filter_7_filter_235_qs; + reg_rdata_next[12] = cmd_filter_7_filter_236_qs; + reg_rdata_next[13] = cmd_filter_7_filter_237_qs; + reg_rdata_next[14] = cmd_filter_7_filter_238_qs; + reg_rdata_next[15] = cmd_filter_7_filter_239_qs; + reg_rdata_next[16] = cmd_filter_7_filter_240_qs; + reg_rdata_next[17] = cmd_filter_7_filter_241_qs; + reg_rdata_next[18] = cmd_filter_7_filter_242_qs; + reg_rdata_next[19] = cmd_filter_7_filter_243_qs; + reg_rdata_next[20] = cmd_filter_7_filter_244_qs; + reg_rdata_next[21] = cmd_filter_7_filter_245_qs; + reg_rdata_next[22] = cmd_filter_7_filter_246_qs; + reg_rdata_next[23] = cmd_filter_7_filter_247_qs; + reg_rdata_next[24] = cmd_filter_7_filter_248_qs; + reg_rdata_next[25] = cmd_filter_7_filter_249_qs; + reg_rdata_next[26] = cmd_filter_7_filter_250_qs; + reg_rdata_next[27] = cmd_filter_7_filter_251_qs; + reg_rdata_next[28] = cmd_filter_7_filter_252_qs; + reg_rdata_next[29] = cmd_filter_7_filter_253_qs; + reg_rdata_next[30] = cmd_filter_7_filter_254_qs; + reg_rdata_next[31] = cmd_filter_7_filter_255_qs; + end + + racl_addr_hit_read[27]: begin + reg_rdata_next[31:0] = addr_swap_mask_qs; + end + + racl_addr_hit_read[28]: begin + reg_rdata_next[31:0] = addr_swap_data_qs; + end + + racl_addr_hit_read[29]: begin + reg_rdata_next[31:0] = payload_swap_mask_qs; + end + + racl_addr_hit_read[30]: begin + reg_rdata_next[31:0] = payload_swap_data_qs; + end + + racl_addr_hit_read[31]: begin + reg_rdata_next[7:0] = cmd_info_0_opcode_0_qs; + reg_rdata_next[9:8] = cmd_info_0_addr_mode_0_qs; + reg_rdata_next[10] = cmd_info_0_addr_swap_en_0_qs; + reg_rdata_next[11] = cmd_info_0_mbyte_en_0_qs; + reg_rdata_next[14:12] = cmd_info_0_dummy_size_0_qs; + reg_rdata_next[15] = cmd_info_0_dummy_en_0_qs; + reg_rdata_next[19:16] = cmd_info_0_payload_en_0_qs; + reg_rdata_next[20] = cmd_info_0_payload_dir_0_qs; + reg_rdata_next[21] = cmd_info_0_payload_swap_en_0_qs; + reg_rdata_next[23:22] = cmd_info_0_read_pipeline_mode_0_qs; + reg_rdata_next[24] = cmd_info_0_upload_0_qs; + reg_rdata_next[25] = cmd_info_0_busy_0_qs; + reg_rdata_next[31] = cmd_info_0_valid_0_qs; + end + + racl_addr_hit_read[32]: begin + reg_rdata_next[7:0] = cmd_info_1_opcode_1_qs; + reg_rdata_next[9:8] = cmd_info_1_addr_mode_1_qs; + reg_rdata_next[10] = cmd_info_1_addr_swap_en_1_qs; + reg_rdata_next[11] = cmd_info_1_mbyte_en_1_qs; + reg_rdata_next[14:12] = cmd_info_1_dummy_size_1_qs; + reg_rdata_next[15] = cmd_info_1_dummy_en_1_qs; + reg_rdata_next[19:16] = cmd_info_1_payload_en_1_qs; + reg_rdata_next[20] = cmd_info_1_payload_dir_1_qs; + reg_rdata_next[21] = cmd_info_1_payload_swap_en_1_qs; + reg_rdata_next[23:22] = cmd_info_1_read_pipeline_mode_1_qs; + reg_rdata_next[24] = cmd_info_1_upload_1_qs; + reg_rdata_next[25] = cmd_info_1_busy_1_qs; + reg_rdata_next[31] = cmd_info_1_valid_1_qs; + end + + racl_addr_hit_read[33]: begin + reg_rdata_next[7:0] = cmd_info_2_opcode_2_qs; + reg_rdata_next[9:8] = cmd_info_2_addr_mode_2_qs; + reg_rdata_next[10] = cmd_info_2_addr_swap_en_2_qs; + reg_rdata_next[11] = cmd_info_2_mbyte_en_2_qs; + reg_rdata_next[14:12] = cmd_info_2_dummy_size_2_qs; + reg_rdata_next[15] = cmd_info_2_dummy_en_2_qs; + reg_rdata_next[19:16] = cmd_info_2_payload_en_2_qs; + reg_rdata_next[20] = cmd_info_2_payload_dir_2_qs; + reg_rdata_next[21] = cmd_info_2_payload_swap_en_2_qs; + reg_rdata_next[23:22] = cmd_info_2_read_pipeline_mode_2_qs; + reg_rdata_next[24] = cmd_info_2_upload_2_qs; + reg_rdata_next[25] = cmd_info_2_busy_2_qs; + reg_rdata_next[31] = cmd_info_2_valid_2_qs; + end + + racl_addr_hit_read[34]: begin + reg_rdata_next[7:0] = cmd_info_3_opcode_3_qs; + reg_rdata_next[9:8] = cmd_info_3_addr_mode_3_qs; + reg_rdata_next[10] = cmd_info_3_addr_swap_en_3_qs; + reg_rdata_next[11] = cmd_info_3_mbyte_en_3_qs; + reg_rdata_next[14:12] = cmd_info_3_dummy_size_3_qs; + reg_rdata_next[15] = cmd_info_3_dummy_en_3_qs; + reg_rdata_next[19:16] = cmd_info_3_payload_en_3_qs; + reg_rdata_next[20] = cmd_info_3_payload_dir_3_qs; + reg_rdata_next[21] = cmd_info_3_payload_swap_en_3_qs; + reg_rdata_next[23:22] = cmd_info_3_read_pipeline_mode_3_qs; + reg_rdata_next[24] = cmd_info_3_upload_3_qs; + reg_rdata_next[25] = cmd_info_3_busy_3_qs; + reg_rdata_next[31] = cmd_info_3_valid_3_qs; + end + + racl_addr_hit_read[35]: begin + reg_rdata_next[7:0] = cmd_info_4_opcode_4_qs; + reg_rdata_next[9:8] = cmd_info_4_addr_mode_4_qs; + reg_rdata_next[10] = cmd_info_4_addr_swap_en_4_qs; + reg_rdata_next[11] = cmd_info_4_mbyte_en_4_qs; + reg_rdata_next[14:12] = cmd_info_4_dummy_size_4_qs; + reg_rdata_next[15] = cmd_info_4_dummy_en_4_qs; + reg_rdata_next[19:16] = cmd_info_4_payload_en_4_qs; + reg_rdata_next[20] = cmd_info_4_payload_dir_4_qs; + reg_rdata_next[21] = cmd_info_4_payload_swap_en_4_qs; + reg_rdata_next[23:22] = cmd_info_4_read_pipeline_mode_4_qs; + reg_rdata_next[24] = cmd_info_4_upload_4_qs; + reg_rdata_next[25] = cmd_info_4_busy_4_qs; + reg_rdata_next[31] = cmd_info_4_valid_4_qs; + end + + racl_addr_hit_read[36]: begin + reg_rdata_next[7:0] = cmd_info_5_opcode_5_qs; + reg_rdata_next[9:8] = cmd_info_5_addr_mode_5_qs; + reg_rdata_next[10] = cmd_info_5_addr_swap_en_5_qs; + reg_rdata_next[11] = cmd_info_5_mbyte_en_5_qs; + reg_rdata_next[14:12] = cmd_info_5_dummy_size_5_qs; + reg_rdata_next[15] = cmd_info_5_dummy_en_5_qs; + reg_rdata_next[19:16] = cmd_info_5_payload_en_5_qs; + reg_rdata_next[20] = cmd_info_5_payload_dir_5_qs; + reg_rdata_next[21] = cmd_info_5_payload_swap_en_5_qs; + reg_rdata_next[23:22] = cmd_info_5_read_pipeline_mode_5_qs; + reg_rdata_next[24] = cmd_info_5_upload_5_qs; + reg_rdata_next[25] = cmd_info_5_busy_5_qs; + reg_rdata_next[31] = cmd_info_5_valid_5_qs; + end + + racl_addr_hit_read[37]: begin + reg_rdata_next[7:0] = cmd_info_6_opcode_6_qs; + reg_rdata_next[9:8] = cmd_info_6_addr_mode_6_qs; + reg_rdata_next[10] = cmd_info_6_addr_swap_en_6_qs; + reg_rdata_next[11] = cmd_info_6_mbyte_en_6_qs; + reg_rdata_next[14:12] = cmd_info_6_dummy_size_6_qs; + reg_rdata_next[15] = cmd_info_6_dummy_en_6_qs; + reg_rdata_next[19:16] = cmd_info_6_payload_en_6_qs; + reg_rdata_next[20] = cmd_info_6_payload_dir_6_qs; + reg_rdata_next[21] = cmd_info_6_payload_swap_en_6_qs; + reg_rdata_next[23:22] = cmd_info_6_read_pipeline_mode_6_qs; + reg_rdata_next[24] = cmd_info_6_upload_6_qs; + reg_rdata_next[25] = cmd_info_6_busy_6_qs; + reg_rdata_next[31] = cmd_info_6_valid_6_qs; + end + + racl_addr_hit_read[38]: begin + reg_rdata_next[7:0] = cmd_info_7_opcode_7_qs; + reg_rdata_next[9:8] = cmd_info_7_addr_mode_7_qs; + reg_rdata_next[10] = cmd_info_7_addr_swap_en_7_qs; + reg_rdata_next[11] = cmd_info_7_mbyte_en_7_qs; + reg_rdata_next[14:12] = cmd_info_7_dummy_size_7_qs; + reg_rdata_next[15] = cmd_info_7_dummy_en_7_qs; + reg_rdata_next[19:16] = cmd_info_7_payload_en_7_qs; + reg_rdata_next[20] = cmd_info_7_payload_dir_7_qs; + reg_rdata_next[21] = cmd_info_7_payload_swap_en_7_qs; + reg_rdata_next[23:22] = cmd_info_7_read_pipeline_mode_7_qs; + reg_rdata_next[24] = cmd_info_7_upload_7_qs; + reg_rdata_next[25] = cmd_info_7_busy_7_qs; + reg_rdata_next[31] = cmd_info_7_valid_7_qs; + end + + racl_addr_hit_read[39]: begin + reg_rdata_next[7:0] = cmd_info_8_opcode_8_qs; + reg_rdata_next[9:8] = cmd_info_8_addr_mode_8_qs; + reg_rdata_next[10] = cmd_info_8_addr_swap_en_8_qs; + reg_rdata_next[11] = cmd_info_8_mbyte_en_8_qs; + reg_rdata_next[14:12] = cmd_info_8_dummy_size_8_qs; + reg_rdata_next[15] = cmd_info_8_dummy_en_8_qs; + reg_rdata_next[19:16] = cmd_info_8_payload_en_8_qs; + reg_rdata_next[20] = cmd_info_8_payload_dir_8_qs; + reg_rdata_next[21] = cmd_info_8_payload_swap_en_8_qs; + reg_rdata_next[23:22] = cmd_info_8_read_pipeline_mode_8_qs; + reg_rdata_next[24] = cmd_info_8_upload_8_qs; + reg_rdata_next[25] = cmd_info_8_busy_8_qs; + reg_rdata_next[31] = cmd_info_8_valid_8_qs; + end + + racl_addr_hit_read[40]: begin + reg_rdata_next[7:0] = cmd_info_9_opcode_9_qs; + reg_rdata_next[9:8] = cmd_info_9_addr_mode_9_qs; + reg_rdata_next[10] = cmd_info_9_addr_swap_en_9_qs; + reg_rdata_next[11] = cmd_info_9_mbyte_en_9_qs; + reg_rdata_next[14:12] = cmd_info_9_dummy_size_9_qs; + reg_rdata_next[15] = cmd_info_9_dummy_en_9_qs; + reg_rdata_next[19:16] = cmd_info_9_payload_en_9_qs; + reg_rdata_next[20] = cmd_info_9_payload_dir_9_qs; + reg_rdata_next[21] = cmd_info_9_payload_swap_en_9_qs; + reg_rdata_next[23:22] = cmd_info_9_read_pipeline_mode_9_qs; + reg_rdata_next[24] = cmd_info_9_upload_9_qs; + reg_rdata_next[25] = cmd_info_9_busy_9_qs; + reg_rdata_next[31] = cmd_info_9_valid_9_qs; + end + + racl_addr_hit_read[41]: begin + reg_rdata_next[7:0] = cmd_info_10_opcode_10_qs; + reg_rdata_next[9:8] = cmd_info_10_addr_mode_10_qs; + reg_rdata_next[10] = cmd_info_10_addr_swap_en_10_qs; + reg_rdata_next[11] = cmd_info_10_mbyte_en_10_qs; + reg_rdata_next[14:12] = cmd_info_10_dummy_size_10_qs; + reg_rdata_next[15] = cmd_info_10_dummy_en_10_qs; + reg_rdata_next[19:16] = cmd_info_10_payload_en_10_qs; + reg_rdata_next[20] = cmd_info_10_payload_dir_10_qs; + reg_rdata_next[21] = cmd_info_10_payload_swap_en_10_qs; + reg_rdata_next[23:22] = cmd_info_10_read_pipeline_mode_10_qs; + reg_rdata_next[24] = cmd_info_10_upload_10_qs; + reg_rdata_next[25] = cmd_info_10_busy_10_qs; + reg_rdata_next[31] = cmd_info_10_valid_10_qs; + end + + racl_addr_hit_read[42]: begin + reg_rdata_next[7:0] = cmd_info_11_opcode_11_qs; + reg_rdata_next[9:8] = cmd_info_11_addr_mode_11_qs; + reg_rdata_next[10] = cmd_info_11_addr_swap_en_11_qs; + reg_rdata_next[11] = cmd_info_11_mbyte_en_11_qs; + reg_rdata_next[14:12] = cmd_info_11_dummy_size_11_qs; + reg_rdata_next[15] = cmd_info_11_dummy_en_11_qs; + reg_rdata_next[19:16] = cmd_info_11_payload_en_11_qs; + reg_rdata_next[20] = cmd_info_11_payload_dir_11_qs; + reg_rdata_next[21] = cmd_info_11_payload_swap_en_11_qs; + reg_rdata_next[23:22] = cmd_info_11_read_pipeline_mode_11_qs; + reg_rdata_next[24] = cmd_info_11_upload_11_qs; + reg_rdata_next[25] = cmd_info_11_busy_11_qs; + reg_rdata_next[31] = cmd_info_11_valid_11_qs; + end + + racl_addr_hit_read[43]: begin + reg_rdata_next[7:0] = cmd_info_12_opcode_12_qs; + reg_rdata_next[9:8] = cmd_info_12_addr_mode_12_qs; + reg_rdata_next[10] = cmd_info_12_addr_swap_en_12_qs; + reg_rdata_next[11] = cmd_info_12_mbyte_en_12_qs; + reg_rdata_next[14:12] = cmd_info_12_dummy_size_12_qs; + reg_rdata_next[15] = cmd_info_12_dummy_en_12_qs; + reg_rdata_next[19:16] = cmd_info_12_payload_en_12_qs; + reg_rdata_next[20] = cmd_info_12_payload_dir_12_qs; + reg_rdata_next[21] = cmd_info_12_payload_swap_en_12_qs; + reg_rdata_next[23:22] = cmd_info_12_read_pipeline_mode_12_qs; + reg_rdata_next[24] = cmd_info_12_upload_12_qs; + reg_rdata_next[25] = cmd_info_12_busy_12_qs; + reg_rdata_next[31] = cmd_info_12_valid_12_qs; + end + + racl_addr_hit_read[44]: begin + reg_rdata_next[7:0] = cmd_info_13_opcode_13_qs; + reg_rdata_next[9:8] = cmd_info_13_addr_mode_13_qs; + reg_rdata_next[10] = cmd_info_13_addr_swap_en_13_qs; + reg_rdata_next[11] = cmd_info_13_mbyte_en_13_qs; + reg_rdata_next[14:12] = cmd_info_13_dummy_size_13_qs; + reg_rdata_next[15] = cmd_info_13_dummy_en_13_qs; + reg_rdata_next[19:16] = cmd_info_13_payload_en_13_qs; + reg_rdata_next[20] = cmd_info_13_payload_dir_13_qs; + reg_rdata_next[21] = cmd_info_13_payload_swap_en_13_qs; + reg_rdata_next[23:22] = cmd_info_13_read_pipeline_mode_13_qs; + reg_rdata_next[24] = cmd_info_13_upload_13_qs; + reg_rdata_next[25] = cmd_info_13_busy_13_qs; + reg_rdata_next[31] = cmd_info_13_valid_13_qs; + end + + racl_addr_hit_read[45]: begin + reg_rdata_next[7:0] = cmd_info_14_opcode_14_qs; + reg_rdata_next[9:8] = cmd_info_14_addr_mode_14_qs; + reg_rdata_next[10] = cmd_info_14_addr_swap_en_14_qs; + reg_rdata_next[11] = cmd_info_14_mbyte_en_14_qs; + reg_rdata_next[14:12] = cmd_info_14_dummy_size_14_qs; + reg_rdata_next[15] = cmd_info_14_dummy_en_14_qs; + reg_rdata_next[19:16] = cmd_info_14_payload_en_14_qs; + reg_rdata_next[20] = cmd_info_14_payload_dir_14_qs; + reg_rdata_next[21] = cmd_info_14_payload_swap_en_14_qs; + reg_rdata_next[23:22] = cmd_info_14_read_pipeline_mode_14_qs; + reg_rdata_next[24] = cmd_info_14_upload_14_qs; + reg_rdata_next[25] = cmd_info_14_busy_14_qs; + reg_rdata_next[31] = cmd_info_14_valid_14_qs; + end + + racl_addr_hit_read[46]: begin + reg_rdata_next[7:0] = cmd_info_15_opcode_15_qs; + reg_rdata_next[9:8] = cmd_info_15_addr_mode_15_qs; + reg_rdata_next[10] = cmd_info_15_addr_swap_en_15_qs; + reg_rdata_next[11] = cmd_info_15_mbyte_en_15_qs; + reg_rdata_next[14:12] = cmd_info_15_dummy_size_15_qs; + reg_rdata_next[15] = cmd_info_15_dummy_en_15_qs; + reg_rdata_next[19:16] = cmd_info_15_payload_en_15_qs; + reg_rdata_next[20] = cmd_info_15_payload_dir_15_qs; + reg_rdata_next[21] = cmd_info_15_payload_swap_en_15_qs; + reg_rdata_next[23:22] = cmd_info_15_read_pipeline_mode_15_qs; + reg_rdata_next[24] = cmd_info_15_upload_15_qs; + reg_rdata_next[25] = cmd_info_15_busy_15_qs; + reg_rdata_next[31] = cmd_info_15_valid_15_qs; + end + + racl_addr_hit_read[47]: begin + reg_rdata_next[7:0] = cmd_info_16_opcode_16_qs; + reg_rdata_next[9:8] = cmd_info_16_addr_mode_16_qs; + reg_rdata_next[10] = cmd_info_16_addr_swap_en_16_qs; + reg_rdata_next[11] = cmd_info_16_mbyte_en_16_qs; + reg_rdata_next[14:12] = cmd_info_16_dummy_size_16_qs; + reg_rdata_next[15] = cmd_info_16_dummy_en_16_qs; + reg_rdata_next[19:16] = cmd_info_16_payload_en_16_qs; + reg_rdata_next[20] = cmd_info_16_payload_dir_16_qs; + reg_rdata_next[21] = cmd_info_16_payload_swap_en_16_qs; + reg_rdata_next[23:22] = cmd_info_16_read_pipeline_mode_16_qs; + reg_rdata_next[24] = cmd_info_16_upload_16_qs; + reg_rdata_next[25] = cmd_info_16_busy_16_qs; + reg_rdata_next[31] = cmd_info_16_valid_16_qs; + end + + racl_addr_hit_read[48]: begin + reg_rdata_next[7:0] = cmd_info_17_opcode_17_qs; + reg_rdata_next[9:8] = cmd_info_17_addr_mode_17_qs; + reg_rdata_next[10] = cmd_info_17_addr_swap_en_17_qs; + reg_rdata_next[11] = cmd_info_17_mbyte_en_17_qs; + reg_rdata_next[14:12] = cmd_info_17_dummy_size_17_qs; + reg_rdata_next[15] = cmd_info_17_dummy_en_17_qs; + reg_rdata_next[19:16] = cmd_info_17_payload_en_17_qs; + reg_rdata_next[20] = cmd_info_17_payload_dir_17_qs; + reg_rdata_next[21] = cmd_info_17_payload_swap_en_17_qs; + reg_rdata_next[23:22] = cmd_info_17_read_pipeline_mode_17_qs; + reg_rdata_next[24] = cmd_info_17_upload_17_qs; + reg_rdata_next[25] = cmd_info_17_busy_17_qs; + reg_rdata_next[31] = cmd_info_17_valid_17_qs; + end + + racl_addr_hit_read[49]: begin + reg_rdata_next[7:0] = cmd_info_18_opcode_18_qs; + reg_rdata_next[9:8] = cmd_info_18_addr_mode_18_qs; + reg_rdata_next[10] = cmd_info_18_addr_swap_en_18_qs; + reg_rdata_next[11] = cmd_info_18_mbyte_en_18_qs; + reg_rdata_next[14:12] = cmd_info_18_dummy_size_18_qs; + reg_rdata_next[15] = cmd_info_18_dummy_en_18_qs; + reg_rdata_next[19:16] = cmd_info_18_payload_en_18_qs; + reg_rdata_next[20] = cmd_info_18_payload_dir_18_qs; + reg_rdata_next[21] = cmd_info_18_payload_swap_en_18_qs; + reg_rdata_next[23:22] = cmd_info_18_read_pipeline_mode_18_qs; + reg_rdata_next[24] = cmd_info_18_upload_18_qs; + reg_rdata_next[25] = cmd_info_18_busy_18_qs; + reg_rdata_next[31] = cmd_info_18_valid_18_qs; + end + + racl_addr_hit_read[50]: begin + reg_rdata_next[7:0] = cmd_info_19_opcode_19_qs; + reg_rdata_next[9:8] = cmd_info_19_addr_mode_19_qs; + reg_rdata_next[10] = cmd_info_19_addr_swap_en_19_qs; + reg_rdata_next[11] = cmd_info_19_mbyte_en_19_qs; + reg_rdata_next[14:12] = cmd_info_19_dummy_size_19_qs; + reg_rdata_next[15] = cmd_info_19_dummy_en_19_qs; + reg_rdata_next[19:16] = cmd_info_19_payload_en_19_qs; + reg_rdata_next[20] = cmd_info_19_payload_dir_19_qs; + reg_rdata_next[21] = cmd_info_19_payload_swap_en_19_qs; + reg_rdata_next[23:22] = cmd_info_19_read_pipeline_mode_19_qs; + reg_rdata_next[24] = cmd_info_19_upload_19_qs; + reg_rdata_next[25] = cmd_info_19_busy_19_qs; + reg_rdata_next[31] = cmd_info_19_valid_19_qs; + end + + racl_addr_hit_read[51]: begin + reg_rdata_next[7:0] = cmd_info_20_opcode_20_qs; + reg_rdata_next[9:8] = cmd_info_20_addr_mode_20_qs; + reg_rdata_next[10] = cmd_info_20_addr_swap_en_20_qs; + reg_rdata_next[11] = cmd_info_20_mbyte_en_20_qs; + reg_rdata_next[14:12] = cmd_info_20_dummy_size_20_qs; + reg_rdata_next[15] = cmd_info_20_dummy_en_20_qs; + reg_rdata_next[19:16] = cmd_info_20_payload_en_20_qs; + reg_rdata_next[20] = cmd_info_20_payload_dir_20_qs; + reg_rdata_next[21] = cmd_info_20_payload_swap_en_20_qs; + reg_rdata_next[23:22] = cmd_info_20_read_pipeline_mode_20_qs; + reg_rdata_next[24] = cmd_info_20_upload_20_qs; + reg_rdata_next[25] = cmd_info_20_busy_20_qs; + reg_rdata_next[31] = cmd_info_20_valid_20_qs; + end + + racl_addr_hit_read[52]: begin + reg_rdata_next[7:0] = cmd_info_21_opcode_21_qs; + reg_rdata_next[9:8] = cmd_info_21_addr_mode_21_qs; + reg_rdata_next[10] = cmd_info_21_addr_swap_en_21_qs; + reg_rdata_next[11] = cmd_info_21_mbyte_en_21_qs; + reg_rdata_next[14:12] = cmd_info_21_dummy_size_21_qs; + reg_rdata_next[15] = cmd_info_21_dummy_en_21_qs; + reg_rdata_next[19:16] = cmd_info_21_payload_en_21_qs; + reg_rdata_next[20] = cmd_info_21_payload_dir_21_qs; + reg_rdata_next[21] = cmd_info_21_payload_swap_en_21_qs; + reg_rdata_next[23:22] = cmd_info_21_read_pipeline_mode_21_qs; + reg_rdata_next[24] = cmd_info_21_upload_21_qs; + reg_rdata_next[25] = cmd_info_21_busy_21_qs; + reg_rdata_next[31] = cmd_info_21_valid_21_qs; + end + + racl_addr_hit_read[53]: begin + reg_rdata_next[7:0] = cmd_info_22_opcode_22_qs; + reg_rdata_next[9:8] = cmd_info_22_addr_mode_22_qs; + reg_rdata_next[10] = cmd_info_22_addr_swap_en_22_qs; + reg_rdata_next[11] = cmd_info_22_mbyte_en_22_qs; + reg_rdata_next[14:12] = cmd_info_22_dummy_size_22_qs; + reg_rdata_next[15] = cmd_info_22_dummy_en_22_qs; + reg_rdata_next[19:16] = cmd_info_22_payload_en_22_qs; + reg_rdata_next[20] = cmd_info_22_payload_dir_22_qs; + reg_rdata_next[21] = cmd_info_22_payload_swap_en_22_qs; + reg_rdata_next[23:22] = cmd_info_22_read_pipeline_mode_22_qs; + reg_rdata_next[24] = cmd_info_22_upload_22_qs; + reg_rdata_next[25] = cmd_info_22_busy_22_qs; + reg_rdata_next[31] = cmd_info_22_valid_22_qs; + end + + racl_addr_hit_read[54]: begin + reg_rdata_next[7:0] = cmd_info_23_opcode_23_qs; + reg_rdata_next[9:8] = cmd_info_23_addr_mode_23_qs; + reg_rdata_next[10] = cmd_info_23_addr_swap_en_23_qs; + reg_rdata_next[11] = cmd_info_23_mbyte_en_23_qs; + reg_rdata_next[14:12] = cmd_info_23_dummy_size_23_qs; + reg_rdata_next[15] = cmd_info_23_dummy_en_23_qs; + reg_rdata_next[19:16] = cmd_info_23_payload_en_23_qs; + reg_rdata_next[20] = cmd_info_23_payload_dir_23_qs; + reg_rdata_next[21] = cmd_info_23_payload_swap_en_23_qs; + reg_rdata_next[23:22] = cmd_info_23_read_pipeline_mode_23_qs; + reg_rdata_next[24] = cmd_info_23_upload_23_qs; + reg_rdata_next[25] = cmd_info_23_busy_23_qs; + reg_rdata_next[31] = cmd_info_23_valid_23_qs; + end + + racl_addr_hit_read[55]: begin + reg_rdata_next[7:0] = cmd_info_en4b_opcode_qs; + reg_rdata_next[31] = cmd_info_en4b_valid_qs; + end + + racl_addr_hit_read[56]: begin + reg_rdata_next[7:0] = cmd_info_ex4b_opcode_qs; + reg_rdata_next[31] = cmd_info_ex4b_valid_qs; + end + + racl_addr_hit_read[57]: begin + reg_rdata_next[7:0] = cmd_info_wren_opcode_qs; + reg_rdata_next[31] = cmd_info_wren_valid_qs; + end + + racl_addr_hit_read[58]: begin + reg_rdata_next[7:0] = cmd_info_wrdi_opcode_qs; + reg_rdata_next[31] = cmd_info_wrdi_valid_qs; + end + + racl_addr_hit_read[59]: begin + reg_rdata_next[7:0] = tpm_cap_rev_qs; + reg_rdata_next[8] = tpm_cap_locality_qs; + reg_rdata_next[18:16] = tpm_cap_max_wr_size_qs; + reg_rdata_next[22:20] = tpm_cap_max_rd_size_qs; + end + + racl_addr_hit_read[60]: begin + reg_rdata_next[0] = tpm_cfg_en_qs; + reg_rdata_next[1] = tpm_cfg_tpm_mode_qs; + reg_rdata_next[2] = tpm_cfg_hw_reg_dis_qs; + reg_rdata_next[3] = tpm_cfg_tpm_reg_chk_dis_qs; + reg_rdata_next[4] = tpm_cfg_invalid_locality_qs; + end + + racl_addr_hit_read[61]: begin + reg_rdata_next[0] = tpm_status_cmdaddr_notempty_qs; + reg_rdata_next[1] = tpm_status_wrfifo_pending_qs; + reg_rdata_next[2] = tpm_status_rdfifo_aborted_qs; + end + + racl_addr_hit_read[62]: begin + reg_rdata_next[7:0] = tpm_access_0_access_0_qs; + reg_rdata_next[15:8] = tpm_access_0_access_1_qs; + reg_rdata_next[23:16] = tpm_access_0_access_2_qs; + reg_rdata_next[31:24] = tpm_access_0_access_3_qs; + end + + racl_addr_hit_read[63]: begin + reg_rdata_next[7:0] = tpm_access_1_qs; + end + + racl_addr_hit_read[64]: begin + reg_rdata_next[31:0] = tpm_sts_qs; + end + + racl_addr_hit_read[65]: begin + reg_rdata_next[31:0] = tpm_intf_capability_qs; + end + + racl_addr_hit_read[66]: begin + reg_rdata_next[31:0] = tpm_int_enable_qs; + end + + racl_addr_hit_read[67]: begin + reg_rdata_next[7:0] = tpm_int_vector_qs; + end + + racl_addr_hit_read[68]: begin + reg_rdata_next[31:0] = tpm_int_status_qs; + end + + racl_addr_hit_read[69]: begin + reg_rdata_next[15:0] = tpm_did_vid_vid_qs; + reg_rdata_next[31:16] = tpm_did_vid_did_qs; + end + + racl_addr_hit_read[70]: begin + reg_rdata_next[7:0] = tpm_rid_qs; + end + + racl_addr_hit_read[71]: begin + reg_rdata_next[23:0] = tpm_cmd_addr_addr_qs; + reg_rdata_next[31:24] = tpm_cmd_addr_cmd_qs; + end + + racl_addr_hit_read[72]: begin + reg_rdata_next[31:0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/rdl2ot/tests/snapshots/uart.rdl b/rdl2ot/tests/snapshots/uart.rdl index b290198..1cfce96 100644 --- a/rdl2ot/tests/snapshots/uart.rdl +++ b/rdl2ot/tests/snapshots/uart.rdl @@ -1,4 +1,13 @@ +`include "user_defined.rdl" + addrmap uart { + + signal { + desc = ""; + signalwidth = 0x1; + sigtype = SigType::Alert; + } FATAL_FAULT; + regfile signals { default sw = rw; reg { diff --git a/rdl2ot/tests/snapshots/uart_reg_top.sv b/rdl2ot/tests/snapshots/uart_reg_top.sv index e3e1918..e0e4d17 100644 --- a/rdl2ot/tests/snapshots/uart_reg_top.sv +++ b/rdl2ot/tests/snapshots/uart_reg_top.sv @@ -216,158 +216,221 @@ module uart_reg_top ( logic [23:0] timeout_ctrl_val_wd; logic timeout_ctrl_en_qs; logic timeout_ctrl_en_wd; - // Register instances // R[interrupt_state]: V(False) // F[tx_watermark]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_tx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_tx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_state.tx_watermark.de), .d (hw2reg.interrupt_state.tx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.tx_watermark.q), .ds (), + + // to register interface (read) .qs (interrupt_state_tx_watermark_qs) ); // F[rx_watermark]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_watermark.de), .d (hw2reg.interrupt_state.rx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_watermark.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_watermark_qs) ); // F[tx_empty]: 2:2 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_tx_empty ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_tx_empty_wd), + + // from internal hardware .de (hw2reg.interrupt_state.tx_empty.de), .d (hw2reg.interrupt_state.tx_empty.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.tx_empty.q), .ds (), + + // to register interface (read) .qs (interrupt_state_tx_empty_qs) ); // F[rx_overflow]: 3:3 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_overflow ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_overflow_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_overflow.de), .d (hw2reg.interrupt_state.rx_overflow.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_overflow.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_overflow_qs) ); // F[rx_frame_err]: 4:4 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_frame_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_frame_err_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_frame_err.de), .d (hw2reg.interrupt_state.rx_frame_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_frame_err.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_frame_err_qs) ); // F[rx_break_err]: 5:5 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_break_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_break_err_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_break_err.de), .d (hw2reg.interrupt_state.rx_break_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_break_err.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_break_err_qs) ); // F[rx_timeout]: 6:6 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_timeout ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_timeout_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_timeout.de), .d (hw2reg.interrupt_state.rx_timeout.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_timeout.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_timeout_qs) ); // F[rx_parity_err]: 7:7 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_state_rx_parity_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_state_we), .wd (interrupt_state_rx_parity_err_wd), + + // from internal hardware .de (hw2reg.interrupt_state.rx_parity_err.de), .d (hw2reg.interrupt_state.rx_parity_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_state.rx_parity_err.q), .ds (), + + // to register interface (read) .qs (interrupt_state_rx_parity_err_qs) ); @@ -375,153 +438,217 @@ module uart_reg_top ( // R[interrupt_enable]: V(False) // F[tx_watermark]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_tx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_tx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.tx_watermark.de), .d (hw2reg.interrupt_enable.tx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.tx_watermark.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_tx_watermark_qs) ); // F[rx_watermark]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_watermark.de), .d (hw2reg.interrupt_enable.rx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_watermark.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_watermark_qs) ); // F[tx_empty]: 2:2 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_tx_empty ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_tx_empty_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.tx_empty.de), .d (hw2reg.interrupt_enable.tx_empty.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.tx_empty.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_tx_empty_qs) ); // F[rx_overflow]: 3:3 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_overflow ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_overflow_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_overflow.de), .d (hw2reg.interrupt_enable.rx_overflow.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_overflow.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_overflow_qs) ); // F[rx_frame_err]: 4:4 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_frame_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_frame_err_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_frame_err.de), .d (hw2reg.interrupt_enable.rx_frame_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_frame_err.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_frame_err_qs) ); // F[rx_break_err]: 5:5 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_break_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_break_err_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_break_err.de), .d (hw2reg.interrupt_enable.rx_break_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_break_err.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_break_err_qs) ); // F[rx_timeout]: 6:6 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_timeout ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_timeout_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_timeout.de), .d (hw2reg.interrupt_enable.rx_timeout.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_timeout.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_timeout_qs) ); // F[rx_parity_err]: 7:7 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessW1C), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_enable_rx_parity_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_enable_we), .wd (interrupt_enable_rx_parity_err_wd), + + // from internal hardware .de (hw2reg.interrupt_enable.rx_parity_err.de), .d (hw2reg.interrupt_enable.rx_parity_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_enable.rx_parity_err.q), .ds (), + + // to register interface (read) .qs (interrupt_enable_rx_parity_err_qs) ); @@ -529,173 +656,245 @@ module uart_reg_top ( // R[interrupt_test]: V(False) // F[tx_watermark]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_tx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_tx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_test.tx_watermark.de), .d (hw2reg.interrupt_test.tx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.tx_watermark.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_watermark]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_watermark ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_watermark_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_watermark.de), .d (hw2reg.interrupt_test.rx_watermark.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_watermark.q), .ds (), + + // to register interface (read) .qs () ); // F[tx_empty]: 2:2 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_tx_empty ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_tx_empty_wd), + + // from internal hardware .de (hw2reg.interrupt_test.tx_empty.de), .d (hw2reg.interrupt_test.tx_empty.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.tx_empty.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_overflow]: 3:3 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_overflow ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_overflow_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_overflow.de), .d (hw2reg.interrupt_test.rx_overflow.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_overflow.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_frame_err]: 4:4 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_frame_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_frame_err_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_frame_err.de), .d (hw2reg.interrupt_test.rx_frame_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_frame_err.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_break_err]: 5:5 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_break_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_break_err_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_break_err.de), .d (hw2reg.interrupt_test.rx_break_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_break_err.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_timeout]: 6:6 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_timeout ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_timeout_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_timeout.de), .d (hw2reg.interrupt_test.rx_timeout.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_timeout.q), .ds (), + + // to register interface (read) .qs () ); // F[rx_parity_err]: 7:7 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_interrupt_test_rx_parity_err ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (interrupt_test_we), .wd (interrupt_test_rx_parity_err_wd), + + // from internal hardware .de (hw2reg.interrupt_test.rx_parity_err.de), .d (hw2reg.interrupt_test.rx_parity_err.d), + + // to internal hardware .qe (), .q (reg2hw.interrupt_test.rx_parity_err.q), .ds (), + + // to register interface (read) .qs () ); // R[alert_test]: V(False) prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (1'h0), .Mubi (1'b0) ) u_alert_test ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (alert_test_we), .wd (alert_test_wd), + + // from internal hardware .de (hw2reg.alert_test.de), .d (hw2reg.alert_test.d), + + // to internal hardware .qe (), .q (reg2hw.alert_test.q), .ds (), + + // to register interface (read) .qs () ); @@ -703,172 +902,244 @@ module uart_reg_top ( // R[ctrl]: V(False) // F[tx]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_tx ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_tx_wd), + + // from internal hardware .de (hw2reg.ctrl.tx.de), .d (hw2reg.ctrl.tx.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.tx.q), .ds (), + + // to register interface (read) .qs (ctrl_tx_qs) ); // F[rx]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_rx ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_rx_wd), + + // from internal hardware .de (hw2reg.ctrl.rx.de), .d (hw2reg.ctrl.rx.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.rx.q), .ds (), + + // to register interface (read) .qs (ctrl_rx_qs) ); // F[nf]: 2:2 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_nf ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_nf_wd), + + // from internal hardware .de (hw2reg.ctrl.nf.de), .d (hw2reg.ctrl.nf.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.nf.q), .ds (), + + // to register interface (read) .qs (ctrl_nf_qs) ); // F[slpbk]: 4:4 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_slpbk ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_slpbk_wd), + + // from internal hardware .de (hw2reg.ctrl.slpbk.de), .d (hw2reg.ctrl.slpbk.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.slpbk.q), .ds (), + + // to register interface (read) .qs (ctrl_slpbk_qs) ); // F[llpbk]: 5:5 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_llpbk ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_llpbk_wd), + + // from internal hardware .de (hw2reg.ctrl.llpbk.de), .d (hw2reg.ctrl.llpbk.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.llpbk.q), .ds (), + + // to register interface (read) .qs (ctrl_llpbk_qs) ); // F[parity_en]: 6:6 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_parity_en ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_parity_en_wd), + + // from internal hardware .de (hw2reg.ctrl.parity_en.de), .d (hw2reg.ctrl.parity_en.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.parity_en.q), .ds (), + + // to register interface (read) .qs (ctrl_parity_en_qs) ); // F[parity_odd]: 7:7 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ctrl_parity_odd ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_parity_odd_wd), + + // from internal hardware .de (hw2reg.ctrl.parity_odd.de), .d (hw2reg.ctrl.parity_odd.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.parity_odd.q), .ds (), + + // to register interface (read) .qs (ctrl_parity_odd_qs) ); // F[rxblvl]: 9:8 prim_subreg #( - .DW (2), + .DW (2), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (2'h0), .Mubi (1'b0) ) u_ctrl_rxblvl ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_rxblvl_wd), + + // from internal hardware .de (hw2reg.ctrl.rxblvl.de), .d (hw2reg.ctrl.rxblvl.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.rxblvl.q), .ds (), + + // to register interface (read) .qs (ctrl_rxblvl_qs) ); // F[nco]: 31:16 prim_subreg #( - .DW (16), + .DW (16), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (16'h0), .Mubi (1'b0) ) u_ctrl_nco ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ctrl_we), .wd (ctrl_nco_wd), + + // from internal hardware .de (hw2reg.ctrl.nco.de), .d (hw2reg.ctrl.nco.d), + + // to internal hardware .qe (), .q (reg2hw.ctrl.nco.q), .ds (), + + // to register interface (read) .qs (ctrl_nco_qs) ); @@ -876,155 +1147,219 @@ module uart_reg_top ( // R[status]: V(False) // F[txfull]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) ) u_status_txfull ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.txfull.de), .d (hw2reg.status.txfull.d), + + // to internal hardware .qe (), .q (reg2hw.status.txfull.q), .ds (), + + // to register interface (read) .qs (status_txfull_qs) ); // F[rxfull]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0), .Mubi (1'b0) ) u_status_rxfull ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.rxfull.de), .d (hw2reg.status.rxfull.d), + + // to internal hardware .qe (), .q (reg2hw.status.rxfull.q), .ds (), + + // to register interface (read) .qs (status_rxfull_qs) ); // F[txempty]: 2:2 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) ) u_status_txempty ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.txempty.de), .d (hw2reg.status.txempty.d), + + // to internal hardware .qe (), .q (reg2hw.status.txempty.q), .ds (), + + // to register interface (read) .qs (status_txempty_qs) ); // F[txidle]: 3:3 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) ) u_status_txidle ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.txidle.de), .d (hw2reg.status.txidle.d), + + // to internal hardware .qe (), .q (reg2hw.status.txidle.q), .ds (), + + // to register interface (read) .qs (status_txidle_qs) ); // F[rxidle]: 4:4 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) ) u_status_rxidle ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.rxidle.de), .d (hw2reg.status.rxidle.d), + + // to internal hardware .qe (), .q (reg2hw.status.rxidle.q), .ds (), + + // to register interface (read) .qs (status_rxidle_qs) ); // F[rxempty]: 5:5 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (1'h1), .Mubi (1'b0) ) u_status_rxempty ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.status.rxempty.de), .d (hw2reg.status.rxempty.d), + + // to internal hardware .qe (), .q (reg2hw.status.rxempty.q), .ds (), + + // to register interface (read) .qs (status_rxempty_qs) ); // R[rdata]: V(False) prim_subreg #( - .DW (8), + .DW (8), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (8'h0), .Mubi (1'b0) ) u_rdata ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.rdata.de), .d (hw2reg.rdata.d), + + // to internal hardware .qe (), .q (reg2hw.rdata.q), .ds (), + + // to register interface (read) .qs (rdata_qs) ); // R[wdata]: V(False) prim_subreg #( - .DW (8), + .DW (8), .SwAccess(prim_subreg_pkg::SwAccessWO), .RESVAL (8'h0), .Mubi (1'b0) ) u_wdata ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (wdata_we), .wd (wdata_wd), + + // from internal hardware .de (hw2reg.wdata.de), .d (hw2reg.wdata.d), + + // to internal hardware .qe (), .q (reg2hw.wdata.q), .ds (), + + // to register interface (read) .qs () ); @@ -1032,77 +1367,109 @@ module uart_reg_top ( // R[fifo_ctrl]: V(False) // F[rxrst]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_fifo_ctrl_rxrst ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (fifo_ctrl_we), .wd (fifo_ctrl_rxrst_wd), + + // from internal hardware .de (hw2reg.fifo_ctrl.rxrst.de), .d (hw2reg.fifo_ctrl.rxrst.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_ctrl.rxrst.q), .ds (), + + // to register interface (read) .qs (fifo_ctrl_rxrst_qs) ); // F[txrst]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_fifo_ctrl_txrst ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (fifo_ctrl_we), .wd (fifo_ctrl_txrst_wd), + + // from internal hardware .de (hw2reg.fifo_ctrl.txrst.de), .d (hw2reg.fifo_ctrl.txrst.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_ctrl.txrst.q), .ds (), + + // to register interface (read) .qs (fifo_ctrl_txrst_qs) ); // F[rxilvl]: 4:2 prim_subreg #( - .DW (3), + .DW (3), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (3'h0), .Mubi (1'b0) ) u_fifo_ctrl_rxilvl ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (fifo_ctrl_we), .wd (fifo_ctrl_rxilvl_wd), + + // from internal hardware .de (hw2reg.fifo_ctrl.rxilvl.de), .d (hw2reg.fifo_ctrl.rxilvl.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_ctrl.rxilvl.q), .ds (), + + // to register interface (read) .qs (fifo_ctrl_rxilvl_qs) ); // F[txilvl]: 6:5 prim_subreg #( - .DW (2), + .DW (2), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (2'h0), .Mubi (1'b0) ) u_fifo_ctrl_txilvl ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (fifo_ctrl_we), .wd (fifo_ctrl_txilvl_wd), + + // from internal hardware .de (hw2reg.fifo_ctrl.txilvl.de), .d (hw2reg.fifo_ctrl.txilvl.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_ctrl.txilvl.q), .ds (), + + // to register interface (read) .qs (fifo_ctrl_txilvl_qs) ); @@ -1110,39 +1477,55 @@ module uart_reg_top ( // R[fifo_status]: V(False) // F[txlvl]: 5:0 prim_subreg #( - .DW (6), + .DW (6), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (6'h0), .Mubi (1'b0) ) u_fifo_status_txlvl ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.fifo_status.txlvl.de), .d (hw2reg.fifo_status.txlvl.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_status.txlvl.q), .ds (), + + // to register interface (read) .qs (fifo_status_txlvl_qs) ); // F[rxlvl]: 21:16 prim_subreg #( - .DW (6), + .DW (6), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (6'h0), .Mubi (1'b0) ) u_fifo_status_rxlvl ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.fifo_status.rxlvl.de), .d (hw2reg.fifo_status.rxlvl.d), + + // to internal hardware .qe (), .q (reg2hw.fifo_status.rxlvl.q), .ds (), + + // to register interface (read) .qs (fifo_status_rxlvl_qs) ); @@ -1150,59 +1533,83 @@ module uart_reg_top ( // R[ovrd]: V(False) // F[txen]: 0:0 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ovrd_txen ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ovrd_we), .wd (ovrd_txen_wd), + + // from internal hardware .de (hw2reg.ovrd.txen.de), .d (hw2reg.ovrd.txen.d), + + // to internal hardware .qe (), .q (reg2hw.ovrd.txen.q), .ds (), + + // to register interface (read) .qs (ovrd_txen_qs) ); // F[txval]: 1:1 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_ovrd_txval ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (ovrd_we), .wd (ovrd_txval_wd), + + // from internal hardware .de (hw2reg.ovrd.txval.de), .d (hw2reg.ovrd.txval.d), + + // to internal hardware .qe (), .q (reg2hw.ovrd.txval.q), .ds (), + + // to register interface (read) .qs (ovrd_txval_qs) ); // R[val]: V(False) prim_subreg #( - .DW (16), + .DW (16), .SwAccess(prim_subreg_pkg::SwAccessRO), .RESVAL (16'h0), .Mubi (1'b0) ) u_val ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (1'b0), .wd ('0), + + // from internal hardware .de (hw2reg.val.de), .d (hw2reg.val.d), + + // to internal hardware .qe (), .q (reg2hw.val.q), .ds (), + + // to register interface (read) .qs (val_qs) ); @@ -1210,39 +1617,55 @@ module uart_reg_top ( // R[timeout_ctrl]: V(False) // F[val]: 23:0 prim_subreg #( - .DW (24), + .DW (24), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (24'h0), .Mubi (1'b0) ) u_timeout_ctrl_val ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (timeout_ctrl_we), .wd (timeout_ctrl_val_wd), + + // from internal hardware .de (hw2reg.timeout_ctrl.val.de), .d (hw2reg.timeout_ctrl.val.d), + + // to internal hardware .qe (), .q (reg2hw.timeout_ctrl.val.q), .ds (), + + // to register interface (read) .qs (timeout_ctrl_val_qs) ); // F[en]: 31:31 prim_subreg #( - .DW (1), + .DW (1), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (1'h0), .Mubi (1'b0) ) u_timeout_ctrl_en ( .clk_i (clk_i), .rst_ni (rst_ni), + + // from register interface .we (timeout_ctrl_we), .wd (timeout_ctrl_en_wd), + + // from internal hardware .de (hw2reg.timeout_ctrl.en.de), .d (hw2reg.timeout_ctrl.en.d), + + // to internal hardware .qe (), .q (reg2hw.timeout_ctrl.en.q), .ds (), + + // to register interface (read) .qs (timeout_ctrl_en_qs) ); @@ -1287,70 +1710,109 @@ module uart_reg_top ( // Generate write-enables assign interrupt_state_we = addr_hit[0] & reg_we & !reg_error; + assign interrupt_state_tx_watermark_wd = reg_wdata[0]; + assign interrupt_state_rx_watermark_wd = reg_wdata[1]; + assign interrupt_state_tx_empty_wd = reg_wdata[2]; + assign interrupt_state_rx_overflow_wd = reg_wdata[3]; + assign interrupt_state_rx_frame_err_wd = reg_wdata[4]; + assign interrupt_state_rx_break_err_wd = reg_wdata[5]; + assign interrupt_state_rx_timeout_wd = reg_wdata[6]; + assign interrupt_state_rx_parity_err_wd = reg_wdata[7]; - + assign interrupt_enable_we = addr_hit[1] & reg_we & !reg_error; + assign interrupt_enable_tx_watermark_wd = reg_wdata[0]; + assign interrupt_enable_rx_watermark_wd = reg_wdata[1]; + assign interrupt_enable_tx_empty_wd = reg_wdata[2]; + assign interrupt_enable_rx_overflow_wd = reg_wdata[3]; + assign interrupt_enable_rx_frame_err_wd = reg_wdata[4]; + assign interrupt_enable_rx_break_err_wd = reg_wdata[5]; + assign interrupt_enable_rx_timeout_wd = reg_wdata[6]; + assign interrupt_enable_rx_parity_err_wd = reg_wdata[7]; - + assign interrupt_test_we = addr_hit[2] & reg_we & !reg_error; + assign interrupt_test_tx_watermark_wd = reg_wdata[0]; + assign interrupt_test_rx_watermark_wd = reg_wdata[1]; + assign interrupt_test_tx_empty_wd = reg_wdata[2]; + assign interrupt_test_rx_overflow_wd = reg_wdata[3]; + assign interrupt_test_rx_frame_err_wd = reg_wdata[4]; + assign interrupt_test_rx_break_err_wd = reg_wdata[5]; + assign interrupt_test_rx_timeout_wd = reg_wdata[6]; + assign interrupt_test_rx_parity_err_wd = reg_wdata[7]; - + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + assign alert_test_wd = reg_wdata[0]; - + assign ctrl_we = addr_hit[4] & reg_we & !reg_error; + assign ctrl_tx_wd = reg_wdata[0]; + assign ctrl_rx_wd = reg_wdata[1]; + assign ctrl_nf_wd = reg_wdata[2]; + assign ctrl_slpbk_wd = reg_wdata[4]; + assign ctrl_llpbk_wd = reg_wdata[5]; + assign ctrl_parity_en_wd = reg_wdata[6]; + assign ctrl_parity_odd_wd = reg_wdata[7]; + assign ctrl_rxblvl_wd = reg_wdata[9:8]; + assign ctrl_nco_wd = reg_wdata[31:16]; - - - + assign wdata_we = addr_hit[7] & reg_we & !reg_error; + assign wdata_wd = reg_wdata[7:0]; - + assign fifo_ctrl_we = addr_hit[8] & reg_we & !reg_error; + assign fifo_ctrl_rxrst_wd = reg_wdata[0]; + assign fifo_ctrl_txrst_wd = reg_wdata[1]; + assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2]; + assign fifo_ctrl_txilvl_wd = reg_wdata[6:5]; - - + assign ovrd_we = addr_hit[10] & reg_we & !reg_error; + assign ovrd_txen_wd = reg_wdata[0]; + assign ovrd_txval_wd = reg_wdata[1]; - - + assign timeout_ctrl_we = addr_hit[12] & reg_we & !reg_error; + assign timeout_ctrl_val_wd = reg_wdata[23:0]; + assign timeout_ctrl_en_wd = reg_wdata[31]; - + // Assign write-enables to checker logic vector. always_comb begin diff --git a/rdl2ot/tests/snapshots/udp.rdl b/rdl2ot/tests/snapshots/udp.rdl new file mode 100644 index 0000000..0b730db --- /dev/null +++ b/rdl2ot/tests/snapshots/udp.rdl @@ -0,0 +1,192 @@ +/* Copyright lowRISC contributors (OpenTitan project). +* Licensed under the Apache License, Version 2.0; see LICENSE for details. +* SPDX-License-Identifier: Apache-2.0 +*/ + +`ifndef UDP_RDL +`define UDP_RDL + +/** + * 4-bits boolean values + */ +enum MultiBitBool4 { + True = 0x6; + False = 0x9; +}; + +/** + * 8-bits boolean values + */ +enum MultiBitBool8 { + True = 0x96; + False = 0x69; +}; + +/** + * 12-bits boolean values + */ +enum MultiBitBool12 { + True = 0x696; + False = 0x969; +}; + +/** + * 16-bits boolean values + */ +enum MultiBitBool16 { + True = 0x9696; + False = 0x6969; +}; + +/** + * 20-bits boolean values + */ +enum MultiBitBool20 { + True = 0x69696; + False = 0x96969; +}; + +/** + * 24-bits boolean values + */ +enum MultiBitBool24 { + True = 0x969696; + False = 0x696969; +}; + +/** + * 28-bits boolean values + */ +enum MultiBitBool28 { + True = 0x6969696; + False = 0x9696969; +}; + +/** + * 32-bits boolean values + */ +enum MultiBitBool32 { + True = 0x96969696; + False = 0x69696969; +}; + +/* + * The same as swwe, but supports multibit references. + */ +property mubi_swwe { + type = ref; + component = reg|field; +}; + +/** + * true if hardware uses `re` signal, which is latched signal of software read pulse. + * The standard SystemRDL property `swacc` cannot be used here because `swacc = hwre | swmod`. + */ +property hwre { + type = boolean; + component = reg; + default = false; +}; + +/** + * If it is true, the register will be implemented using the prim_subreg_shadow module. + * Shadow registers are a mechanism to guard sensitive registers against this specific + * type of attack. They come at a cost of increased area, and a modified SW interaction. + */ +property shadowed { + type = boolean; + component = reg; + default = false; +}; + +/* + * Indicates the register must cross to a different clock domain before use. + * The value shown here should correspond to one of the module's clocks. + */ +property async_clk { + type = ref; + component = reg; +}; +property async_rst { + type = ref; + component = reg; +}; + +/* + * If true, integrity bits are passed through directly from the memory. + */ +property integrity_bypass { + type = boolean; + component = mem; + default = false; +}; + +/* + * If true, this array was originally a compacted multi-register. + */ +property compacted { + type = boolean; + component = reg; + default = false; +}; + +/* + * Defines properties to be used inside signals. + * These will help to model the hjson fields: 'inter_signal_list', 'available_output_list', + * 'interrupt_list' and 'alert_list' as rdl signals. + */ +enum SigType { + None; + Interrupt; // Signal is an interrupt + Alert; // Signal is an alert + InterModReqRsp;// Signal is an inter module, with type=req_rsp + InterModReq; // Signal is an inter module, with type=uni and act=req + InterModRecv; // Signal is an inter module, with type=uni and act=recv + Output; // Signal is an output + Input; // Signal is an input + InOut; // Signal is input and/or output + Sync; // Signal is used for synchonization. i.e clock, reset. +}; + +property sigtype { + type = SigType; + component = signal; + default = SigType::None; +}; + +/* + * Defines the Inter-module signal's data structure. It is generally bundled into `struct packed` + * type. This `struct` is used with `package` for topgen tool to define the signal. + */ +property inter_mod_struct { + type = string; + component = signal; + default = "logic"; +}; +property inter_mod_package { + type = string; + component = signal; +}; + +enum BusProtocol { + TlUl; +}; + +enum BusDirection { + Host; + Device; +}; + +struct BusInterfaceCfg { + BusProtocol protocol; + BusDirection direction; + boolean racl_support; + string hier_path; +}; + +property bus_interface_cfg{ + type = BusInterfaceCfg; + component = addrmap; +}; + +`endif diff --git a/rdl2ot/tests/snapshots/user_defined.rdl b/rdl2ot/tests/snapshots/user_defined.rdl index 8aad102..4c21036 100644 --- a/rdl2ot/tests/snapshots/user_defined.rdl +++ b/rdl2ot/tests/snapshots/user_defined.rdl @@ -1,3 +1,5 @@ +`ifndef UDP_RDL +`define UDP_RDL enum MultiBitBool4 { True = 0x6; @@ -8,3 +10,23 @@ enum MultiBitBool8 { True = 0x96; False = 0x69; }; + +enum SigType { + None; + Interrupt; // Signal is an interrupt + Alert; // Signal is an alert + InterModReqRsp;// Signal is an inter module, with type=req_rsp + InterModReq; // Signal is an inter module, with type=uni and act=req + InterModRecv; // Signal is an inter module, with type=uni and act=recv + Output; // Signal is an output + Input; // Signal is an input + InOut; // Signal is input and/or output +}; + +property sigtype { + type = SigType; + component = signal; + default = SigType::None; +}; + +`endif diff --git a/rdl2ot/tests/test_rdl2ot.py b/rdl2ot/tests/test_rdl2ot.py index 82b0e4f..7f2c867 100644 --- a/rdl2ot/tests/test_rdl2ot.py +++ b/rdl2ot/tests/test_rdl2ot.py @@ -28,7 +28,7 @@ def _run_cli_tool(input_file_path: Path, output_dir_path: Path) -> subprocess.Co return subprocess.run(command, capture_output=True, text=True, check=False) # noqa: S603 -test_ips = ["lc_ctrl", "uart", "soc_strawberry"] +test_ips = ["lc_ctrl", "uart", "soc_strawberry", "spi_device", "mbx"] @pytest.mark.parametrize("ip_block", test_ips) diff --git a/rdlexporter/pyproject.toml b/rdlexporter/pyproject.toml index 2f53cf2..9be9311 100644 --- a/rdlexporter/pyproject.toml +++ b/rdlexporter/pyproject.toml @@ -4,13 +4,13 @@ [project] name = "rdlexporter" -version = "0.2.0" +version = "0.4.0" description = "Library to export rdl files" requires-python = ">=3.10" keywords = ["SystemRDL", "library", "exporter"] readme = "README.md" dependencies = [ - "systemrdl-compiler>=1.29", + "systemrdl-compiler~=1.32.1", ] authors = [ diff --git a/rdlexporter/src/rdlexporter/exporter.py b/rdlexporter/src/rdlexporter/exporter.py index 2930acf..6502e0c 100644 --- a/rdlexporter/src/rdlexporter/exporter.py +++ b/rdlexporter/src/rdlexporter/exporter.py @@ -9,11 +9,26 @@ from systemrdl import RDLCompiler from systemrdl.ast.cast import AssignmentCast -from systemrdl.ast.literals import BoolLiteral, BuiltinEnumLiteral, IntLiteral, StringLiteral +from systemrdl.ast.literals import ( + BoolLiteral, + BuiltinEnumLiteral, + EnumLiteral, + IntLiteral, + StringLiteral, +) from systemrdl.ast.references import InstRef -from systemrdl.component import AddressableComponent, Addrmap, Field, Mem, Reg -from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType +from systemrdl.component import ( + AddressableComponent, + Addrmap, + Field, + Mem, + Reg, + Signal, + VectorComponent, +) +from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType, UserEnum from systemrdl.rdltypes.user_enum import UserEnumMeta +from systemrdl.rdltypes.user_struct import UserStruct @dataclass @@ -38,13 +53,6 @@ def _indent(self) -> str: def _is_nested(self) -> bool: return self.indent_pos > 0 - def _get_field_limits(self, field: Field) -> (int, int): - return ( - (field.msb, field.lsb) - if isinstance(field.msb, int) - else (field.msb.get_value(), field.lsb.get_value()) - ) - def _get_offset(self, comp: AddressableComponent) -> str: if isinstance(comp.addr_offset, AssignmentCast): return f" @ 0x{comp.addr_offset.get_value():X}" @@ -74,27 +82,33 @@ def _emit_dynamic_assignment(self) -> None: expr = f"{left_expr} = {right_expr};\n" self.stream += self._indent() + expr - def _emit_property(self, properties: dict) -> None: + def _emit_user_struct(self, data: UserStruct) -> None: + self.stream += f"{data.type_name}'{{\n" + self.indent_pos += self.indent_width + self._emit_property(data.members, ":", ",") + # Dropping the trailing comma because Systemrdl doesn't like it. + self.stream = self.stream[:-2] + self.stream[-1] + self.indent_pos -= self.indent_width + self.stream += self._indent() + "};\n" + + def _emit_property(self, properties: dict, assign_op: str = "=", endline: str = ";") -> None: + handlers = [ + (UserEnumMeta, lambda obj: obj.type_name), + (BuiltinEnumLiteral, lambda obj: obj.val.name), + (StringLiteral, lambda obj: f'''"{obj.get_value()}"'''), + (BoolLiteral, lambda obj: str(obj.get_value()).lower()), + (IntLiteral, lambda obj: f"0x{obj.get_value():x}"), + (str, lambda obj: f'''"{obj}"'''), + (bool, lambda obj: str(obj).lower()), + (int, lambda obj: f"0x{obj:x}"), + (EnumLiteral, lambda obj: f"{type(obj.val).type_name}::{obj.val.name}"), + (UserEnum, lambda obj: f"{type(obj).type_name}::{obj.name}"), + (UserStruct, self._emit_user_struct), + (AccessType | OnReadType | OnWriteType, lambda obj: obj.name), + ] + for name, obj in properties.items(): - if isinstance(obj, UserEnumMeta): - val = obj.type_name - elif isinstance(obj, BuiltinEnumLiteral): - val = obj.val.name - elif isinstance(obj, AccessType | OnReadType | OnWriteType): - val = obj.name - elif isinstance(obj, StringLiteral): - val = f'''"{obj.get_value()}"''' - elif isinstance(obj, BoolLiteral): - val = str(obj.get_value()).lower() - elif isinstance(obj, IntLiteral): - val = f"0x{obj.get_value():x}" - elif isinstance(obj, str): - val = f'''"{obj}"''' - elif isinstance(obj, bool): - val = str(obj).lower() - elif isinstance(obj, int): - val = f"0x{obj:x}" - elif isinstance(obj, InstRef): + if isinstance(obj, InstRef): # This should be emited at a higher scope indicated by `ref_root._scope_name`. ref = obj.get_value() scope = ref.ref_root._scope_name or ref.ref_root.type_name # noqa: SLF001 @@ -106,11 +120,15 @@ def _emit_property(self, properties: dict) -> None: } ) continue + + for type_, handler in handlers: + if isinstance(obj, type_): + self.stream += self._indent() + f"{name} {assign_op} " + if val:= handler(obj): + self.stream += f"{val}{endline}\n" + break else: print(f"Warning: Type {type(obj)} not implemented, skipping it.") - continue - - self.stream += self._indent() + f"{name} = {val};\n" def _arrays(self, component: Reg) -> str: if not component.is_array: @@ -123,6 +141,17 @@ def _arrays(self, component: Reg) -> str: dim = self._get_register_array_dim(component) return f"[{dim}]" + def _vector(self, component: VectorComponent) -> str: + if component.msb is None and component.lsb is None: + return "" + + msb, lsb = ( + (component.msb, component.lsb) + if isinstance(component.msb, int) + else (component.msb.get_value(), component.lsb.get_value()) + ) + return f"[{msb}:{lsb}]" + def _emit_parameters(self, parameters: list) -> None: if not len(parameters): return @@ -130,7 +159,7 @@ def _emit_parameters(self, parameters: list) -> None: self.stream += "#(\n" self.indent_pos += self.indent_width for index, param in enumerate(parameters): - val = param.get_value() + val = param.get_value() or param._value # noqa: SLF001 if isinstance(val, int) or param.param_type.is_integer: type_ = "longint" else: @@ -157,6 +186,17 @@ def _emit_mem(self, mem: Mem) -> None: self.stream += f"{offset};\n" self.ast_path.pop() + def _emit_signal(self, signal: Signal) -> None: + self.ast_path.append(signal.inst_name) + self.stream += self._indent() + "signal " + self._emit_parameters(signal.parameters) + self.stream += "{\n" + self.indent_pos += self.indent_width + self._emit_property(signal.properties) + self.indent_pos -= self.indent_width + self.stream += self._indent() + f"}} {signal.inst_name}" + self._vector(signal) + ";\n" + self.ast_path.pop() + def _emit_field(self, field: Field) -> None: self.ast_path.append(field.inst_name) self.stream += self._indent() + "field " @@ -165,8 +205,7 @@ def _emit_field(self, field: Field) -> None: self.indent_pos += self.indent_width self._emit_property(field.properties) self.indent_pos -= self.indent_width - msb, lsb = self._get_field_limits(field) - self.stream += self._indent() + f"}} {field.inst_name}[{msb}:{lsb}];\n" + self.stream += self._indent() + f"}} {field.inst_name}" + self._vector(field) + ";\n" self.ast_path.pop() def _emit_register(self, register: Reg) -> None: @@ -195,6 +234,7 @@ def _emit_addrmap(self, name: str, addrmap: Addrmap) -> None: self._emit_parameters(addrmap.parameters) self.stream += "{\n" self.indent_pos += self.indent_width + self._emit_property(addrmap.properties) for child in addrmap.children: if isinstance(child, Reg): self._emit_register(child) @@ -202,10 +242,12 @@ def _emit_addrmap(self, name: str, addrmap: Addrmap) -> None: self._emit_addrmap(child.inst_name, child) elif isinstance(child, Mem): self._emit_mem(child) + elif isinstance(child, Signal): + self._emit_signal(child) else: self._raise_type_error(type(child)) - self._emit_dynamic_assignment() self.stream += "\n" + self._emit_dynamic_assignment() self.indent_pos -= self.indent_width self.stream += self._indent() + "}" diff --git a/rdlexporter/tests/snapshots/generic.rdl b/rdlexporter/tests/snapshots/generic.rdl index c72c78c..9052c4f 100644 --- a/rdlexporter/tests/snapshots/generic.rdl +++ b/rdlexporter/tests/snapshots/generic.rdl @@ -1,29 +1,47 @@ -addrmap generic #( +addrmap root #( longint Width = 86 ){ - reg { - field { - desc = "Enable the ip"; - sw = rw; - } EN[0:0]; - } CTRL_WEN @ 0x0; + udp_config = udp_struct'{ + name : "interface", + enable : true + }; + addrmap { + is_interface = true; + udp_config = udp_struct'{ + name : "racl", + enable : true + }; + reg { + field { + desc = "Enable the ip"; + sw = rw; + } EN[0:0]; + } CTRL_WEN @ 0x0; - reg { - field { - reset = 0x0; - swmod = true; - desc = "Enable the ip"; - } EN[0:0]; - field { - reset = 0x7; - swmod = false; - desc = "Define the mode."; - sw = rw; - onread = rclr; - onwrite = woset; - hw = rw; - } MODE[9:2]; - } CTRL[4] @ 0x4; - CTRL.MODE -> swwe = CTRL_WEN.EN; + signal { + desc = "Fire when fifo is empty."; + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } FIFO_EMPTY; + + reg { + field { + reset = 0x0; + swmod = true; + desc = "Enable the ip"; + } EN[0:0]; + field { + reset = 0x7; + swmod = false; + desc = "Define the mode."; + sw = rw; + onread = rclr; + onwrite = woset; + hw = rw; + } MODE[9:2]; + } CTRL[4] @ 0x4; + + CTRL.MODE -> swwe = CTRL_WEN.EN; + } GENERIC; }; diff --git a/rdlexporter/tests/snapshots/lc_ctrl.rdl b/rdlexporter/tests/snapshots/lc_ctrl.rdl index f0f1795..f71e697 100644 --- a/rdlexporter/tests/snapshots/lc_ctrl.rdl +++ b/rdlexporter/tests/snapshots/lc_ctrl.rdl @@ -123,7 +123,6 @@ addrmap lc_ctrl #( reset = 0x69; } MUTEX[7:0]; } CLAIM_TRANSITION_IF @ 0xC; - CLAIM_TRANSITION_IF.MUTEX -> swwe = CLAIM_TRANSITION_IF_REGWEN.REGWEN; external reg { desc = "Register write enable for the hardware mutex register."; @@ -145,7 +144,6 @@ addrmap lc_ctrl #( desc = "Start"; } START[0:0]; } TRANSITION_CMD @ 0x14; - TRANSITION_CMD.START -> swwe = TRANSITION_REGWEN.REGWEN; external reg { desc = "Control register for state transition requests."; @@ -161,8 +159,6 @@ addrmap lc_ctrl #( sw = rw; } VOLATILE_RAW_UNLOCK[1:1]; } TRANSITION_CTRL @ 0x18; - TRANSITION_CTRL.EXT_CLOCK_EN -> swwe = TRANSITION_REGWEN.REGWEN; - TRANSITION_CTRL.VOLATILE_RAW_UNLOCK -> swwe = TRANSITION_REGWEN.REGWEN; external reg { desc = "128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP/DMI interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF."; @@ -173,7 +169,6 @@ addrmap lc_ctrl #( desc = "Transition token."; } TRANSITION_TOKEN[31:0]; } TRANSITION_TOKEN[4] @ 0x1C; - TRANSITION_TOKEN.TRANSITION_TOKEN -> swwe = TRANSITION_REGWEN.REGWEN; external reg { desc = "This register exposes the decoded life cycle state."; @@ -184,7 +179,6 @@ addrmap lc_ctrl #( sw = rw; } STATE[29:0]; } TRANSITION_TARGET @ 0x2C; - TRANSITION_TARGET.STATE -> swwe = TRANSITION_REGWEN.REGWEN; external reg { desc = "Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value."; @@ -195,7 +189,6 @@ addrmap lc_ctrl #( sw = rw; } OTP_VENDOR_TEST_CTRL[31:0]; } OTP_VENDOR_TEST_CTRL @ 0x30; - OTP_VENDOR_TEST_CTRL.OTP_VENDOR_TEST_CTRL -> swwe = TRANSITION_REGWEN.REGWEN; external reg { desc = "Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero."; @@ -280,6 +273,13 @@ addrmap lc_ctrl #( } MANUF_STATE[31:0]; } MANUF_STATE[8] @ 0x6C; + CLAIM_TRANSITION_IF.MUTEX -> swwe = CLAIM_TRANSITION_IF_REGWEN.REGWEN; + TRANSITION_CMD.START -> swwe = TRANSITION_REGWEN.REGWEN; + TRANSITION_CTRL.EXT_CLOCK_EN -> swwe = TRANSITION_REGWEN.REGWEN; + TRANSITION_CTRL.VOLATILE_RAW_UNLOCK -> swwe = TRANSITION_REGWEN.REGWEN; + TRANSITION_TOKEN.TRANSITION_TOKEN -> swwe = TRANSITION_REGWEN.REGWEN; + TRANSITION_TARGET.STATE -> swwe = TRANSITION_REGWEN.REGWEN; + OTP_VENDOR_TEST_CTRL.OTP_VENDOR_TEST_CTRL -> swwe = TRANSITION_REGWEN.REGWEN; } regs; addrmap { diff --git a/rdlexporter/tests/snapshots/uart.rdl b/rdlexporter/tests/snapshots/uart.rdl index 7a27280..7d8bc31 100644 --- a/rdlexporter/tests/snapshots/uart.rdl +++ b/rdlexporter/tests/snapshots/uart.rdl @@ -4,6 +4,11 @@ addrmap uart #( longint param1 = 1, longint param2 = 2 ){ + signal { + signalwidth = 0x1; + sigtype = SigType::Interrupt; + } TX_FIFO_EMPTY; + reg { desc = "Interrupt state register."; field { diff --git a/rdlexporter/tests/snapshots/user_defined.rdl b/rdlexporter/tests/snapshots/user_defined.rdl index 8aad102..3c349e4 100644 --- a/rdlexporter/tests/snapshots/user_defined.rdl +++ b/rdlexporter/tests/snapshots/user_defined.rdl @@ -8,3 +8,35 @@ enum MultiBitBool8 { True = 0x96; False = 0x69; }; + + +enum SigType { + None; + Interrupt; // Signal is an interrupt + Alert; // Signal is an alert + Output; // Signal is an output + Input; // Signal is an input + Inout; // Signal is input and/or output +}; + +property sigtype { + type = SigType; + component = signal; + default = SigType::None; +}; + +struct udp_struct { + string name; + boolean enable; +}; + +property udp_config { + type = udp_struct; + component = addrmap; +}; + +property is_interface { + type = boolean; + component = addrmap; + default = false; +}; diff --git a/rdlexporter/tests/test_exporter.py b/rdlexporter/tests/test_exporter.py index 3358303..42a73e9 100644 --- a/rdlexporter/tests/test_exporter.py +++ b/rdlexporter/tests/test_exporter.py @@ -6,6 +6,7 @@ from pathlib import Path +import systemrdl from systemrdl import RDLCompiler, RDLImporter, rdltypes from systemrdl.ast.references import InstRef from systemrdl.core.parameter import Parameter @@ -25,6 +26,7 @@ def _run_ip_test_from_file(tmp_path: Path, ip_block: str) -> None: rdlc = RDLCompiler() rdlc.compile_file(input_rdl) + rdlc.elaborate() # Include the user defined enums and properties. with output_file.open("w") as f: @@ -57,11 +59,13 @@ def test_importer(tmp_path: Path) -> None: output_file = tmp_path / "generic.rdl" rdlc = RDLCompiler() - + rdlc.compile_file(SNAPSHOTS_DIR / "user_defined.rdl") imp = RDLImporter(rdlc) imp.default_src_ref = FileSourceRef(tmp_path) + root_addrmap = imp.create_addrmap_definition("root") addrmap = imp.create_addrmap_definition("generic") + addrmap = imp.instantiate_addrmap(addrmap, "GENERIC", 0x00) field_wen = imp.create_field_definition("EN") field_wen = imp.instantiate_field(field_wen, "EN", 0, 1) @@ -79,6 +83,14 @@ def test_importer(tmp_path: Path) -> None: imp.assign_property(field_en, "swmod", value=True) imp.assign_property(field_en, "desc", "Enable the ip") + signal_t = imp._create_definition(systemrdl.component.Signal, "interrupt", None) # noqa: SLF001 + signal = imp._instantiate(signal_t, "FIFO_EMPTY", None) # noqa: SLF001 + imp.assign_property(signal, "desc", "Fire when fifo is empty.") + imp.assign_property(signal, "signalwidth", 1) + enum = imp.compiler.namespace.lookup_type("SigType") + imp.assign_property(signal, "sigtype", enum["Interrupt"]) + addrmap.children.append(signal) + field_mode = imp.create_field_definition("MODE") field_mode = imp.instantiate_field(field_mode, "MODE", 2, 8) imp.assign_property(field_mode, "reset", 0x7) @@ -105,15 +117,29 @@ def test_importer(tmp_path: Path) -> None: reg = imp.instantiate_reg(reg, "CTRL", 0x04, [4], 0x04) imp.add_child(addrmap, reg) + imp.assign_property(addrmap, "is_interface", True) # noqa: FBT003 + type_ = imp.compiler.namespace.lookup_type("udp_struct") + inst = type_({"name": "racl", "enable": True}) + imp.assign_property(addrmap, "udp_config", inst) + + imp.add_child(root_addrmap, addrmap) value = 0x56 param = Parameter(rdltypes.get_rdltype(value), "Width") param._value = value # noqa: SLF001 - addrmap.parameters.append(param) + root_addrmap.parameters_dict["Width"] = param - imp.register_root_component(addrmap) + inst = type_({"name": "interface", "enable": True}) + imp.assign_property(root_addrmap, "udp_config", inst) + + imp.register_root_component(root_addrmap) RdlExporter(rdlc).export(output_file) + # Check that the generated file is valid rdl by compiling it. + rdlc = RDLCompiler() + rdlc.compile_file(SNAPSHOTS_DIR / "user_defined.rdl") + rdlc.compile_file(output_file) + actual_output_content = output_file.read_text(encoding="utf-8") assert actual_output_content == snapshot_content, ( f"Output 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