[dv] Correctly set minstret in cosim

SamuelRiedel · SamuelRiedel · commit e3f146879853 · 2026-05-12T17:39:02.000+02:00
diff --git a/dv/cosim/cosim.h b/dv/cosim/cosim.h
@@ -128,6 +128,17 @@ class Cosim {
   // A full 64-bit value is provided setting both the mcycle and mcycleh CSRs.
   virtual void set_mcycle(uint64_t mcycle) = 0;
 
+  // Set the value of minstret.
+  //
+  // The co-simulation model doesn't alter the value of minstret itself (other
+  // than instructions that do a direct CSR write). minstret should be set to
+  // the correct value before any `step` call that may execute an instruction
+  // that observes the value of minstret.
+  //
+  // A full 64-bit value is provided setting both the minstret and minstreth
+  // CSRs.
+  virtual void set_minstret(uint64_t minstret) = 0;
+
   // Set the value of a CSR. This is used when it is needed to have direct
   // communication between DUT and Spike (e.g. Performance counters).
   virtual void set_csr(const int csr_num, const uint32_t new_val) = 0;
diff --git a/dv/cosim/cosim_dpi.cc b/dv/cosim/cosim_dpi.cc
@@ -52,6 +52,13 @@ void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle) {
   cosim->set_mcycle(mcycle_full);
 }
 
+void riscv_cosim_set_minstret(Cosim *cosim, svBitVecVal *minstret) {
+  assert(cosim);
+
+  uint64_t minstret_full = minstret[0] | (uint64_t)minstret[1] << 32;
+  cosim->set_minstret(minstret_full);
+}
+
 void riscv_cosim_set_csr(Cosim *cosim, const int csr_id,
                          const svBitVecVal *csr_val) {
   assert(cosim);
diff --git a/dv/cosim/cosim_dpi.h b/dv/cosim/cosim_dpi.h
@@ -23,6 +23,7 @@ void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi);
 void riscv_cosim_set_nmi_int(Cosim *cosim, svBit nmi_int);
 void riscv_cosim_set_debug_req(Cosim *cosim, svBit debug_req);
 void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle);
+void riscv_cosim_set_minstret(Cosim *cosim, svBitVecVal *minstret);
 void riscv_cosim_set_csr(Cosim *cosim, const int csr_id,
                          const svBitVecVal *csr_val);
 void riscv_cosim_set_ic_scr_key_valid(Cosim *cosim, svBit valid);
diff --git a/dv/cosim/cosim_dpi.svh b/dv/cosim/cosim_dpi.svh
@@ -18,6 +18,7 @@ import "DPI-C" function void riscv_cosim_set_nmi(chandle cosim_handle, bit nmi);
 import "DPI-C" function void riscv_cosim_set_nmi_int(chandle cosim_handle, bit nmi_int);
 import "DPI-C" function void riscv_cosim_set_debug_req(chandle cosim_handle, bit debug_req);
 import "DPI-C" function void riscv_cosim_set_mcycle(chandle cosim_handle, bit [63:0] mcycle);
+import "DPI-C" function void riscv_cosim_set_minstret(chandle cosim_handle, bit [63:0] minstret);
 import "DPI-C" function void riscv_cosim_set_csr(chandle cosim_handle, int csr_id,
   bit [31:0] csr_val);
 import "DPI-C" function void riscv_cosim_set_ic_scr_key_valid(chandle cosim_handle, bit valid);
diff --git a/dv/cosim/spike_cosim.cc b/dv/cosim/spike_cosim.cc
@@ -750,6 +750,27 @@ void SpikeCosim::set_mcycle(uint64_t mcycle) {
   // to write all 64 bits at once at least.
 }
 
+void SpikeCosim::set_minstret(uint64_t minstret) {
+  uint32_t upper_minstret = minstret >> 32;
+  uint32_t lower_minstret = minstret & 0xffffffff;
+
+  // Spike decrements the MINSTRET CSR when you write to it. This is the same
+  // issue as with MCYCLE. See `set_mcycle` for more details.
+
+  // Write the lower half first, incremented twice due to the double decrement
+  processor->get_state()->csrmap[CSR_MINSTRET]->write(lower_minstret + 2);
+
+  if ((processor->get_state()->csrmap[CSR_MINSTRET]->read() & 0xffffffff) ==
+      0) {
+    // If the lower half is 0 at this point then the upper half will get
+    // decremented, so increment it first.
+    upper_minstret++;
+  }
+
+  // Set the upper half
+  processor->get_state()->csrmap[CSR_MINSTRETH]->write(upper_minstret);
+}
+
 void SpikeCosim::set_csr(const int csr_num, const uint32_t new_val) {
   // Note that this is tested with ibex-cosim-v0.3 version of Spike. 'set_csr'
   // method might have a hardwired zero for mhpmcounterX registers.
diff --git a/dv/cosim/spike_cosim.h b/dv/cosim/spike_cosim.h
@@ -132,6 +132,7 @@ class SpikeCosim : public simif_t, public Cosim {
   void set_nmi_int(bool nmi_int) override;
   void set_debug_req(bool debug_req) override;
   void set_mcycle(uint64_t mcycle) override;
+  void set_minstret(uint64_t minstret) override;
   void set_csr(const int csr_num, const uint32_t new_val) override;
   void set_ic_scr_key_valid(bool valid) override;
   void notify_dside_access(const DSideAccessInfo &access_info) override;
diff --git a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
@@ -151,6 +151,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
       riscv_cosim_set_nmi_int(cosim_handle, rvfi_instr.nmi_int);
       riscv_cosim_set_mip(cosim_handle, rvfi_instr.pre_mip, rvfi_instr.post_mip);
       riscv_cosim_set_mcycle(cosim_handle, rvfi_instr.mcycle);
+      riscv_cosim_set_minstret(cosim_handle, rvfi_instr.minstret);
 
       // Set performance counters through a pseudo-backdoor write
       for (int i=0; i < 10; i++) begin
diff --git a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv
@@ -44,6 +44,7 @@ class ibex_rvfi_monitor extends uvm_monitor;
       trans_collected.debug_req        = vif.monitor_cb.ext_debug_req;
       trans_collected.rf_wr_suppress   = vif.monitor_cb.ext_rf_wr_suppress;
       trans_collected.mcycle           = vif.monitor_cb.ext_mcycle;
+      trans_collected.minstret         = vif.monitor_cb.ext_minstret;
       trans_collected.ic_scr_key_valid = vif.monitor_cb.ext_ic_scr_key_valid;
 
       for (int i=0; i < 10; i++) begin
diff --git a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv
@@ -16,6 +16,7 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
   bit        debug_req;
   bit        rf_wr_suppress;
   bit [63:0] mcycle;
+  bit [63:0] minstret;
 
   bit [31:0] mhpmcounters  [10];
   bit [31:0] mhpmcountersh [10];
@@ -34,6 +35,7 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
     `uvm_field_int (debug_req, UVM_DEFAULT)
     `uvm_field_int (rf_wr_suppress, UVM_DEFAULT)
     `uvm_field_int (mcycle, UVM_DEFAULT)
+    `uvm_field_int (minstret, UVM_DEFAULT)
     `uvm_field_sarray_int (mhpmcounters, UVM_DEFAULT)
     `uvm_field_sarray_int (mhpmcountersh, UVM_DEFAULT)
     `uvm_field_int (ic_scr_key_valid, UVM_DEFAULT)
diff --git a/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv b/dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv
@@ -33,6 +33,7 @@ interface core_ibex_rvfi_if(input logic clk);
   logic [31:0] ext_debug_req;
   logic [31:0] ext_rf_wr_suppress;
   logic [63:0] ext_mcycle;
+  logic [63:0] ext_minstret;
   logic        ext_irq_valid;
 
   logic [31:0] ext_mhpmcounters [10];
@@ -70,6 +71,7 @@ interface core_ibex_rvfi_if(input logic clk);
     input ext_debug_req;
     input ext_rf_wr_suppress;
     input ext_mcycle;
+    input ext_minstret;
     input ext_mhpmcounters;
     input ext_mhpmcountersh;
     input ext_ic_scr_key_valid;
diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
@@ -249,6 +249,7 @@ module core_ibex_tb_top;
   assign rvfi_if.ext_debug_req        = dut.rvfi_ext_debug_req;
   assign rvfi_if.ext_rf_wr_suppress   = dut.rvfi_ext_rf_wr_suppress;
   assign rvfi_if.ext_mcycle           = dut.rvfi_ext_mcycle;
+  assign rvfi_if.ext_minstret         = dut.rvfi_ext_minstret;
   assign rvfi_if.ext_mhpmcounters     = dut.rvfi_ext_mhpmcounters;
   assign rvfi_if.ext_mhpmcountersh    = dut.rvfi_ext_mhpmcountersh;
   assign rvfi_if.ext_ic_scr_key_valid = dut.rvfi_ext_ic_scr_key_valid;
diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
@@ -156,6 +156,7 @@ module ibex_core import ibex_pkg::*; #(
   output logic                         rvfi_ext_debug_mode,
   output logic                         rvfi_ext_rf_wr_suppress,
   output logic [63:0]                  rvfi_ext_mcycle,
+  output logic [63:0]                  rvfi_ext_minstret,
   output logic [31:0]                  rvfi_ext_mhpmcounters [10],
   output logic [31:0]                  rvfi_ext_mhpmcountersh [10],
   output logic                         rvfi_ext_ic_scr_key_valid,
@@ -1316,6 +1317,7 @@ module ibex_core import ibex_pkg::*; #(
   logic            rvfi_ext_stage_debug_req           [RVFI_STAGES+1];
   logic            rvfi_ext_stage_debug_mode          [RVFI_STAGES];
   logic [63:0]     rvfi_ext_stage_mcycle              [RVFI_STAGES];
+  logic [63:0]     rvfi_ext_stage_minstret            [RVFI_STAGES];
   logic [31:0]     rvfi_ext_stage_mhpmcounters        [RVFI_STAGES][10];
   logic [31:0]     rvfi_ext_stage_mhpmcountersh       [RVFI_STAGES][10];
   logic            rvfi_ext_stage_ic_scr_key_valid    [RVFI_STAGES];
@@ -1384,6 +1386,7 @@ module ibex_core import ibex_pkg::*; #(
   assign rvfi_ext_debug_req           = rvfi_ext_stage_debug_req           [RVFI_STAGES];
   assign rvfi_ext_debug_mode          = rvfi_ext_stage_debug_mode          [RVFI_STAGES-1];
   assign rvfi_ext_mcycle              = rvfi_ext_stage_mcycle              [RVFI_STAGES-1];
+  assign rvfi_ext_minstret            = rvfi_ext_stage_minstret            [RVFI_STAGES-1];
   assign rvfi_ext_mhpmcounters        = rvfi_ext_stage_mhpmcounters        [RVFI_STAGES-1];
   assign rvfi_ext_mhpmcountersh       = rvfi_ext_stage_mhpmcountersh       [RVFI_STAGES-1];
   assign rvfi_ext_ic_scr_key_valid    = rvfi_ext_stage_ic_scr_key_valid    [RVFI_STAGES-1];
@@ -1607,6 +1610,7 @@ module ibex_core import ibex_pkg::*; #(
         rvfi_ext_stage_debug_req[i+1]         <= '0;
         rvfi_ext_stage_debug_mode[i]          <= '0;
         rvfi_ext_stage_mcycle[i]              <= '0;
+        rvfi_ext_stage_minstret[i]            <= '0;
         rvfi_ext_stage_ic_scr_key_valid[i]    <= '0;
         rvfi_ext_stage_expanded_insn_valid[i] <= '0;
         rvfi_ext_stage_expanded_insn[i]       <= '0;
@@ -1661,6 +1665,7 @@ module ibex_core import ibex_pkg::*; #(
             rvfi_stage_mem_addr[i]                <= rvfi_mem_addr_d;
             rvfi_ext_stage_debug_mode[i]          <= debug_mode;
             rvfi_ext_stage_mcycle[i]              <= cs_registers_i.mcycle_counter_i.counter_val_o;
+            rvfi_ext_stage_minstret[i]            <= cs_registers_i.mhpmcounter[2];
             rvfi_ext_stage_ic_scr_key_valid[i]    <= cs_registers_i.cpuctrlsts_ic_scr_key_valid_q;
             rvfi_ext_stage_expanded_insn_valid[i] <= rvfi_expanded_insn_valid;
             rvfi_ext_stage_expanded_insn[i]       <= rvfi_expanded_insn;
@@ -1731,6 +1736,7 @@ module ibex_core import ibex_pkg::*; #(
 
             rvfi_ext_stage_debug_mode[i]          <= rvfi_ext_stage_debug_mode[i-1];
             rvfi_ext_stage_mcycle[i]              <= rvfi_ext_stage_mcycle[i-1];
+            rvfi_ext_stage_minstret[i]            <= rvfi_ext_stage_minstret[i-1];
             rvfi_ext_stage_ic_scr_key_valid[i]    <= rvfi_ext_stage_ic_scr_key_valid[i-1];
             rvfi_ext_stage_mhpmcounters[i]        <= rvfi_ext_stage_mhpmcounters[i-1];
             rvfi_ext_stage_mhpmcountersh[i]       <= rvfi_ext_stage_mhpmcountersh[i-1];
diff --git a/rtl/ibex_lockstep.sv b/rtl/ibex_lockstep.sv
@@ -547,6 +547,7 @@ module ibex_lockstep import ibex_pkg::*; #(
     .rvfi_ext_debug_mode          (),
     .rvfi_ext_rf_wr_suppress      (),
     .rvfi_ext_mcycle              (),
+    .rvfi_ext_minstret            (),
     .rvfi_ext_mhpmcounters        (),
     .rvfi_ext_mhpmcountersh       (),
     .rvfi_ext_ic_scr_key_valid    (),
diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv
@@ -149,6 +149,7 @@ module ibex_top import ibex_pkg::*; #(
   output logic                                                        rvfi_ext_debug_mode,
   output logic                                                        rvfi_ext_rf_wr_suppress,
   output logic [63:0]                                                 rvfi_ext_mcycle,
+  output logic [63:0]                                                 rvfi_ext_minstret,
   output logic [31:0]                                                 rvfi_ext_mhpmcounters [10],
   output logic [31:0]                                                 rvfi_ext_mhpmcountersh [10],
   output logic                                                        rvfi_ext_ic_scr_key_valid,
@@ -446,6 +447,7 @@ module ibex_top import ibex_pkg::*; #(
     .rvfi_ext_debug_mode,
     .rvfi_ext_rf_wr_suppress,
     .rvfi_ext_mcycle,
+    .rvfi_ext_minstret,
     .rvfi_ext_mhpmcounters,
     .rvfi_ext_mhpmcountersh,
     .rvfi_ext_ic_scr_key_valid,
diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv
@@ -154,6 +154,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
   logic        rvfi_ext_debug_mode;
   logic        rvfi_ext_rf_wr_suppress;
   logic [63:0] rvfi_ext_mcycle;
+  logic [63:0] rvfi_ext_minstret;
 
   logic [31:0] rvfi_ext_mhpmcounters [10];
   logic [31:0] rvfi_ext_mhpmcountersh [10];
@@ -175,6 +176,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
   logic        unused_rvfi_ext_debug_mode;
   logic        unused_rvfi_ext_rf_wr_suppress;
   logic [63:0] unused_rvfi_ext_mcycle;
+  logic [63:0] unused_rvfi_ext_minstret;
   logic        unused_rvfi_ext_ic_scr_key_valid;
   logic        unused_rvfi_ext_irq_valid;
   logic        unused_rvfi_ext_expanded_insn_last;
@@ -189,6 +191,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
   assign unused_rvfi_ext_debug_mode = rvfi_ext_debug_mode;
   assign unused_rvfi_ext_rf_wr_suppress = rvfi_ext_rf_wr_suppress;
   assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
+  assign unused_rvfi_ext_minstret = rvfi_ext_minstret;
   assign unused_perf_regs = rvfi_ext_mhpmcounters;
   assign unused_perf_regsh = rvfi_ext_mhpmcountersh;
   assign unused_rvfi_ext_ic_scr_key_valid = rvfi_ext_ic_scr_key_valid;
@@ -305,6 +308,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .rvfi_ext_debug_mode,
     .rvfi_ext_rf_wr_suppress,
     .rvfi_ext_mcycle,
+    .rvfi_ext_minstret,
     .rvfi_ext_mhpmcounters,
     .rvfi_ext_mhpmcountersh,
     .rvfi_ext_ic_scr_key_valid,
