[cheriot,rtl] Integrate TRVK filter into Ibex Top

dv/formal/check/top.sv

@@ -142,7 +142,33 @@ localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;
 
 default clocking @(posedge clk_i); endclocking
 
+// The TRVK (CHERIoT revocation) filter is only instantiated when BaseIsa is
+// BaseIsaRV32IorCHERIoT. The core has no CHERIoT support yet and the formal spec
+// is the plain RISC-V Sail model, so select BaseIsaRV32I to bypass the filter
+// (a combinational pass-through of the data interface). The filter's ports still
+// exist on ibex_top, so provide nets for the `.*` connection below: drive the
+// inputs to their inactive values and leave the outputs as sinks.
+logic [31:0] trvk_heap_base_addr_i;
+logic        data_tag_o;
+logic        data_tag_i;
+logic        trvk_revbm_req_o;
+logic        trvk_revbm_gnt_i;
+logic        trvk_revbm_rvalid_i;
+logic [31:0] trvk_revbm_addr_o;
+logic [31:0] trvk_revbm_rdata_i;
+logic [ 6:0] trvk_revbm_rdata_intg_i;
+logic        trvk_revbm_err_i;
+
+assign trvk_heap_base_addr_i   = 32'b0;
+assign data_tag_i              = 1'b0;
+assign trvk_revbm_gnt_i        = 1'b0;
+assign trvk_revbm_rvalid_i     = 1'b0;
+assign trvk_revbm_rdata_i      = 32'b0;
+assign trvk_revbm_rdata_intg_i = 7'b0;
+assign trvk_revbm_err_i        = 1'b0;
+
 ibex_top #(
+    .BaseIsa(ibex_pkg::BaseIsaRV32I),
     .DmHaltAddr(DmHaltAddr),
     .DmExceptionAddr(DmExceptionAddr),
     .SecureIbex(SecureIbex),

dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

@@ -180,6 +180,8 @@ module ibex_riscv_compliance (
       // First instruction executed is at 0x0 + 0x80
       .boot_addr_i               (32'h00000000         ),
 
+      .trvk_heap_base_addr_i     (32'h00000000         ),
+
       .instr_req_o               (host_req[CoreI]      ),
       .instr_gnt_i               (host_gnt[CoreI]      ),
       .instr_rvalid_i            (host_rvalid[CoreI]   ),
@@ -196,10 +198,20 @@ module ibex_riscv_compliance (
       .data_addr_o               (host_addr[CoreD]     ),
       .data_wdata_o              (host_wdata[CoreD]    ),
       .data_wdata_intg_o         (                     ),
+      .data_tag_o                (                     ),
       .data_rdata_i              (host_rdata[CoreD]    ),
       .data_rdata_intg_i         (ibex_data_rdata_intg ),
+      .data_tag_i                (1'b0                 ),
       .data_err_i                (host_err[CoreD]      ),
 
+      .trvk_revbm_req_o          (                     ),
+      .trvk_revbm_gnt_i          (1'b0                 ),
+      .trvk_revbm_rvalid_i       (1'b0                 ),
+      .trvk_revbm_addr_o         (                     ),
+      .trvk_revbm_rdata_i        ('0                   ),
+      .trvk_revbm_rdata_intg_i   ('0                   ),
+      .trvk_revbm_err_i          (1'b0                 ),
+
       .irq_software_i            (1'b0                 ),
       .irq_timer_i               (1'b0                 ),
       .irq_external_i            (1'b0                 ),

dv/uvm/core_ibex/ibex_dv.f

@@ -50,10 +50,17 @@
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_39_32_dec.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_enc.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_72_64_dec.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_fifo_sync_cnt.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_fifo_sync.sv
+
+// Vendored PULP common cells (used by the TRVK filter).
+${PRJ_DIR}/vendor/pulp_common_cells/rtl/stream_fork.sv
+${PRJ_DIR}/vendor/pulp_common_cells/rtl/stream_join_dynamic.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/rtl
 ${PRJ_DIR}/rtl/ibex_pkg.sv
+${PRJ_DIR}/rtl/ibex_cheriot_pkg.sv
 ${PRJ_DIR}/rtl/ibex_tracer_pkg.sv
 ${PRJ_DIR}/rtl/ibex_tracer.sv
 ${PRJ_DIR}/rtl/ibex_alu.sv
@@ -81,6 +88,7 @@
 ${PRJ_DIR}/rtl/ibex_register_file_latch.sv
 ${PRJ_DIR}/rtl/ibex_pmp.sv
 ${PRJ_DIR}/rtl/ibex_core.sv
+${PRJ_DIR}/rtl/ibex_trvk.sv
 ${PRJ_DIR}/rtl/ibex_top.sv
 ${PRJ_DIR}/rtl/ibex_top_tracing.sv
 

dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

@@ -95,29 +95,30 @@ module core_ibex_tb_top;
   assign {scramble_key, scramble_nonce} = scrambling_key_if.d_data;
 
   ibex_top_tracing #(
-    .PMPEnable            (PMPEnable           ),
-    .PMPGranularity       (PMPGranularity      ),
-    .PMPNumRegions        (PMPNumRegions       ),
-    .MHPMCounterNum       (MHPMCounterNum      ),
-    .MHPMCounterWidth     (MHPMCounterWidth    ),
-    .RV32E                (RV32E               ),
-    .RV32M                (RV32M               ),
-    .RV32B                (RV32B               ),
-    .RegFile              (RegFile             ),
-    .BranchTargetALU      (BranchTargetALU     ),
-    .WritebackStage       (WritebackStage      ),
-    .ICache               (ICache              ),
-    .ICacheECC            (ICacheECC           ),
-    .ICacheTweakInfection (ICacheTweakInfection),
-    .SecureIbex           (SecureIbex          ),
-    .LockstepOffset       (LockstepOffset      ),
-    .ICacheScramble       (ICacheScramble      ),
-    .BranchPredictor      (BranchPredictor     ),
-    .DbgTriggerEn         (DbgTriggerEn        ),
-    .DmBaseAddr           (DmBaseAddr          ),
-    .DmAddrMask           (DmAddrMask          ),
-    .DmHaltAddr           (DmHaltAddr          ),
-    .DmExceptionAddr      (DmExceptionAddr     )
+    .BaseIsa              (ibex_pkg::BaseIsaRV32I),
+    .PMPEnable            (PMPEnable             ),
+    .PMPGranularity       (PMPGranularity        ),
+    .PMPNumRegions        (PMPNumRegions         ),
+    .MHPMCounterNum       (MHPMCounterNum        ),
+    .MHPMCounterWidth     (MHPMCounterWidth      ),
+    .RV32E                (RV32E                 ),
+    .RV32M                (RV32M                 ),
+    .RV32B                (RV32B                 ),
+    .RegFile              (RegFile               ),
+    .BranchTargetALU      (BranchTargetALU       ),
+    .WritebackStage       (WritebackStage        ),
+    .ICache               (ICache                ),
+    .ICacheECC            (ICacheECC             ),
+    .ICacheTweakInfection (ICacheTweakInfection  ),
+    .SecureIbex           (SecureIbex            ),
+    .LockstepOffset       (LockstepOffset        ),
+    .ICacheScramble       (ICacheScramble        ),
+    .BranchPredictor      (BranchPredictor       ),
+    .DbgTriggerEn         (DbgTriggerEn          ),
+    .DmBaseAddr           (DmBaseAddr            ),
+    .DmAddrMask           (DmAddrMask            ),
+    .DmHaltAddr           (DmHaltAddr            ),
+    .DmExceptionAddr      (DmExceptionAddr       )
 
   ) dut (
     .clk_i                     (clk                        ),
@@ -132,6 +133,7 @@ module core_ibex_tb_top;
 
     .hart_id_i                 (32'b0                      ),
     .boot_addr_i               (BootAddr                   ),
+    .trvk_heap_base_addr_i     (32'b0                      ),
 
     .instr_req_o               (instr_mem_vif.request      ),
     .instr_gnt_i               (instr_mem_vif.grant        ),
@@ -149,10 +151,20 @@ module core_ibex_tb_top;
     .data_be_o                 (data_mem_vif.be            ),
     .data_rdata_i              (data_mem_vif.rdata         ),
     .data_rdata_intg_i         (data_mem_vif.rintg         ),
+    .data_tag_i                (1'b0                       ),
     .data_wdata_o              (data_mem_vif.wdata         ),
     .data_wdata_intg_o         (data_mem_vif.wintg         ),
+    .data_tag_o                (                           ),
     .data_err_i                (data_mem_vif.error         ),
 
+    .trvk_revbm_req_o          (                           ),
+    .trvk_revbm_gnt_i          (1'b0                       ),
+    .trvk_revbm_rvalid_i       (1'b0                       ),
+    .trvk_revbm_addr_o         (                           ),
+    .trvk_revbm_rdata_i        ('b0                        ),
+    .trvk_revbm_rdata_intg_i   ('b0                        ),
+    .trvk_revbm_err_i          (                           ),
+
     .irq_software_i            (irq_vif.irq_software       ),
     .irq_timer_i               (irq_vif.irq_timer          ),
     .irq_external_i            (irq_vif.irq_external       ),

examples/simple_system/rtl/ibex_simple_system.sv

@@ -240,6 +240,8 @@ module ibex_simple_system (
       // First instruction executed is at 0x0 + 0x80
       .boot_addr_i               (32'h00100000),
 
+      .trvk_heap_base_addr_i     (32'h00000000),
+
       .instr_req_o               (instr_req),
       .instr_gnt_i               (instr_gnt),
       .instr_rvalid_i            (instr_rvalid),
@@ -256,10 +258,20 @@ module ibex_simple_system (
       .data_addr_o               (host_addr[CoreD]),
       .data_wdata_o              (host_wdata[CoreD]),
       .data_wdata_intg_o         (),
+      .data_tag_o                (),
       .data_rdata_i              (host_rdata[CoreD]),
       .data_rdata_intg_i         (data_rdata_intg),
+      .data_tag_i                (1'b0),
       .data_err_i                (host_err[CoreD]),
 
+      .trvk_revbm_req_o          (),
+      .trvk_revbm_gnt_i          (1'b0),
+      .trvk_revbm_rvalid_i       (1'b0),
+      .trvk_revbm_addr_o         (),
+      .trvk_revbm_rdata_i        ('0),
+      .trvk_revbm_rdata_intg_i   ('0),
+      .trvk_revbm_err_i          (1'b0),
+
       .irq_software_i            (1'b0),
       .irq_timer_i               (timer_irq),
       .irq_external_i            (1'b0),

ibex_core.core

@@ -12,6 +12,7 @@ filesets:
       - lowrisc:prim:clock_gating
       - lowrisc:prim:lfsr
       - lowrisc:prim:mubi
+      - lowrisc:prim:fifo
       - lowrisc:ibex:ibex_pkg
       - lowrisc:ibex:ibex_icache
       - lowrisc:dv:dv_fcov_macros

ibex_pkg.core

@@ -9,6 +9,7 @@ filesets:
   files_rtl:
     files:
       - rtl/ibex_pkg.sv
+      - rtl/ibex_cheriot_pkg.sv
     file_type: systemVerilogSource
 
 targets:

ibex_top.core

@@ -19,10 +19,12 @@ filesets:
       - lowrisc:prim:onehot_check
       - lowrisc:prim:onehot
       - lowrisc:prim:util
+      - pulp-platform:common_cells:common_cells
     files:
       - rtl/ibex_register_file_ff.sv # generic FF-based
       - rtl/ibex_register_file_fpga.sv # FPGA
       - rtl/ibex_register_file_latch.sv # ASIC
+      - rtl/ibex_trvk.sv
       - rtl/ibex_lockstep.sv
       - rtl/ibex_top.sv
     file_type: systemVerilogSource

rtl/ibex_cheriot_pkg.sv

@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package ibex_cheriot_pkg;
+
+  parameter int unsigned TOP_W     = 9;
+  parameter int unsigned BOT_W     = 9;
+  parameter int unsigned EXP_W     = 5;
+  parameter int unsigned OTYPE_W   = 3;
+  parameter int unsigned CPERMS_W  = 6;
+
+
+  // Obtain 32-bit representation of top
+  function automatic logic[32:0] get_bound33(logic [TOP_W-1:0] top, logic [1:0]  cor,
+                                             logic [EXP_W-1:0] exponent, logic [31:0] addr);
+    logic [32:0] t1, t2, mask, cor_val;
+
+    if (cor[1])
+      // negative sign extension
+      cor_val = {33{cor[1]}};
+    else
+      cor_val = {32'h0, (~cor[1]) & cor[0]};
+
+    cor_val = (cor_val << exponent) << TOP_W;
+    mask    = (33'h1_ffff_ffff << exponent) << TOP_W;
+
+    // apply correction and truncate
+    t1 = ({1'b0, addr} & mask) + cor_val;
+    // extend to 32 bit
+    t2 = {24'h0, top};
+    t1 = t1 | (t2 << exponent);
+
+    return t1;
+  endfunction
+
+
+  // Update the top/base correction for a cap
+  function automatic logic [2:0] update_temp_fields(logic [TOP_W-1:0] top, logic [BOT_W-1:0] base,
+                                                    logic [BOT_W-1:0] addrmi);
+    logic top_hi, addr_hi;
+    logic [2:0] res3;
+
+    top_hi   = (top < base);
+    addr_hi  = (addrmi < base);
+
+    // top_cor
+    res3[2:1] = (top_hi == addr_hi)? 2'b00 : ((top_hi && (!addr_hi))? 2'b01 : 2'b11);
+
+    // base_cor
+    res3[0] = (addr_hi) ? 1'b1 : 1'b0;
+
+    return res3;
+  endfunction
+
+endpackage

rtl/ibex_pkg.sv

@@ -32,6 +32,11 @@ package ibex_pkg;
   // Parameter Enums //
   /////////////////////
 
+  typedef enum integer {
+    BaseIsaRV32I          = 0, // only RV32I
+    BaseIsaRV32IorCHERIoT = 1  // dual base ISA: RV32I/CHERIoT runtime switchable
+  } base_isa_e;
+
   typedef enum integer {
     RegFileFF    = 0,
     RegFileFPGA  = 1,