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KolosKoblasz-SemifyKolosKoblasz-Semify
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[clkmgr, vendoring] Modified template files commited
 * Path and tool fixes applied to template files * transactional and hint clock related code pieces removed from the templates. * vseq list modified * hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv.tpl deleted Signed-off-by: Kolos Koblasz <kolos.koblasz@semify-eda.com>
1 parent 024a170 commit 53ea63c

8 files changed

Lines changed: 83 additions & 189 deletions

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‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/data/clkmgr_testplan.hjson.tpl‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,14 +3,14 @@
33
// SPDX-License-Identifier: Apache-2.0
44
{
55
name: "clkmgr"
6-
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
7-
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
8-
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
9-
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
10-
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
11-
"hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
6+
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
7+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
8+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
9+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
10+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
11+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
1212
"clkmgr_sec_cm_testplan.hjson",
13-
"hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"]
13+
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"]
1414
testpoints: [
1515
{
1616
name: smoke

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/clkmgr_sim_cfg.hjson.tpl‎

Lines changed: 8 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
tb: tb
1313
1414
// Simulator used to sign off this block
15-
tool: vcs
15+
tool: xcelium
1616
1717
// Fusesoc core file used for building the file list.
1818
fusesoc_core: ${instance_vlnv("lowrisc:dv:clkmgr_sim:0.1")}
@@ -25,14 +25,14 @@
2525

2626
// Import additional common sim cfg files.
2727
import_cfgs: [// Project wide common sim cfg file
28-
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
28+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
2929
// Common CIP test lists
30-
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
31-
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
32-
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
33-
"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
34-
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
35-
"{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson"
30+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
31+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
32+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
33+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson",
34+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
35+
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson"
3636
]
3737

3838
// Add additional tops for simulation.
@@ -88,19 +88,10 @@
8888
name: clkmgr_peri
8989
uvm_test_seq: clkmgr_peri_vseq
9090
}
91-
{
92-
name: clkmgr_trans
93-
uvm_test_seq: clkmgr_trans_vseq
94-
}
9591
{
9692
name: clkmgr_clk_status
9793
uvm_test_seq: clkmgr_clk_status_vseq
9894
}
99-
{
100-
name: clkmgr_idle_intersig_mubi
101-
uvm_test_seq: clkmgr_trans_vseq
102-
run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiIdle"]
103-
}
10495
% if ext_clk_bypass:
10596
{
10697
name: clkmgr_lc_ctrl_intersig_mubi

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/env/clkmgr_if.sv.tpl‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -83,22 +83,7 @@ interface clkmgr_if (
8383
};
8484

8585
clk_hints_t clk_hints_csr;
86-
always_comb
87-
clk_hints_csr = '{
88-
% for target in list(reversed(hint_targets)):
89-
<% sep = '' if loop.last else ',' %>\
90-
${target}: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_${target}_hint.q${sep}
91-
% endfor
92-
};
9386

94-
clk_hints_t clk_hints_status_csr;
95-
always_comb
96-
clk_hints_status_csr = '{
97-
% for target in list(reversed(hint_targets)):
98-
<% sep = '' if loop.last else ',' %>\
99-
${target}: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_${target}_val_qs${sep}
100-
% endfor
101-
};
10287
% if ext_clk_bypass:
10388

10489
prim_mubi_pkg::mubi4_t extclk_ctrl_csr_sel;

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv.tpl‎

Lines changed: 0 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq;
1919
cfg.clk_rst_vif.wait_clks(10);
2020
test_jitter();
2121
test_peri_clocks();
22-
test_trans_clocks();
2322
endtask : body
2423

2524
// Simply flip the jitter enable CSR. The side-effects are checked in the scoreboard.
@@ -53,58 +52,4 @@ class clkmgr_smoke_vseq extends clkmgr_base_vseq;
5352
csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset()));
5453
endtask : test_peri_clocks
5554

56-
// Starts with all units busy, and for each one this clears the hint and reads the hint status,
57-
// expecting it to remain at 1 since the unit is busy; then it sets the corresponding idle bit
58-
// and reads status again, expecting it to be low.
59-
//
60-
// We disable the value checks when reset is active since the reads return unpredictable data.
61-
task test_trans_clocks();
62-
trans_e trans;
63-
logic bit_value;
64-
logic [TL_DW-1:0] value;
65-
mubi_hintables_t idle;
66-
hintables_t bool_idle;
67-
typedef struct {
68-
trans_e unit;
69-
uvm_reg_field hint_bit;
70-
uvm_reg_field value_bit;
71-
} trans_descriptor_t;
72-
trans_descriptor_t trans_descriptors[NUM_TRANS] = '{
73-
'{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val},
74-
'{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val},
75-
'{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val},
76-
'{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val}
77-
};
78-
idle = 0;
79-
// Changes in idle take at least 10 cycles to stick.
80-
cfg.clkmgr_vif.update_idle(idle);
81-
cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
82-
83-
trans = trans.first;
84-
csr_rd(.ptr(ral.clk_hints), .value(value));
85-
`uvm_info(`gfn, $sformatf("Starting hints at 0x%0x, idle at 0x%x", value, idle), UVM_MEDIUM)
86-
do begin
87-
trans_descriptor_t descriptor = trans_descriptors[int'(trans)];
88-
`uvm_info(`gfn, $sformatf("Clearing %s hint bit", descriptor.unit.name), UVM_MEDIUM)
89-
csr_wr(.ptr(descriptor.hint_bit), .value(1'b0));
90-
csr_rd(.ptr(descriptor.value_bit), .value(bit_value));
91-
if (!cfg.under_reset) begin
92-
`DV_CHECK_EQ(bit_value, 1'b1, $sformatf(
93-
"%s hint value cannot drop while busy", descriptor.unit.name()))
94-
end
95-
`uvm_info(`gfn, $sformatf("Setting %s idle bit", descriptor.unit.name), UVM_MEDIUM)
96-
cfg.clk_rst_vif.wait_clks(1);
97-
idle[trans] = prim_mubi_pkg::MuBi4True;
98-
cfg.clkmgr_vif.update_idle(idle);
99-
// Some cycles for the logic to settle.
100-
cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
101-
csr_rd(.ptr(descriptor.value_bit), .value(bit_value));
102-
if (!cfg.under_reset) begin
103-
`DV_CHECK_EQ(bit_value, 1'b0, $sformatf(
104-
"%s hint value should drop when idle", descriptor.unit.name()))
105-
end
106-
trans = trans.next();
107-
end while (trans != trans.first);
108-
csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset()));
109-
endtask : test_trans_clocks
11055
endclass : clkmgr_smoke_vseq

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv.tpl‎

Lines changed: 66 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -29,70 +29,70 @@ class clkmgr_trans_vseq extends clkmgr_base_vseq;
2929
% endif
3030
% endfor
3131

32-
task body();
33-
for (int i = 0; i < num_trans; ++i) begin
34-
logic bit_value;
35-
hintables_t value;
36-
hintables_t bool_idle;
37-
38-
`DV_CHECK_RANDOMIZE_FATAL(this)
39-
40-
csr_rd(.ptr(ral.clk_hints_status), .value(value));
41-
42-
`uvm_info(`gfn, $sformatf("Initial clk_hints_status: %b", value), UVM_MEDIUM)
43-
cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode));
44-
45-
// add random value if mubi idle test
46-
if (mubi_mode == ClkmgrMubiIdle) drive_idle(idle);
47-
print_mubi_hintable(idle);
48-
control_ip_clocks();
49-
`uvm_info(`gfn, $sformatf("Idle = 0x%x", cfg.clkmgr_vif.idle_i), UVM_MEDIUM)
50-
cfg.clk_rst_vif.wait_clks(10);
51-
`uvm_info(`gfn, $sformatf("Updating hints to 0x%0x", initial_hints), UVM_MEDIUM)
52-
csr_wr(.ptr(ral.clk_hints), .value(initial_hints));
53-
54-
// Extra wait because of synchronizers plus counters.
55-
cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
56-
// We expect the status to be determined by hints and idle, ignoring scanmode.
57-
bool_idle = mubi_hintables_to_hintables(idle);
58-
value = initial_hints | ~bool_idle;
59-
csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value),
60-
.err_msg($sformatf(
61-
"Busy units have status high: hints=0x%x, idle=0x%x",
62-
initial_hints,
63-
bool_idle
64-
)));
65-
66-
// Setting all idle should make hint_status match hints.
67-
`uvm_info(`gfn, "Setting all units idle", UVM_MEDIUM)
68-
cfg.clkmgr_vif.update_idle({NUM_TRANS{MuBi4True}});
69-
cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
70-
71-
csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(initial_hints),
72-
.err_msg("All idle: expect status matches hints"));
73-
74-
// Now set all hints, and the status should also be all ones.
75-
value = '1;
76-
csr_wr(.ptr(ral.clk_hints), .value(value));
77-
cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
78-
// We expect all units to be on.
79-
csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value),
80-
.err_msg("All idle and all hints high: units status should be high"));
81-
82-
// Set hints to the reset value for stress tests.
83-
csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset()));
84-
end
85-
endtask : body
86-
87-
task drive_idle(ref mubi_hintables_t tbl);
88-
int period;
89-
mubi_hintables_t rand_idle;
90-
foreach (rand_idle[i])
91-
rand_idle[i] = get_rand_mubi4_val(.t_weight(0), .f_weight(0), .other_weight(1));
92-
93-
@cfg.clkmgr_vif.trans_cb;
94-
cfg.clkmgr_vif.idle_i = rand_idle;
95-
96-
tbl = rand_idle;
97-
endtask : drive_idle
32+
// task body();
33+
// for (int i = 0; i < num_trans; ++i) begin
34+
// logic bit_value;
35+
// hintables_t value;
36+
// hintables_t bool_idle;
37+
//
38+
// `DV_CHECK_RANDOMIZE_FATAL(this)
39+
//
40+
// csr_rd(.ptr(ral.clk_hints_status), .value(value));
41+
//
42+
// `uvm_info(`gfn, $sformatf("Initial clk_hints_status: %b", value), UVM_MEDIUM)
43+
// cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode));
44+
//
45+
// // add random value if mubi idle test
46+
// if (mubi_mode == ClkmgrMubiIdle) drive_idle(idle);
47+
// print_mubi_hintable(idle);
48+
// control_ip_clocks();
49+
// `uvm_info(`gfn, $sformatf("Idle = 0x%x", cfg.clkmgr_vif.idle_i), UVM_MEDIUM)
50+
// cfg.clk_rst_vif.wait_clks(10);
51+
// `uvm_info(`gfn, $sformatf("Updating hints to 0x%0x", initial_hints), UVM_MEDIUM)
52+
// csr_wr(.ptr(ral.clk_hints), .value(initial_hints));
53+
//
54+
// // Extra wait because of synchronizers plus counters.
55+
// cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
56+
// // We expect the status to be determined by hints and idle, ignoring scanmode.
57+
// bool_idle = mubi_hintables_to_hintables(idle);
58+
// value = initial_hints | ~bool_idle;
59+
// csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value),
60+
// .err_msg($sformatf(
61+
// "Busy units have status high: hints=0x%x, idle=0x%x",
62+
// initial_hints,
63+
// bool_idle
64+
// )));
65+
//
66+
// // Setting all idle should make hint_status match hints.
67+
// `uvm_info(`gfn, "Setting all units idle", UVM_MEDIUM)
68+
// cfg.clkmgr_vif.update_idle({NUM_TRANS{MuBi4True}});
69+
// cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
70+
//
71+
// csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(initial_hints),
72+
// .err_msg("All idle: expect status matches hints"));
73+
//
74+
// // Now set all hints, and the status should also be all ones.
75+
// value = '1;
76+
// csr_wr(.ptr(ral.clk_hints), .value(value));
77+
// cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES);
78+
// // We expect all units to be on.
79+
// csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value),
80+
// .err_msg("All idle and all hints high: units status should be high"));
81+
//
82+
// // Set hints to the reset value for stress tests.
83+
// csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset()));
84+
// end
85+
// endtask : body
86+
//
87+
// task drive_idle(ref mubi_hintables_t tbl);
88+
// int period;
89+
// mubi_hintables_t rand_idle;
90+
// foreach (rand_idle[i])
91+
// rand_idle[i] = get_rand_mubi4_val(.t_weight(0), .f_weight(0), .other_weight(1));
92+
//
93+
// @cfg.clkmgr_vif.trans_cb;
94+
// cfg.clkmgr_vif.idle_i = rand_idle;
95+
//
96+
// tbl = rand_idle;
97+
// endtask : drive_idle
9898
endclass : clkmgr_trans_vseq

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv.tpl‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,4 +14,3 @@
1414
`include "clkmgr_regwen_vseq.sv"
1515
`include "clkmgr_smoke_vseq.sv"
1616
`include "clkmgr_stress_all_vseq.sv"
17-
`include "clkmgr_trans_vseq.sv"

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/sva/clkmgr_bind.sv.tpl‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -43,19 +43,7 @@ module clkmgr_bind;
4343
);
4444

4545
% endfor
46-
// Assertions for transactional clocks.
47-
% for clk, sig in typed_clocks['hint_clks'].items():
48-
bind clkmgr clkmgr_trans_sva_if clkmgr_${sig['endpoint_ip']}_trans_sva_if (
49-
.clk(clk_${sig['src_name']}_i),
50-
.rst_n(rst_${sig['src_name']}_ni),
51-
.hint(reg2hw.clk_hints.${clk}_hint.q),
52-
.idle(idle_i[${hint_names[clk]}] == prim_mubi_pkg::MuBi4True),
53-
.scanmode(scanmode_i == prim_mubi_pkg::MuBi4True),
54-
.status(hw2reg.clk_hints_status.${clk}_val.d),
55-
.trans_clk(clocks_o.${clk})
56-
);
5746

58-
% endfor
5947
% if ext_clk_bypass:
6048
bind clkmgr clkmgr_extclk_sva_if clkmgr_extclk_sva_if (
6149
.clk_i,

‎hw/vendor/lowrisc_ip/ip_templates/clkmgr/dv/tb.sv.tpl‎

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -79,23 +79,9 @@ module tb;
7979
u_reg.u_fatal_err_code_shadow_storage_err.qs,
8080
u_reg.u_fatal_err_code_idle_cnt.qs,
8181
u_reg.u_fatal_err_code_reg_intg.qs
82-
}),
83-
.clk_enables({
84-
% for clk in [c for c in reversed(typed_clocks['sw_clks'].values())]:
85-
<% sep = "})," if loop.last else "," %>\
86-
% if len(typed_clocks['sw_clks']) == 1:
87-
reg2hw.clk_enables.q${sep}
88-
% else:
89-
reg2hw.clk_enables.clk_${clk['src_name']}_peri_en.q${sep}
90-
% endif
91-
% endfor
92-
.clk_hints({
93-
reg2hw.clk_hints.clk_main_otbn_hint.q,
94-
reg2hw.clk_hints.clk_main_kmac_hint.q,
95-
reg2hw.clk_hints.clk_main_hmac_hint.q,
96-
reg2hw.clk_hints.clk_main_aes_hint.q})
82+
})
9783
);
98-
84+
9985
rst_shadowed_if rst_shadowed_if (
10086
.rst_n(rst_n),
10187
.rst_shadowed_n(rst_shadowed_n)

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