[fpga] Expose HW_ID register

- Extend RestOfChipBase/Length in top_pkg to encompass the SW-DV window
(0x2002_0000), routing it through the rest_of_chip port without touching
top_chip_system.
- Add a second device to the rest-of-chip crossbar in
chip_mocha_genesys2 backed by axi_to_mem; reads to offset +0x08 return
the Genesys2 platform identifier (0x0000_000A), enabling SW tests to
detect the platform at runtime consistently with the sim infrastructure.

Signed-off-by: martin-velay <mvelay@lowrisc.org>

Author: martin-velay

hw/top_chip/rtl/chip_mocha_genesys2.sv

@@ -76,6 +76,7 @@ module chip_mocha_genesys2 #(
 );
   // Local parameters
   localparam int unsigned InitialResetCycles = 4;
+  localparam bit [31:0]   FpgaHwId           = 32'h0000_000A;   // FpgaGenesys2
 
   // Rest of chip AXI crossbar configuration
   localparam axi_pkg::xbar_cfg_t xbar_cfg = '{
@@ -97,7 +98,8 @@ module chip_mocha_genesys2 #(
   // Rest of chip AXI crossbar address mapping
   axi_pkg::xbar_rule_64_t [xbar_cfg.NoAddrRules-1:0] addr_map;
   assign addr_map = '{
-    '{ idx: top_pkg::Ethernet, start_addr: top_pkg::EthernetBase, end_addr: top_pkg::EthernetBase + top_pkg::EthernetLength }
+    '{ idx: top_pkg::SwDvWindowDevIdx, start_addr: top_pkg::SwDvWindowBase, end_addr: top_pkg::SwDvWindowBase + top_pkg::SwDvWindowLength },
+    '{ idx: top_pkg::Ethernet,         start_addr: top_pkg::EthernetBase,   end_addr: top_pkg::EthernetBase   + top_pkg::EthernetLength   }
   };
 
   // Internal clock signals
@@ -155,6 +157,14 @@ module chip_mocha_genesys2 #(
   // Ethernet interrupt line
   logic ethernet_irq;
 
+  // SW-DV window AXI subordinate memory interface acting as a sink
+  logic                             hw_id_mem_req;
+  logic                             hw_id_mem_req_d;
+  logic                             hw_id_mem_we;
+  logic [top_pkg::AxiAddrWidth-1:0] hw_id_mem_addr;
+  logic [top_pkg::AxiDataWidth-1:0] hw_id_mem_rdata;
+  logic                             hw_id_sel_d;
+
   // Clock generation
   clkgen_xil7series u_clk_gen (
     .clk_200m_i      (clk_200m),
@@ -562,4 +572,44 @@ module chip_mocha_genesys2 #(
     .eth_rgmii_mdc_o    (eth_mdc)
   );
 
+  // SW-DV window: read-only HW_ID register.
+  // Uses the same axi_to_mem + 1-cycle loopback pattern as sim_sram_axi_sink.
+  // Writes are accepted and discarded. Reads return FpgaHwId at offset +0x08, 0 elsewhere.
+  axi_to_mem #(
+    .axi_req_t    (top_pkg::axi_req_t   ),
+    .axi_resp_t   (top_pkg::axi_resp_t  ),
+    .DataWidth    (top_pkg::AxiDataWidth),
+    .AddrWidth    (top_pkg::AxiAddrWidth),
+    .IdWidth      (top_pkg::AxiIdWidth  ),
+    .NumBanks     (1                    )
+  ) u_hw_id_axi_to_mem (
+    .clk_i        (u_top_chip_system.clkmgr_clocks.clk_main_infra                       ),
+    .rst_ni       (u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]),
+    .busy_o       (                                                                     ),
+    .axi_req_i    (xbar_device_req [top_pkg::SwDvWindowDevIdx]                          ),
+    .axi_resp_o   (xbar_device_resp[top_pkg::SwDvWindowDevIdx]                          ),
+    .mem_req_o    (hw_id_mem_req                                                        ),
+    .mem_gnt_i    (1'b1                                                                 ),
+    .mem_addr_o   (hw_id_mem_addr                                                       ),
+    .mem_wdata_o  (                                                                     ),  // Ignored: RO register
+    .mem_strb_o   (                                                                     ),  // Ignored: RO register
+    .mem_atop_o   (                                                                     ),  // Not used
+    .mem_we_o     (hw_id_mem_we                                                         ),
+    .mem_rvalid_i (hw_id_mem_req_d                                                      ),
+    .mem_rdata_i  (hw_id_mem_rdata                                                      )
+  );
+
+  always_ff @(posedge u_top_chip_system.clkmgr_clocks.clk_main_infra
+              or negedge u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]) begin
+    if (!u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]) begin
+      hw_id_mem_req_d <= 1'b0;
+      hw_id_sel_d     <= 1'b0;
+    end else begin
+      hw_id_mem_req_d <= hw_id_mem_req;
+      hw_id_sel_d     <= hw_id_mem_req && !hw_id_mem_we && (hw_id_mem_addr[7:0] == 8'h08);
+    end
+  end
+
+  assign hw_id_mem_rdata = hw_id_sel_d ? {{(top_pkg::AxiDataWidth-32){1'b0}}, FpgaHwId} : '0;
+
 endmodule

hw/top_chip/rtl/top_pkg.sv

@@ -40,7 +40,7 @@ package top_pkg;
     SRAMBase       = 64'h1000_0000,
     DebugMemBase   = 64'h2000_0000,
     MailboxBase    = 64'h2001_0000,
-    RestOfChipBase = 64'h3000_0000,
+    RestOfChipBase = 64'h2002_0000,
     TlCrossbarBase = 64'h4000_0000,
     DRAMBase       = 64'h8000_0000
   } axi_addr_start_t;
@@ -50,7 +50,7 @@ package top_pkg;
   localparam longint unsigned SRAMLength         = 64'h0002_0000;
   localparam longint unsigned DebugMemLength     = 64'h0000_1000;
   localparam longint unsigned MailboxLength      = 64'h0001_0000;
-  localparam longint unsigned RestOfChipLength   = 64'h0000_8000;
+  localparam longint unsigned RestOfChipLength   = 64'h0FFE_8000;   // 0x2002_0000 to 0x3000_7FFF
   localparam longint unsigned TlCrossbarLength   = 64'h1000_0000;
   localparam longint unsigned DRAMPhysicalLength = 64'h4000_0000;
 
@@ -64,23 +64,26 @@ package top_pkg;
 
   // Rest of chip AXI crossbar parameters
   localparam int RestOfChipAxiXbarHosts   = 1;
-  localparam int RestOfChipAxiXbarDevices = 1;
+  localparam int RestOfChipAxiXbarDevices = 2;
 
   // Rest of chip AXI crossbar hosts and devices
   typedef enum int unsigned {
     MochaAXICrossbar = 0
   } rest_of_chip_axi_hosts_t;
 
   typedef enum int unsigned {
-    Ethernet = 0
+    Ethernet         = 0,
+    SwDvWindowDevIdx = 1
   } rest_of_chip_axi_devices_t;
 
   typedef enum longint unsigned {
-    EthernetBase = 64'h3000_0000
+    EthernetBase   = 64'h3000_0000,
+    SwDvWindowBase = 64'h2002_0000
   } rest_of_chip_axi_addr_start_t;
 
   // Memory lengths
-  localparam longint unsigned EthernetLength = 64'h0000_8000;
+  localparam longint unsigned EthernetLength   = 64'h0000_8000;
+  localparam longint unsigned SwDvWindowLength = 64'h0000_0100;
 
   // Memory address masks
   localparam longint unsigned EthernetMask = EthernetLength - 1;