[dv] Add support for HW_ID for SW

- Related to issue #423
- This commit adds support for a HW_ID register that can be used by
  SW DV tests to identify the hardware they are running on. This is
  useful for SW DV tests that need to run on multiple hardware platforms
  and need a way to differentiate between them.
- Add framework C test

Signed-off-by: martin-velay <mvelay@lowrisc.org>

Author: martin-velay

hw/top_chip/dv/env/top_chip_dv_env_pkg.sv

@@ -41,11 +41,15 @@ package top_chip_dv_env_pkg;
   // 50 MHz Peripheral clock
   parameter int unsigned PeriClkFreq = 50_000_000;
 
-  // SW DV special write locations for test status and logging will always fit in 32-bits
+  // SW-DV special locations for test status, logging, and platform identification.
+  // These are intercepted by sim_sram_axi_sink before the AXI crossbar.
   parameter bit [31:0] SW_DV_START_ADDR       = 'h2002_0000;
   parameter bit [31:0] SW_DV_SIZE             = 'h0000_0100;        // 256 bytes reserved for SW DV
   parameter bit [31:0] SW_DV_TEST_STATUS_ADDR = SW_DV_START_ADDR + 'h00;
-  parameter bit [31:0] SW_DV_LOG_ADDR         = SW_DV_START_ADDR + 'h04;
+  parameter bit [31:0] SW_DV_HW_ID_ADDR       = SW_DV_START_ADDR + 'h04;
+  parameter bit [31:0] SW_DV_LOG_ADDR         = SW_DV_START_ADDR + 'h08;
+
+  parameter bit [31:0] SW_DV_HW_ID            = 32'h0000_002A;
 
   // File includes
   `include "mem_clear_util.sv"

hw/top_chip/dv/sim_sram_axi/sim_sram_axi_if.sv

@@ -15,6 +15,8 @@ interface sim_sram_axi_if (
   // Control signals set by the Testbench
   logic [31:0] start_addr;
   logic [31:0] sw_dv_size;
+  logic [31:0] hw_id_addr;
+  logic [31:0] hw_id;
 
   // Monitor signals driven by the Sink
   axi_req_t  req;

hw/top_chip/dv/sim_sram_axi/sim_sram_axi_sink.sv

@@ -68,6 +68,19 @@ module sim_sram_axi_sink #(
   logic [top_pkg::AxiDataWidth-1:0] mem_rdata;
   logic [top_pkg::AxiStrbWidth-1:0] mem_be;
 
+  // True when the access targets the read-only HW_ID register.
+  // axi_to_mem aligns addresses to AxiDataWidth/8 bytes, so compare against the
+  // 8-byte aligned hw_id_addr (clearing the lower 3 bits for a 64-bit bus).
+  logic hw_id_sel;
+  assign hw_id_sel = (mem_addr[31:0] == {u_sim_sram_if.hw_id_addr[31:3], 3'b000});
+
+  // Insert one cycle delay to align with mem_req_d
+  logic hw_id_sel_d;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) hw_id_sel_d <= 1'b0;
+    else         hw_id_sel_d <= mem_req && !mem_we && hw_id_sel;
+  end
+
   axi_to_mem #(
     .axi_req_t    (top_pkg::axi_req_t     ),
     .axi_resp_t   (top_pkg::axi_resp_t    ),
@@ -102,9 +115,9 @@ module sim_sram_axi_sink #(
     end
   end : delayed_mem_req
 
-  // Assert Error if ErrOnRead is set and a read occurs
+  // Assert Error if ErrOnRead is set and a read occurs to a non-HW_ID address.
   if (ErrOnRead) begin : gen_err_on_read
-    `ASSERT(ErrOnRead_A, mem_req |-> mem_we, clk_i, !rst_ni)
+    `ASSERT(ErrOnRead_A, (mem_req && !hw_id_sel) |-> mem_we, clk_i, !rst_ni)
   end : gen_err_on_read
 
   // Conditional SRAM Instantiation
@@ -138,9 +151,9 @@ module sim_sram_axi_sink #(
     );
   end : gen_sram
   else begin : gen_no_sram
-    // If no SRAM, return 0s on read.
-    // Handshaking is handled by the common logic and axi_to_mem.
-    assign mem_rdata = '0;
+    // If no SRAM, return hw_id for RO register reads, 0 otherwise.
+    // hw_id at byte offset 4 occupies the upper 32 bits of the 64-bit AXI word [63:32].
+    assign mem_rdata = hw_id_sel_d ? {u_sim_sram_if.hw_id, {(AxiDataWidth-32){1'b0}}} : '0;
   end : gen_no_sram
 
   // Simulation SRAM Interface Instance

hw/top_chip/dv/tb/tb.sv

@@ -15,6 +15,8 @@ module tb;
   import top_chip_dv_env_pkg::SW_DV_START_ADDR;
   import top_chip_dv_env_pkg::SW_DV_TEST_STATUS_ADDR;
   import top_chip_dv_env_pkg::SW_DV_LOG_ADDR;
+  import top_chip_dv_env_pkg::SW_DV_HW_ID_ADDR;
+  import top_chip_dv_env_pkg::SW_DV_HW_ID;
 
   // Macro includes
   `include "uvm_macros.svh"
@@ -271,6 +273,8 @@ module tb;
     // Set base of SW DV special write locations
     `SIM_SRAM_IF.start_addr                              = SW_DV_START_ADDR;
     `SIM_SRAM_IF.sw_dv_size                              = SW_DV_SIZE;
+    `SIM_SRAM_IF.hw_id                                   = SW_DV_HW_ID;
+    `SIM_SRAM_IF.hw_id_addr                              = SW_DV_HW_ID_ADDR;
     `SIM_SRAM_IF.u_sw_test_status_if.sw_test_status_addr = SW_DV_TEST_STATUS_ADDR;
     `SIM_SRAM_IF.u_sw_logger_if.sw_log_addr              = SW_DV_LOG_ADDR;
 

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -103,6 +103,20 @@
       run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_interrupt_test_cheri_sram.vmem",
                  "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"]
     }
+    {
+      name: test_framework_test
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["test_framework_test_vanilla_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_test_vanilla_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"]
+    }
+    {
+      name: test_framework_test_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["test_framework_test_cheri_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_test_cheri_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"]
+    }
     {
       name: test_framework_exception_test
       uvm_test_seq: top_chip_dv_base_vseq
@@ -346,6 +360,8 @@
         "rv_timer_smoke_cheri",
         "rv_timer_irq",
         "rv_timer_irq_cheri",
+        "test_framework_test",
+        "test_framework_test_cheri",
         "test_framework_exception_test",
         "test_framework_exception_test_cheri",
         "spi_device_smoke",
@@ -398,6 +414,8 @@
     {
       name: test_framework
       tests: [
+        "test_framework_test",
+        "test_framework_test_cheri",
         "test_framework_exception_test",
         "test_framework_exception_test_cheri"
       ]

hw/top_chip/dv/verilator/top_chip_verilator.sv

@@ -187,9 +187,15 @@ module top_chip_verilator (
   `define DUT               u_top_chip_system
   `define SIM_SRAM_IF       u_sim_sram.u_sim_sram_if
 
+  // Special addresses for SW-DV communication
   localparam bit [31:0] VERILATOR_SW_DV_START_ADDR       = 'h2002_0000;
   localparam bit [31:0] VERILATOR_SW_DV_SIZE             = 'h0000_0100;   // 256 bytes reserved
   localparam bit [31:0] VERILATOR_SW_DV_TEST_STATUS_ADDR = VERILATOR_SW_DV_START_ADDR + 'h00;
+  localparam bit [31:0] VERILATOR_SW_DV_HW_ID_ADDR       = VERILATOR_SW_DV_START_ADDR + 'h04;
+
+  // Specific ID for SW-DV to identify that it's running on Verilator. This can be used by
+  // SW to adapt its behavior when running on Verilator vs other simulators or real hardware.
+  localparam bit [31:0] VERILATOR_HW_ID                  = 32'h0000_001A;
 
   // Signals to connect the sink
   top_pkg::axi_req_t  sim_sram_cpu_req;
@@ -228,10 +234,12 @@ module top_chip_verilator (
     .data     (`SIM_SRAM_IF.req.w.data[15:0] )  // Test status is 16-bits wide
   );
 
-  // Set the start address and the size of the simulation SRAM
+  // Set special SW-DV registers
   initial begin
     `SIM_SRAM_IF.start_addr                 = VERILATOR_SW_DV_START_ADDR;
     `SIM_SRAM_IF.sw_dv_size                 = VERILATOR_SW_DV_SIZE;
+    `SIM_SRAM_IF.hw_id_addr                 = VERILATOR_SW_DV_HW_ID_ADDR;
+    `SIM_SRAM_IF.hw_id                      = VERILATOR_HW_ID;
     u_sw_test_status_if.sw_test_status_addr = VERILATOR_SW_DV_TEST_STATUS_ADDR;
   end