[cov] Select some FPGA tests for CI setup validation

This commit adds the `coverage` tag to the `fpga_params` of several
smoke and functional tests. This allows these tests to be
automatically selected by the CI pipeline to validate the coverage
collection setup on FPGA targets.

Change-Id: I86d8e28ee885cf683d961dd5e1eaf44a100e8ad2
Signed-off-by: Yi-Hsuan Deng <yhdeng@google.com>

Author: sasdf

sw/device/lib/crypto/drivers/BUILD

@@ -179,6 +179,7 @@ opentitan_test(
     name = "entropy_test",
     srcs = ["entropy_test.c"],
     exec_env = EARLGREY_TEST_ENVS,
+    fpga = fpga_params(tags = ["coverage"]),
     verilator = verilator_params(
         timeout = "long",
         tags = ["broken"],  # TODO #16672 test broken by icache

sw/device/silicon_creator/lib/BUILD

@@ -77,6 +77,7 @@ opentitan_test(
             "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys": None,
         },
     ),
+    fpga = fpga_params(tags = ["coverage"]),
     verilator = verilator_params(
         timeout = "eternal",
         tags = ["flaky"],

sw/device/silicon_creator/lib/cert/BUILD

@@ -8,6 +8,7 @@ load(
 )
 load(
     "//rules/opentitan:defs.bzl",
+    "fpga_params",
     "opentitan_test",
 )
 
@@ -215,6 +216,7 @@ opentitan_test(
         "//hw/top_earlgrey:fpga_cw310_rom_ext": None,
         "//hw/top_earlgrey:sim_qemu_rom_ext": None,
     },
+    fpga = fpga_params(tags = ["coverage"]),
     deps = [
         ":dice_cwt",
         "//hw/top_earlgrey/ip_autogen/flash_ctrl:flash_ctrl_c_regs",

sw/device/silicon_creator/rom/e2e/clkmgr/BUILD

@@ -52,6 +52,7 @@ JITTER_TESTCASES = [
         "name": "enabled",
         "fpga": fpga_params(
             otp = ":otp_img_jitter_enabled",
+            tags = ["coverage"],
         ),
         "defines": ["TEST_JITTER_ENABLED"],
     },

sw/device/silicon_creator/rom_ext/e2e/boot_svc/BUILD

@@ -286,6 +286,7 @@ opentitan_test(
         assemble = "{rom_ext}@{rom_ext_slot_a} {firmware}@{owner_slot_a} {firmware}@{owner_slot_b}",
         exit_failure = "BFV:.*|PASS|FAIL",
         exit_success = "FinalBootLog: 3:AAA\r\n",
+        tags = ["coverage"],
     ),
     linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_owner_slot_virtual",
     qemu = qemu_params(

sw/device/tests/BUILD

@@ -4576,6 +4576,7 @@ opentitan_test(
             "//hw/top_earlgrey:silicon_creator": None,
         },
     ),
+    fpga = fpga_params(tags = ["coverage"]),
     deps = [
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",