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[dv/cov] Update coverage cfg paths to account for dropped _aon suffix
Signed-off-by: Florian Glaser <glaserf@lowrisc.org> [dv/cov] Update coverage cfg paths for new top-level wrapper Mirror the dv/cov path updates done earlier for the PD reorganization, this time accounting for the additional top_{topname} wrapper level. Coverage and exclusion paths now traverse tb.dut.top_{topname}.{topname}_pd_{main,aon}.u_* instead of tb.dut.top_{topname}.u_* or tb.dut.top_{topname}_pd_aon.u_*. For darjeeling, AON instances that had not yet been re-rooted under top_darjeeling_pd_aon are placed directly under top_darjeeling.darjeeling_pd_aon. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
1 parent 4b224cd commit 0debbf8

13 files changed

Lines changed: 38 additions & 38 deletions

‎hw/top_darjeeling/dv/cov/chip_cover.cfg‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ begin tgl(portsonly)
1717
// exclusion is documented in more detail in the issue lowrisc/opentitan#15427.
1818
-node tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex.u_core crash_dump_o.*
1919
-node tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex crash_dump_o.*
20-
-node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr_aon cpu_dump_i.*
20+
-node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr cpu_dump_i.*
2121
-node tb.dut.top_darjeeling.darjeeling_pd_main.u_alert_handler crashdump_o.*
22-
-node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr_aon alert_dump_i.*
22+
-node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr alert_dump_i.*
2323
end
2424

2525
// Include all coverage metrics in non-preverified modules.
@@ -59,7 +59,7 @@ end
5959
// TODO: Re-enable tgl(portsonly) on the excluded pre-verified sub-modules above in
6060
// non-preverified parents.
6161
begin tgl(portsonly)
62-
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender 1
62+
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux.gen_alert_tx[0].u_prim_alert_sender 1
6363
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender 1
6464
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender 1
6565
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender 1

‎hw/top_darjeeling/dv/cov/chip_cover_reg_top.cfg‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,13 @@
1414
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_otp_ctrl *tl_*
1515
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_lc_ctrl *tl_*
1616
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_alert_handler *tl_*
17-
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_pwrmgr_aon *tl_*
18-
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr_aon *tl_*
19-
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_clkmgr_aon *tl_*
20-
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux_aon *tl_*
21-
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_aon_timer_aon *tl_*
17+
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_pwrmgr *tl_*
18+
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_rstmgr *tl_*
19+
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_clkmgr *tl_*
20+
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux *tl_*
21+
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_aon_timer *tl_*
2222
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_sensor_ctrl *tl_*
23-
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_sram_ctrl_ret_aon *tl_*
23+
+node tb.dut.top_darjeeling.darjeeling_pd_aon.u_sram_ctrl_ret *tl_*
2424
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_flash_ctrl *tl_*
2525
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_dm *tl_*
2626
+node tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_plic *tl_*
@@ -43,7 +43,7 @@
4343

4444
// Only cover the `u_reg` instance of un-pre-verified modules.
4545
begin line+cond+fsm+branch+assert
46-
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux_aon.u_reg
46+
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_pinmux.u_reg
4747
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_plic.u_reg
4848
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_sensor_ctrl.u_reg
4949
+tree tb.dut.top_darjeeling.darjeeling_pd_main.u_rv_core_ibex.u_reg_cfg

‎hw/top_darjeeling/dv/cov/clkmgr_tgl_excl.cfg‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@
55
//======================================================================
66
// This file contains outputs of clkmgr tied to constants.
77
//======================================================================
8-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_powerup
9-
-node tb.dut*.u_clkmgr_aon.cg_en_o.main_powerup
10-
-node tb.dut*.u_clkmgr_aon.cg_en_o.io_powerup
11-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_peri
12-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_timers
13-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_secure
8+
-node tb.dut*.u_clkmgr.cg_en_o.aon_powerup
9+
-node tb.dut*.u_clkmgr.cg_en_o.main_powerup
10+
-node tb.dut*.u_clkmgr.cg_en_o.io_powerup
11+
-node tb.dut*.u_clkmgr.cg_en_o.aon_peri
12+
-node tb.dut*.u_clkmgr.cg_en_o.aon_timers
13+
-node tb.dut*.u_clkmgr.cg_en_o.aon_secure

‎hw/top_darjeeling/dv/cov/conn_ast_mem_cfg.el‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en"
107107
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv"
108108
Toggle ram_1p_cfg_i.ram_cfg.cfg "logic ram_1p_cfg_i.ram_cfg.cfg[3:0]"
109109
CHECKSUM: "2518565141 1739668335"
110-
INSTANCE: tb.dut.top_darjeeling.darjeeling_pd_aon.u_sram_ctrl_ret_aon
110+
INSTANCE: tb.dut.top_darjeeling.darjeeling_pd_aon.u_sram_ctrl_ret
111111
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv"
112112
Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en"
113113
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_darjeeling/formal/conn_csvs/ast_mem_cfg.csv"

‎hw/top_darjeeling/dv/cov/constfile.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@
44

55
// Syntax: instance {Top.M1} {x} {1'b0}
66
// TODO: This is unsupported!
7-
// instance {tb.dut.top_darjeeling.u_pinmux_aon} {mio_attr_o[0][8:4]} {5'b00000}
7+
// instance {tb.dut.top_darjeeling.u_pinmux} {mio_attr_o[0][8:4]} {5'b00000}

‎hw/top_darjeeling/dv/cov/pinmux_pad_attr.el‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1929,7 +1929,7 @@ Toggle dio_attr_i[10].drive_strength [2] "logic dio_attr_i[10].drive_strength[3:
19291929
ANNOTATION: "[UNR] Tie offs."
19301930
Toggle dio_attr_i[10].drive_strength [1] "logic dio_attr_i[10].drive_strength[3:0]"
19311931
CHECKSUM: "1538068739 3741435232"
1932-
INSTANCE: tb.dut.top_darjeeling.u_pinmux_aon
1932+
INSTANCE: tb.dut.top_darjeeling.u_pinmux
19331933
ANNOTATION: "[UNR] Tie offs."
19341934
Toggle mio_attr_o[9].slew_rate "logic mio_attr_o[9].slew_rate[1:0]"
19351935
ANNOTATION: "[UNR] Tie offs."
@@ -2817,7 +2817,7 @@ MODULE: prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )
28172817
ANNOTATION: "[UNR] Input ie_i is tied off to 1. This branch cannot be taken."
28182818
Branch 0 "2282619788" "ie_i" (1) "ie_i 0"
28192819
CHECKSUM: "1538068739 3449335269"
2820-
INSTANCE: tb.dut.top_darjeeling.u_pinmux_aon
2820+
INSTANCE: tb.dut.top_darjeeling.u_pinmux
28212821
ANNOTATION: "vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value."
28222822
Block 76 "0" "assign hw2reg.dio_pad_attr[0].slew_rate.d = dio_attr[0].slew_rate;"
28232823
ANNOTATION: "vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value."

‎hw/top_darjeeling/dv/cov/pwrmgr_tgl_excl.cfg‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,4 +5,4 @@
55
//======================================================================
66
// This file contains outputs of pwrmgr tied to constants.
77
//======================================================================
8-
-node tb.dut*.u_pwrmgr_aon.pwr_ast_o.slow_clk_en
8+
-node tb.dut*.u_pwrmgr.pwr_ast_o.slow_clk_en

‎hw/top_earlgrey/dv/cov/chip_cover.cfg‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ begin tgl(portsonly)
1717
// exclusion is documented in more detail in the issue lowrisc/opentitan#15427.
1818
-node tb.dut.top_earlgrey.earlgrey_pd_main.u_rv_core_ibex.u_core crash_dump_o.*
1919
-node tb.dut.top_earlgrey.earlgrey_pd_main.u_rv_core_ibex crash_dump_o.*
20-
-node tb.dut.top_earlgrey.earlgrey_pd_aon.u_rstmgr_aon cpu_dump_i.*
20+
-node tb.dut.top_earlgrey.earlgrey_pd_aon.u_rstmgr cpu_dump_i.*
2121
-node tb.dut.top_earlgrey.earlgrey_pd_main.u_alert_handler crashdump_o.*
22-
-node tb.dut.top_earlgrey.earlgrey_pd_aon.u_rstmgr_aon alert_dump_i.*
22+
-node tb.dut.top_earlgrey.earlgrey_pd_aon.u_rstmgr alert_dump_i.*
2323

2424
// [UNR] The pass through port on SPI_HOST1 is tied off / unused.
2525
-node tb.dut.top_earlgrey.earlgrey_pd_main.u_spi_host1 passthrough_i.*
@@ -64,7 +64,7 @@ end
6464
// TODO: Re-enable tgl(portsonly) on the excluded pre-verified sub-modules above in
6565
// non-preverified parents.
6666
begin tgl(portsonly)
67-
+tree tb.dut.top_earlgrey.earlgrey_pd_main.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender 1
67+
+tree tb.dut.top_earlgrey.earlgrey_pd_main.u_pinmux.gen_alert_tx[0].u_prim_alert_sender 1
6868
+tree tb.dut.top_earlgrey.earlgrey_pd_main.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender 1
6969
+tree tb.dut.top_earlgrey.earlgrey_pd_main.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender 1
7070
+tree tb.dut.top_earlgrey.earlgrey_pd_main.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender 1

‎hw/top_earlgrey/dv/cov/clkmgr_tgl_excl.cfg‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,12 @@
55
//======================================================================
66
// This file contains outputs of clkmgr tied to constants.
77
//======================================================================
8-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_powerup
9-
-node tb.dut*.u_clkmgr_aon.cg_en_o.usb_powerup
10-
-node tb.dut*.u_clkmgr_aon.cg_en_o.main_powerup
11-
-node tb.dut*.u_clkmgr_aon.cg_en_o.io_powerup
12-
-node tb.dut*.u_clkmgr_aon.cg_en_o.io_div2_powerup
13-
-node tb.dut*.u_clkmgr_aon.cg_en_o.io_div4_powerup
14-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_peri
15-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_timers
16-
-node tb.dut*.u_clkmgr_aon.cg_en_o.aon_secure
8+
-node tb.dut*.u_clkmgr.cg_en_o.aon_powerup
9+
-node tb.dut*.u_clkmgr.cg_en_o.usb_powerup
10+
-node tb.dut*.u_clkmgr.cg_en_o.main_powerup
11+
-node tb.dut*.u_clkmgr.cg_en_o.io_powerup
12+
-node tb.dut*.u_clkmgr.cg_en_o.io_div2_powerup
13+
-node tb.dut*.u_clkmgr.cg_en_o.io_div4_powerup
14+
-node tb.dut*.u_clkmgr.cg_en_o.aon_peri
15+
-node tb.dut*.u_clkmgr.cg_en_o.aon_timers
16+
-node tb.dut*.u_clkmgr.cg_en_o.aon_secure

‎hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en"
107107
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
108108
Toggle ram_1p_cfg_i.ram_cfg.cfg "logic ram_1p_cfg_i.ram_cfg.cfg[3:0]"
109109
CHECKSUM: "2518565141 1739668335"
110-
INSTANCE: tb.dut.top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret_aon
110+
INSTANCE: tb.dut.top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret
111111
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
112112
Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en"
113113
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"

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