[rtl,fpga] Add and integrate FPGA-only memory backdoor loader IP

The `bkdr_loader` IP is used to preload different ROM and OTP contents when running FPGA tests.
It poses a technology-independent replacement for the currently used bitstream splicing flow.

Co-authored-by: Alex Williams <awill@opentitan.org>
Signed-off-by: Alex Williams <awill@opentitan.org>
Signed-off-by: Thomas Benz <tbenz@lowrisc.org>

Author: a-will

hw/Makefile

@@ -22,6 +22,7 @@ endif
 IPS ?= aes           \
        adc_ctrl      \
        aon_timer     \
+       bkdr_loader   \
        csrng         \
        dma           \
        edn           \

hw/ip/BUILD

@@ -17,6 +17,7 @@ filegroup(
         "//hw/ip/adc_ctrl:rtl_files",
         "//hw/ip/aes:rtl_files",
         "//hw/ip/aon_timer:rtl_files",
+        "//hw/ip/bkdr_loader:rtl_files",
         "//hw/ip/csrng:rtl_files",
         "//hw/ip/dma:rtl_files",
         "//hw/ip/edn:rtl_files",

hw/ip/README.md

@@ -8,6 +8,7 @@
 | [`aes`]          | AES encryption and decryption engine with SCA and FI countermeasures                                                              |
 | [`aon_timer`]    | Wakeup and watchdog timers running on a low-power, always-on clock                                                                |
 | [`ascon`]        | Ascon authenticated encryption and decryption engine                                                                              |
+| [`bkdr_loader`]  | Provides FPGA-only indirect programming to RAMs                                                                                   |
 | [`csrng`]        | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software          |
 | [`dma`]          | DMA Controller for the integrated OpenTitan.                                                                                      |
 | [`edn`]          | Distributes random numbers produced by CSRNG to hardware blocks                                                                   |
@@ -40,6 +41,7 @@
 [`aes`]: ./aes/README.md
 [`aon_timer`]: ./aon_timer/README.md
 [`ascon`]: ./ascon/README.md
+[`bkdr_loader`]: ./bkdr_loader/README.md
 [`csrng`]: ./csrng/README.md
 [`dma`]: ./dma/README.md
 [`edn`]: ./edn/README.md

hw/ip/bkdr_loader/BUILD

@@ -0,0 +1,19 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "rtl_files",
+    srcs = glob(
+        ["**"],
+        exclude = [
+            "dv/**",
+            "doc/**",
+            "README.md",
+        ],
+    ) + [
+        "//hw/ip/bkdr_loader/data:all_files",
+    ],
+)

hw/ip/bkdr_loader/README.md

@@ -0,0 +1,36 @@
+# BKDR_LOADER Technical Specification
+<!-- BEGIN CMDGEN util/mdbook_regression_links.py --hjson hw/ip/bkdr_loader/data/bkdr_loader.hjson --top earlgrey -->
+| Regression | Version | [Stages](https://opentitan.org/book/doc/project_governance/development_stages.html) | Results |
+|-|-|-|-|
+ [`bkdr_loader`](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/dashboard.html) | 0.1.0 | D1, V0 | ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/bkdr_loader/test.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/bkdr_loader/passing.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/bkdr_loader/functional.svg) ![](https://dashboard.reports.lowrisc.org/opentitan/earlgrey/badge/bkdr_loader/code.svg) |
+
+<!-- END CMDGEN -->
+
+# Overview
+
+This document specifies the FPGA-only memory Backdoor Loader which is used to preload non-volatile
+and volatile memories on FPGA targets.
+
+
+## Features
+
+- No impact on ASIC implementation: loader RTL only in FPGA-specific files
+- Exposes FPGA-only registers such as the `USR_TIMESTAMP`
+- Up to 64 memory r/w targets supported
+- Automatic discovery of available targets by presenting a 32-bit target ID as well as width and depth
+- Access to raw BRAM data allowing to set both data and ECC arbitrarily for each target
+
+## Description
+
+The BKDR_LOADER intercepts the reset and JTAG signals between the FPGA pad array and the top-level
+OpenTitan instance. On reset, the IP samples the tap strap pins and becomes active if both strap
+signals are high (DFT mode on the ASIC).
+
+When active, the module keeps the reset to both the AST and OpenTitan asserted to prevent any access
+to non-initialized memory regions. It presents an internal RISC-V DTM over which the loader's internal
+[registers](doc/registers.md) can be accessed. The BKDR_LOADER presents both the number of targets and key target
+information through its register space.
+
+After completing preloading and data validation, the loader is deactivated until the next
+button reset via the control register. In this case, the JTAG signals are forwarded to OpenTitan
+and the reset to the AST and OpenTitan is de-asserted.

hw/ip/bkdr_loader/bkdr_loader.core

@@ -0,0 +1,75 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:bkdr_loader:0.1"
+description: "Backdoor Memory Loader intended for FPGAs"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:all
+      - lowrisc:ip:tlul
+    files:
+      - rtl/bkdr_loader.svh : {is_include_file : true}
+      - rtl/bkdr_loader_reg_pkg.sv
+      - rtl/bkdr_loader_regs_reg_top.sv
+      - rtl/bkdr_loader_pkg.sv
+      - rtl/bkdr_loader.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+    file_type: veribleLintWaiver
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_verilator  ? (files_verilator_waiver)
+      - tool_ascentlint ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl
+    toplevel: bkdr_loader
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
+
+  syn:
+    <<: *default_target
+    # TODO: set default to DC once
+    # this option is available
+    # olofk/edalize#89
+    default_tool: icarus
+    parameters:
+      - SYNTHESIS=true

hw/ip/bkdr_loader/data/BUILD

@@ -0,0 +1,10 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)