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SamuelRiedelnasahlpa
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[sw] Add mcounteren_writable test
Software test to verify that the `mcounteren_writable` can be set and cleared and locked. This test also verifies that it locks the `mcounteren` CSR in Ibex Signed-off-by: Samuel Riedel <sriedel@lowrisc.org>
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‎hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson‎

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tests: ["chip_sw_rv_core_ibex_lockstep_glitch"]
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bazel: []
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}
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{
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name: chip_sw_rv_core_ibex_mcounteren_writable
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desc: '''Verifies that the mcounteren_writable register is lockable.
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'''
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stage: V2
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si_stage: SV1
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lc_states: ["PROD"]
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tests: ["chip_sw_rv_core_ibex_mcounteren_writable"]
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bazel: ["//sw/device/tests:rv_core_ibex_mcounteren_writable_test"]
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}
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{
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name: chip_sw_rv_core_ibex_alerts
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desc: '''Inject and verify all available faults in rv_core_ibex / ibex_top.

‎hw/top_earlgrey/dv/chip_sim_cfg.hjson‎

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sw_images: ["//sw/device/tests:rv_core_ibex_icache_invalidate_test:1:new_rules"]
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en_run_modes: ["sw_test_mode_test_rom"]
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}
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{
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name: chip_sw_rv_core_ibex_mcounteren_writable
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uvm_test_seq: chip_sw_base_vseq
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sw_images: ["//sw/device/tests:rv_core_ibex_mcounteren_writable_test:1:new_rules"]
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en_run_modes: ["sw_test_mode_test_rom"]
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run_opts: ["+sw_test_timeout_ns=7_000_000"]
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}
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{
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name: chip_sw_usb_ast_clk_calib
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uvm_test_seq: "chip_sw_usb_ast_clk_calib_vseq"

‎sw/device/tests/BUILD‎

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],
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)
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opentitan_test(
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name = "rv_core_ibex_mcounteren_writable_test",
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srcs = ["rv_core_ibex_mcounteren_writable_test.c"],
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exec_env = EARLGREY_TEST_ENVS,
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deps = [
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"//hw/top:rv_core_ibex_c_regs",
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"//hw/top_earlgrey/sw/autogen:top_earlgrey",
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"//sw/device/lib/base:mmio",
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"//sw/device/lib/base:multibits",
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"//sw/device/lib/testing/test_framework:check",
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"//sw/device/lib/testing/test_framework:ottf_main",
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],
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)
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opentitan_test(
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name = "rv_core_ibex_epmp_test_functest",
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srcs = ["//sw/device/silicon_creator/manuf/tests:idle_functest.c"],

‎sw/device/tests/rv_core_ibex_mcounteren_writable_test.c‎

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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Verifies that the mcounteren_writable register properly locks the mcounteren
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// CSR and that the register is write-protected when locked.
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#include "sw/device/lib/base/mmio.h"
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#include "sw/device/lib/base/multibits.h"
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#include "sw/device/lib/testing/test_framework/check.h"
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#include "sw/device/lib/testing/test_framework/ottf_main.h"
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#include "hw/top/rv_core_ibex_regs.h"
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#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
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#define MCOUNTERS_DISABLE (0x0)
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#define MCOUNTERS_ENABLE (0x5)
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OTTF_DEFINE_TEST_CONFIG();
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// Helper functions for accessing the mcounteren CSR
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static inline uint32_t csr_read_mcounteren(void) {
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uint32_t val;
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asm volatile("csrr %0, mcounteren" : "=r"(val));
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return val;
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}
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static inline void csr_write_mcounteren(uint32_t val) {
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asm volatile("csrw mcounteren, %0" ::"r"(val));
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}
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bool test_main(void) {
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uint32_t mcounteren_val;
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uint32_t mcounteren_writable_val;
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uint32_t regwen;
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mmio_region_t ibex_cfg =
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mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR);
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// Initialize mcounteren to a known value for testing.
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csr_write_mcounteren(MCOUNTERS_DISABLE);
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// Check defaults
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// MCOUNTEREN_WRITABLE should default to kMultiBitBool4True.
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4True,
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"MCOUNTEREN_WRITABLE default should be MuBi4True (0x%x), got 0x%x",
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kMultiBitBool4True, mcounteren_writable_val);
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// REGWEN should be enabled by default.
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regwen = mmio_region_read32(
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ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_REG_OFFSET);
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CHECK(regwen == 1, "MCOUNTEREN_WRITABLE_REGWEN default should be 1, got 0x%x",
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regwen);
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// Since MCOUNTEREN_WRITABLE is True, writes to mcounteren should succeed.
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csr_write_mcounteren(MCOUNTERS_ENABLE);
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mcounteren_val = csr_read_mcounteren();
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CHECK(mcounteren_val == MCOUNTERS_ENABLE,
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"mcounteren should be writable when MCOUNTEREN_WRITABLE is True. "
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"Expected 0x%x, got 0x%x",
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MCOUNTERS_ENABLE, mcounteren_val);
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// Locking should succeed while REGWEN is enabled.
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mmio_region_write32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET,
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kMultiBitBool4False);
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4False,
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"MCOUNTEREN_WRITABLE write should succeed when unlocked, got 0x%x",
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mcounteren_writable_val);
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// Since MCOUNTEREN_WRITABLE is now False, writes to mcounteren should be
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// ignored.
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csr_write_mcounteren(MCOUNTERS_DISABLE);
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mcounteren_val = csr_read_mcounteren();
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CHECK(mcounteren_val == MCOUNTERS_ENABLE,
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"mcounteren writes should be blocked when MCOUNTEREN_WRITABLE is "
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"False. Expected 0x%x, got 0x%x",
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MCOUNTERS_ENABLE, mcounteren_val);
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// Unlocking should succeed while REGWEN is enabled.
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mmio_region_write32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET,
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kMultiBitBool4True);
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4True,
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"MCOUNTEREN_WRITABLE write should succeed when unlocked, got 0x%x",
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mcounteren_writable_val);
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// Ensure mcounteren is writable again after restoring MCOUNTEREN_WRITABLE to
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// True.
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csr_write_mcounteren(MCOUNTERS_DISABLE);
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mcounteren_val = csr_read_mcounteren();
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CHECK(mcounteren_val == MCOUNTERS_DISABLE,
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"mcounteren should be writable again after restoring config. Expected "
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"0x%x, got 0x%x",
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MCOUNTERS_DISABLE, mcounteren_val);
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// Enable mcounteren again.
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csr_write_mcounteren(MCOUNTERS_ENABLE);
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mcounteren_val = csr_read_mcounteren();
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CHECK(mcounteren_val == MCOUNTERS_ENABLE,
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"mcounteren should be writable again after restoring config. Expected "
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"0x%x, got 0x%x",
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MCOUNTERS_ENABLE, mcounteren_val);
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// Lock again, which should succeed.
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mmio_region_write32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET,
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kMultiBitBool4False);
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4False,
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"MCOUNTEREN_WRITABLE write should succeed when unlocked, got 0x%x",
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mcounteren_writable_val);
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// Clear REGWEN to lock MCOUNTEREN_WRITABLE.
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mmio_region_write32(ibex_cfg,
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RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_REG_OFFSET, 0);
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regwen = mmio_region_read32(
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ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_REG_OFFSET);
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CHECK(regwen == 0,
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"MCOUNTEREN_WRITABLE_REGWEN should read 0 after clearing, got 0x%x",
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regwen);
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// Write to MCOUNTEREN_WRITABLE while locked should have no effect.
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mmio_region_write32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET,
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kMultiBitBool4True);
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4False,
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"MCOUNTEREN_WRITABLE should be unchanged when locked, got 0x%x",
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mcounteren_writable_val);
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// Since the attempt to flip MCOUNTEREN_WRITABLE to True was
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// ignored, writes to mcounteren should be ignored.
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csr_write_mcounteren(MCOUNTERS_DISABLE);
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mcounteren_val = csr_read_mcounteren();
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CHECK(mcounteren_val == MCOUNTERS_ENABLE,
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"mcounteren writes should be blocked when MCOUNTEREN_WRITABLE is "
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"False. Expected 0x%x, got 0x%x",
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MCOUNTERS_ENABLE, mcounteren_val);
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// Attempt to re-enable REGWEN should fail
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mmio_region_write32(ibex_cfg,
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RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_REG_OFFSET, 1);
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regwen = mmio_region_read32(
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ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_REG_OFFSET);
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CHECK(regwen == 0,
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"MCOUNTEREN_WRITABLE_REGWEN should remain 0 after attempted "
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"re-enable, got 0x%x",
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regwen);
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// Write to MCOUNTEREN_WRITABLE while locked should have no effect.
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mmio_region_write32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET,
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kMultiBitBool4True);
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mcounteren_writable_val =
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mmio_region_read32(ibex_cfg, RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REG_OFFSET);
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CHECK(mcounteren_writable_val == kMultiBitBool4False,
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"MCOUNTEREN_WRITABLE should be unchanged when locked, got 0x%x",
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mcounteren_writable_val);
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return true;
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}

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