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[sw/host] Drop aon IP suffix
As a counterpart to the preceeding commit, this one gets rid of all traces of the various forms of the Aon suffix for the host software, including scripts for the penetration tests. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
1 parent eea739b commit 71ab093

9 files changed

Lines changed: 92 additions & 94 deletions

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‎sw/host/opentitanlib/src/test_utils/crashdump.rs‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ pub fn read_cpu_crashdump_data(
2727

2828
// Make sure that CPU_INFO is writable.
2929
jtag.read_memory32(
30-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::CpuRegwen as u32,
30+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::CpuRegwen as u32,
3131
&mut buf,
3232
)?;
3333
if buf[0] & RstmgrCpuRegwen::EN == 0 {
@@ -36,18 +36,18 @@ pub fn read_cpu_crashdump_data(
3636

3737
let mut cpu_crashdump_info = [0u32; 16];
3838
jtag.read_memory32(
39-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::CpuInfoAttr as u32,
39+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::CpuInfoAttr as u32,
4040
&mut buf,
4141
)?;
4242
let len = buf[0];
4343
log::info!("CPU Crash Dump Info ({:?} words):", len);
4444
for i in 0..len {
4545
jtag.write_memory32(
46-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::CpuInfoCtrl as u32,
46+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::CpuInfoCtrl as u32,
4747
&[RstmgrCpuInfoCtrl::INDEX.emplace(i) | RstmgrCpuInfoCtrl::EN],
4848
)?;
4949
jtag.read_memory32(
50-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::CpuInfo as u32,
50+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::CpuInfo as u32,
5151
&mut buf,
5252
)?;
5353
cpu_crashdump_info[i as usize] = buf[0];
@@ -79,18 +79,18 @@ pub fn read_alert_crashdump_data(
7979

8080
let mut buf = [0u32];
8181
jtag.read_memory32(
82-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::AlertInfoAttr as u32,
82+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::AlertInfoAttr as u32,
8383
&mut buf,
8484
)?;
8585
let len = buf[0];
8686
log::info!("Alert Crash Dump Info ({:?} words):", len);
8787
for i in 0..len {
8888
jtag.write_memory32(
89-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::AlertInfoCtrl as u32,
89+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::AlertInfoCtrl as u32,
9090
&[RstmgrAlertInfoCtrl::INDEX.emplace(i) | RstmgrAlertInfoCtrl::EN],
9191
)?;
9292
jtag.read_memory32(
93-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::AlertInfo as u32,
93+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::AlertInfo as u32,
9494
&mut buf,
9595
)?;
9696
log::info!(" Word {:?} = 0x{:x?}", i, buf[0]);
@@ -111,7 +111,7 @@ pub fn read_reset_reason(transport: &TransportWrapper, jtag_params: &JtagParams)
111111

112112
let mut buf = [0u32];
113113
jtag.read_memory32(
114-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32 + RstmgrReg::ResetInfo as u32,
114+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + RstmgrReg::ResetInfo as u32,
115115
&mut buf,
116116
)?;
117117
let reset_reason = buf[0];

‎sw/host/opentitanlib/src/test_utils/extclk.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ pub struct ExternalClock;
2929

3030
impl ExternalClock {
3131
/// Base address of the clock manager.
32-
const CLKMGR_BASE_ADDR: u32 = top_earlgrey::CLKMGR_AON_BASE_ADDR as u32;
32+
const CLKMGR_BASE_ADDR: u32 = top_earlgrey::CLKMGR_BASE_ADDR as u32;
3333

3434
/// Addresses of clock manager registers in memory.
3535
const EXTCLK_CTRL_REGWEN_ADDR: u32 =

‎sw/host/penetrationtests/python/fi/test_scripts/fi_alert_python_test.py‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,9 @@
3232
case_to_alert_list_map = [
3333
42, # Case 0 maps to alert_list index 42 ("aes_recov_ctrl_update_err")
3434
43, # Case 1 maps to alert_list index 43 ("aes_fatal_fault")
35-
31, # Case 2 maps to alert_list index 31 ("aon_timer_aon_fatal_fault")
36-
25, # Case 3 maps to alert_list index 25 ("clkmgr_aon_recov_fault")
37-
26, # Case 4 maps to alert_list index 26 ("clkmgr_aon_fatal_fault")
35+
31, # Case 2 maps to alert_list index 31 ("aon_timer_fatal_fault")
36+
25, # Case 3 maps to alert_list index 25 ("clkmgr_recov_fault")
37+
26, # Case 4 maps to alert_list index 26 ("clkmgr_fatal_fault")
3838
51, # Case 5 maps to alert_list index 51 ("csrng_recov_alert")
3939
52, # Case 6 maps to alert_list index 52 ("csrng_fatal_alert")
4040
55, # Case 7 maps to alert_list index 55 ("edn0_recov_alert")
@@ -67,11 +67,11 @@
6767
13, # Case 34 maps to alert_list index 13 ("otp_ctrl_fatal_bus_integ_error")
6868
14, # Case 35 maps to alert_list index 14 ("otp_ctrl_fatal_prim_otp_alert")
6969
15, # Case 36 maps to alert_list index 15 ("otp_ctrl_recov_prim_otp_alert")
70-
30, # Case 37 maps to alert_list index 30 ("pinmux_aon_fatal_fault")
71-
22, # Case 38 maps to alert_list index 22 ("pwrmgr_aon_fatal_fault")
70+
30, # Case 37 maps to alert_list index 30 ("pinmux_fatal_fault")
71+
22, # Case 38 maps to alert_list index 22 ("pwrmgr_fatal_fault")
7272
60, # Case 39 maps to alert_list index 60 ("rom_ctrl_fatal")
73-
23, # Case 40 maps to alert_list index 23 ("rstmgr_aon_fatal_fault")
74-
24, # Case 41 maps to alert_list index 24 ("rstmgr_aon_fatal_cnsty_fault")
73+
23, # Case 40 maps to alert_list index 23 ("rstmgr_fatal_fault")
74+
24, # Case 41 maps to alert_list index 24 ("rstmgr_fatal_cnsty_fault")
7575
61, # Case 42 maps to alert_list index 61 ("rv_core_ibex_fatal_sw_err")
7676
62, # Case 43 maps to alert_list index 62 ("rv_core_ibex_recov_sw_err")
7777
63, # Case 44 maps to alert_list index 63 ("rv_core_ibex_fatal_hw_err")
@@ -84,8 +84,8 @@
8484
19, # Case 51 maps to alert_list index 19 ("spi_host0_fatal_fault")
8585
20, # Case 52 maps to alert_list index 20 ("spi_host1_fatal_fault")
8686
59, # Case 53 maps to alert_list index 59 ("sram_ctrl_main_fatal_error")
87-
34, # Case 54 maps to alert_list index 34 ("sram_ctrl_ret_aon_fatal_error")
88-
27, # Case 55 maps to alert_list index 27 ("sysrst_ctrl_aon_fatal_fault")
87+
34, # Case 54 maps to alert_list index 34 ("sram_ctrl_ret_fatal_error")
88+
27, # Case 55 maps to alert_list index 27 ("sysrst_ctrl_fatal_fault")
8989
0, # Case 56 maps to alert_list index 0 ("uart0_fatal_fault")
9090
1, # Case 57 maps to alert_list index 1 ("uart1_fatal_fault")
9191
2, # Case 58 maps to alert_list index 2 ("uart2_fatal_fault")

‎sw/host/penetrationtests/python/util/common_library.py‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -49,18 +49,18 @@
4949
2, # "spi_host0_fatal_fault",
5050
2, # "spi_host1_fatal_fault",
5151
2, # "usbdev_fatal_fault",
52-
0, # "pwrmgr_aon_fatal_fault",
53-
0, # "rstmgr_aon_fatal_fault",
54-
0, # "rstmgr_aon_fatal_cnsty_fault",
55-
1, # "clkmgr_aon_recov_fault",
56-
0, # "clkmgr_aon_fatal_fault",
57-
2, # "sysrst_ctrl_aon_fatal_fault",
58-
2, # "adc_ctrl_aon_fatal_fault",
59-
2, # "pinmux_aon_fatal_fault",
60-
0, # "aon_timer_aon_fatal_fault",
52+
0, # "pwrmgr_fatal_fault",
53+
0, # "rstmgr_fatal_fault",
54+
0, # "rstmgr_fatal_cnsty_fault",
55+
1, # "clkmgr_recov_fault",
56+
0, # "clkmgr_fatal_fault",
57+
2, # "sysrst_ctrl_fatal_fault",
58+
2, # "adc_ctrl_fatal_fault",
59+
2, # "pinmux_fatal_fault",
60+
0, # "aon_timer_fatal_fault",
6161
1, # "sensor_ctrl_recov_alert",
6262
0, # "sensor_ctrl_fatal_alert",
63-
0, # "sram_ctrl_ret_aon_fatal_error",
63+
0, # "sram_ctrl_ret_fatal_error",
6464
1, # "flash_ctrl_recov_err",
6565
0, # "flash_ctrl_fatal_std_err",
6666
0, # "flash_ctrl_fatal_err",
@@ -123,18 +123,18 @@
123123
True, # "spi_host0_fatal_fault",
124124
True, # "spi_host1_fatal_fault",
125125
True, # "usbdev_fatal_fault",
126-
True, # "pwrmgr_aon_fatal_fault",
127-
True, # "rstmgr_aon_fatal_fault",
128-
True, # "rstmgr_aon_fatal_cnsty_fault",
129-
True, # "clkmgr_aon_recov_fault",
130-
True, # "clkmgr_aon_fatal_fault",
131-
True, # "sysrst_ctrl_aon_fatal_fault",
132-
True, # "adc_ctrl_aon_fatal_fault",
133-
True, # "pinmux_aon_fatal_fault",
134-
True, # "aon_timer_aon_fatal_fault",
126+
True, # "pwrmgr_fatal_fault",
127+
True, # "rstmgr_fatal_fault",
128+
True, # "rstmgr_fatal_cnsty_fault",
129+
True, # "clkmgr_recov_fault",
130+
True, # "clkmgr_fatal_fault",
131+
True, # "sysrst_ctrl_fatal_fault",
132+
True, # "adc_ctrl_fatal_fault",
133+
True, # "pinmux_fatal_fault",
134+
True, # "aon_timer_fatal_fault",
135135
True, # "sensor_ctrl_recov_alert",
136136
True, # "sensor_ctrl_fatal_alert",
137-
True, # "sram_ctrl_ret_aon_fatal_error",
137+
True, # "sram_ctrl_ret_fatal_error",
138138
True, # "flash_ctrl_recov_err",
139139
True, # "flash_ctrl_fatal_std_err",
140140
True, # "flash_ctrl_fatal_err",
@@ -196,18 +196,18 @@
196196
2, # "spi_host0_fatal_fault",
197197
2, # "spi_host1_fatal_fault",
198198
2, # "usbdev_fatal_fault",
199-
0, # "pwrmgr_aon_fatal_fault",
200-
0, # "rstmgr_aon_fatal_fault",
201-
0, # "rstmgr_aon_fatal_cnsty_fault",
202-
1, # "clkmgr_aon_recov_fault",
203-
0, # "clkmgr_aon_fatal_fault",
204-
2, # "sysrst_ctrl_aon_fatal_fault",
205-
2, # "adc_ctrl_aon_fatal_fault",
206-
2, # "pinmux_aon_fatal_fault",
207-
0, # "aon_timer_aon_fatal_fault",
199+
0, # "pwrmgr_fatal_fault",
200+
0, # "rstmgr_fatal_fault",
201+
0, # "rstmgr_fatal_cnsty_fault",
202+
1, # "clkmgr_recov_fault",
203+
0, # "clkmgr_fatal_fault",
204+
2, # "sysrst_ctrl_fatal_fault",
205+
2, # "adc_ctrl_fatal_fault",
206+
2, # "pinmux_fatal_fault",
207+
0, # "aon_timer_fatal_fault",
208208
1, # "sensor_ctrl_recov_alert",
209209
0, # "sensor_ctrl_fatal_alert",
210-
0, # "sram_ctrl_ret_aon_fatal_error",
210+
0, # "sram_ctrl_ret_fatal_error",
211211
1, # "flash_ctrl_recov_err",
212212
0, # "flash_ctrl_fatal_std_err",
213213
0, # "flash_ctrl_fatal_err",
@@ -261,18 +261,18 @@
261261
True, # "spi_host0_fatal_fault",
262262
True, # "spi_host1_fatal_fault",
263263
True, # "usbdev_fatal_fault",
264-
True, # "pwrmgr_aon_fatal_fault",
265-
True, # "rstmgr_aon_fatal_fault",
266-
True, # "rstmgr_aon_fatal_cnsty_fault",
267-
True, # "clkmgr_aon_recov_fault",
268-
True, # "clkmgr_aon_fatal_fault",
269-
True, # "sysrst_ctrl_aon_fatal_fault",
270-
True, # "adc_ctrl_aon_fatal_fault",
271-
True, # "pinmux_aon_fatal_fault",
272-
True, # "aon_timer_aon_fatal_fault",
264+
True, # "pwrmgr_fatal_fault",
265+
True, # "rstmgr_fatal_fault",
266+
True, # "rstmgr_fatal_cnsty_fault",
267+
True, # "clkmgr_recov_fault",
268+
True, # "clkmgr_fatal_fault",
269+
True, # "sysrst_ctrl_fatal_fault",
270+
True, # "adc_ctrl_fatal_fault",
271+
True, # "pinmux_fatal_fault",
272+
True, # "aon_timer_fatal_fault",
273273
True, # "sensor_ctrl_recov_alert",
274274
True, # "sensor_ctrl_fatal_alert",
275-
True, # "sram_ctrl_ret_aon_fatal_error",
275+
True, # "sram_ctrl_ret_fatal_error",
276276
True, # "flash_ctrl_recov_err",
277277
True, # "flash_ctrl_fatal_std_err",
278278
# On FPGA, this alert always raised, so leave it off
@@ -344,18 +344,18 @@
344344
2, # "spi_host0_fatal_fault",
345345
2, # "spi_host1_fatal_fault",
346346
2, # "usbdev_fatal_fault",
347-
0, # "pwrmgr_aon_fatal_fault",
348-
0, # "rstmgr_aon_fatal_fault",
349-
0, # "rstmgr_aon_fatal_cnsty_fault",
350-
1, # "clkmgr_aon_recov_fault",
351-
0, # "clkmgr_aon_fatal_fault",
352-
2, # "sysrst_ctrl_aon_fatal_fault",
353-
2, # "adc_ctrl_aon_fatal_fault",
354-
2, # "pinmux_aon_fatal_fault",
355-
0, # "aon_timer_aon_fatal_fault",
347+
0, # "pwrmgr_fatal_fault",
348+
0, # "rstmgr_fatal_fault",
349+
0, # "rstmgr_fatal_cnsty_fault",
350+
1, # "clkmgr_recov_fault",
351+
0, # "clkmgr_fatal_fault",
352+
2, # "sysrst_ctrl_fatal_fault",
353+
2, # "adc_ctrl_fatal_fault",
354+
2, # "pinmux_fatal_fault",
355+
0, # "aon_timer_fatal_fault",
356356
1, # "sensor_ctrl_recov_alert",
357357
0, # "sensor_ctrl_fatal_alert",
358-
0, # "sram_ctrl_ret_aon_fatal_error",
358+
0, # "sram_ctrl_ret_fatal_error",
359359
1, # "flash_ctrl_recov_err",
360360
0, # "flash_ctrl_fatal_std_err",
361361
0, # "flash_ctrl_fatal_err",
@@ -409,18 +409,18 @@
409409
True, # "spi_host0_fatal_fault",
410410
True, # "spi_host1_fatal_fault",
411411
True, # "usbdev_fatal_fault",
412-
True, # "pwrmgr_aon_fatal_fault",
413-
True, # "rstmgr_aon_fatal_fault",
414-
True, # "rstmgr_aon_fatal_cnsty_fault",
415-
True, # "clkmgr_aon_recov_fault",
416-
True, # "clkmgr_aon_fatal_fault",
417-
True, # "sysrst_ctrl_aon_fatal_fault",
418-
True, # "adc_ctrl_aon_fatal_fault",
419-
True, # "pinmux_aon_fatal_fault",
420-
True, # "aon_timer_aon_fatal_fault",
412+
True, # "pwrmgr_fatal_fault",
413+
True, # "rstmgr_fatal_fault",
414+
True, # "rstmgr_fatal_cnsty_fault",
415+
True, # "clkmgr_recov_fault",
416+
True, # "clkmgr_fatal_fault",
417+
True, # "sysrst_ctrl_fatal_fault",
418+
True, # "adc_ctrl_fatal_fault",
419+
True, # "pinmux_fatal_fault",
420+
True, # "aon_timer_fatal_fault",
421421
True, # "sensor_ctrl_recov_alert",
422422
True, # "sensor_ctrl_fatal_alert",
423-
True, # "sram_ctrl_ret_aon_fatal_error",
423+
True, # "sram_ctrl_ret_fatal_error",
424424
True, # "flash_ctrl_recov_err",
425425
True, # "flash_ctrl_fatal_std_err",
426426
# On FPGA, this alert always raised, so leave it off

‎sw/host/tests/chip/jtag/src/openocd_test.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ fn test_openocd(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
116116

117117
// Test bulk read/writes by reading the content of the RAM, then overwrite it with
118118
// known values and try to read-back, we restore the content afterwards
119-
let test_ram_addr = top_earlgrey::SRAM_CTRL_RET_AON_RAM_BASE_ADDR as u32;
119+
let test_ram_addr = top_earlgrey::SRAM_CTRL_RET_RAM_BASE_ADDR as u32;
120120
const SIZE: usize = 20;
121121
let mut ram = [0u8; SIZE];
122122
assert_eq!(jtag.read_memory(test_ram_addr, &mut ram)?, SIZE);

‎sw/host/tests/chip/rv_dm/src/csr_rw.rs‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
8181
("aes", top_earlgrey::AES_BASE_ADDR, dif::AES_IV_0_REG_OFFSET),
8282
(
8383
"adc_ctrl",
84-
top_earlgrey::ADC_CTRL_AON_BASE_ADDR,
84+
top_earlgrey::ADC_CTRL_BASE_ADDR,
8585
dif::ADC_CTRL_INTR_ENABLE_REG_OFFSET,
8686
),
8787
(
@@ -91,7 +91,7 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
9191
),
9292
(
9393
"aon_timer",
94-
top_earlgrey::AON_TIMER_AON_BASE_ADDR,
94+
top_earlgrey::AON_TIMER_BASE_ADDR,
9595
dif::AON_TIMER_WKUP_CTRL_REG_OFFSET,
9696
),
9797
(
@@ -166,18 +166,18 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
166166
),
167167
(
168168
"pinmux",
169-
top_earlgrey::PINMUX_AON_BASE_ADDR,
169+
top_earlgrey::PINMUX_BASE_ADDR,
170170
dif::PINMUX_MIO_PAD_ATTR_0_REG_OFFSET,
171171
),
172172
(
173173
"pwrmgr",
174-
top_earlgrey::PWRMGR_AON_BASE_ADDR,
174+
top_earlgrey::PWRMGR_BASE_ADDR,
175175
dif::PWRMGR_INTR_ENABLE_REG_OFFSET,
176176
),
177177
// Skip ROM_CTRL which does not have RW registers
178178
(
179179
"rstmgr",
180-
top_earlgrey::RSTMGR_AON_BASE_ADDR,
180+
top_earlgrey::RSTMGR_BASE_ADDR,
181181
dif::RSTMGR_CPU_INFO_CTRL_REG_OFFSET,
182182
),
183183
(
@@ -187,7 +187,7 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
187187
),
188188
(
189189
"sensor_ctrl",
190-
top_earlgrey::SENSOR_CTRL_AON_BASE_ADDR,
190+
top_earlgrey::SENSOR_CTRL_BASE_ADDR,
191191
dif::SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,
192192
),
193193
(
@@ -207,7 +207,7 @@ fn test_csr_rw(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
207207
),
208208
(
209209
"sysrst_ctrl",
210-
top_earlgrey::SYSRST_CTRL_AON_BASE_ADDR,
210+
top_earlgrey::SYSRST_CTRL_BASE_ADDR,
211211
dif::SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
212212
),
213213
(

‎sw/host/tests/chip/rv_dm/src/mem_access.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,8 @@ fn test_mem_access(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
7676
let rw_regions = [
7777
(
7878
"ram_ret",
79-
top_earlgrey::SRAM_CTRL_RET_AON_RAM_BASE_ADDR as u32,
80-
top_earlgrey::SRAM_CTRL_RET_AON_RAM_SIZE_BYTES as u32,
79+
top_earlgrey::SRAM_CTRL_RET_RAM_BASE_ADDR as u32,
80+
top_earlgrey::SRAM_CTRL_RET_RAM_SIZE_BYTES as u32,
8181
),
8282
(
8383
"ram_main",

‎sw/host/tests/rom/e2e_openocd_debug_test/src/asm_watchdog_bite.rs‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ fn asm_watchdog_bite(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
5656
// We don't want the bark to trigger for this test.
5757
// There's no label before BARK_THOLD is stored, so we need to override the stored value.
5858
dbg.write_u32(
59-
top_earlgrey::AON_TIMER_AON_BASE_ADDR as u32
59+
top_earlgrey::AON_TIMER_BASE_ADDR as u32
6060
+ ot_hal::dif::aon_timer::AonTimerReg::WdogBarkThold as u32,
6161
0xFFFFFFFF,
6262
)?;
@@ -67,8 +67,7 @@ fn asm_watchdog_bite(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
6767

6868
// Clear RESET_INFO.
6969
dbg.write_u32(
70-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32
71-
+ ot_hal::dif::rstmgr::RstmgrReg::ResetInfo as u32,
70+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + ot_hal::dif::rstmgr::RstmgrReg::ResetInfo as u32,
7271
0,
7372
)?;
7473

@@ -97,8 +96,7 @@ fn asm_watchdog_bite(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
9796

9897
// Check the reset reason as well
9998
let reset_info = dbg.read_u32(
100-
top_earlgrey::RSTMGR_AON_BASE_ADDR as u32
101-
+ ot_hal::dif::rstmgr::RstmgrReg::ResetInfo as u32,
99+
top_earlgrey::RSTMGR_BASE_ADDR as u32 + ot_hal::dif::rstmgr::RstmgrReg::ResetInfo as u32,
102100
)?;
103101

104102
// Check that the reset is caused by watchdog.

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