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[cheriot,rtl] Integrate CHERIoT switch into rv_core_ibex
Signed-off-by: Thomas Benz <tbenz@lowrisc.org>
1 parent 1a4f8f0 commit acd2c5d

21 files changed

Lines changed: 1085 additions & 448 deletions

‎hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,6 +1105,40 @@
11051105
]
11061106
},
11071107

1108+
{ name: "CHERIOT_ENA",
1109+
desc: '''
1110+
Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False).
1111+
''',
1112+
swaccess: "wo",
1113+
hwaccess: "hro",
1114+
fields: [
1115+
{ bits: "3:0",
1116+
name: "VAL",
1117+
resval: "0x0"
1118+
desc: '''
1119+
'''
1120+
},
1121+
]
1122+
},
1123+
1124+
{ name: "CHERIOT_LOCK",
1125+
desc: '''
1126+
Locks the CHERIoT/ePMP mode.
1127+
If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register.
1128+
''',
1129+
swaccess: "wo",
1130+
hwaccess: "hro",
1131+
hwext: "true",
1132+
hwqe: "true",
1133+
fields: [
1134+
{ bits: "3:0",
1135+
name: "VAL",
1136+
desc: '''
1137+
'''
1138+
},
1139+
]
1140+
},
1141+
11081142
{ name: "FPGA_INFO",
11091143
desc: '''
11101144
FPGA build timestamp info.

‎hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl‎

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,11 @@ module ${module_instance_name}
252252
// core sleeping
253253
logic core_sleep;
254254

255+
// CHERIoT signals
256+
prim_mubi_pkg::mubi4_t cheriot_ena;
257+
logic cheriot_switch_error;
258+
logic unused_cheriot;
259+
255260
// The following intermediate signals are created to aid in simulations.
256261
//
257262
// If a parent port is connected directly to a port of sub-modules, the implicit wire connection
@@ -1055,6 +1060,29 @@ module ${module_instance_name}
10551060
assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q;
10561061
assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q;
10571062

1063+
////////////////////
1064+
// CHERIoT switch
1065+
////////////////////
1066+
1067+
if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_switch
1068+
cheriot_switch u_cheriot_switch (
1069+
.clk_i,
1070+
.rst_ni,
1071+
.ena_i (reg2hw.cheriot_ena.q),
1072+
.lock_i (reg2hw.cheriot_lock.q),
1073+
.lock_access_i(reg2hw.cheriot_lock.qe),
1074+
.ena_o (cheriot_ena),
1075+
.error_o (cheriot_switch_error)
1076+
);
1077+
// For now, tie off all signals
1078+
assign unused_cheriot = ^{cheriot_ena, cheriot_switch_error};
1079+
1080+
end else begin : gen_no_cheriot_switch
1081+
assign cheriot_ena = prim_mubi_pkg::MuBi4False;
1082+
assign cheriot_switch_error = 1'b0;
1083+
assign unused_cheriot = ^{cheriot_ena, cheriot_switch_error};
1084+
end
1085+
10581086
logic unused_reg2hw;
10591087
assign unused_reg2hw = |reg2hw.rnd_data.q;
10601088

@@ -1145,7 +1173,8 @@ module ${module_instance_name}
11451173
assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable,
11461174
reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data,
11471175
reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err,
1148-
reg2hw_shadow.mcounteren_writable};
1176+
reg2hw_shadow.mcounteren_writable,
1177+
reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock};
11491178

11501179
/////////////////////////////////////////////////////////////////
11511180
// Shadow Core Data Address Translation Unit and TL-UL Adapter //

‎hw/ip_templates/rv_core_ibex/rv_core_ibex.core.tpl‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ filesets:
2020
- lowrisc:prim:mubi
2121
- lowrisc:tlul:adapter_host
2222
- lowrisc:ip:rv_core_ibex_pkg
23+
- lowrisc:ip:cheriot
2324
% if racl_support:
2425
- ${instance_vlnv("lowrisc:constants:top_racl_pkg")}
2526
% endif

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1079,6 +1079,40 @@
10791079
]
10801080
},
10811081

1082+
{ name: "CHERIOT_ENA",
1083+
desc: '''
1084+
Whether to enable (MuBi4True) CHERIoT mode or remain in ePMP mode (MuBi4False).
1085+
''',
1086+
swaccess: "wo",
1087+
hwaccess: "hro",
1088+
fields: [
1089+
{ bits: "3:0",
1090+
name: "VAL",
1091+
resval: "0x0"
1092+
desc: '''
1093+
'''
1094+
},
1095+
]
1096+
},
1097+
1098+
{ name: "CHERIOT_LOCK",
1099+
desc: '''
1100+
Locks the CHERIoT/ePMP mode.
1101+
If CHERIOT_ENA is set to MuBi4True, CHERIoT mode is enabled on write to this register.
1102+
''',
1103+
swaccess: "wo",
1104+
hwaccess: "hro",
1105+
hwext: "true",
1106+
hwqe: "true",
1107+
fields: [
1108+
{ bits: "3:0",
1109+
name: "VAL",
1110+
desc: '''
1111+
'''
1112+
},
1113+
]
1114+
},
1115+
10821116
{ name: "FPGA_INFO",
10831117
desc: '''
10841118
FPGA build timestamp info.

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/doc/registers.md‎

Lines changed: 310 additions & 273 deletions
Large diffs are not rendered by default.

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv‎

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,11 @@ module rv_core_ibex
239239
// core sleeping
240240
logic core_sleep;
241241

242+
// CHERIoT signals
243+
prim_mubi_pkg::mubi4_t cheriot_ena;
244+
logic cheriot_switch_error;
245+
logic unused_cheriot;
246+
242247
// The following intermediate signals are created to aid in simulations.
243248
//
244249
// If a parent port is connected directly to a port of sub-modules, the implicit wire connection
@@ -1030,6 +1035,29 @@ module rv_core_ibex
10301035
assign hw2reg.rnd_status.rnd_data_valid.d = rnd_valid_q;
10311036
assign hw2reg.rnd_status.rnd_data_fips.d = rnd_fips_q;
10321037

1038+
////////////////////
1039+
// CHERIoT switch
1040+
////////////////////
1041+
1042+
if (BaseIsa == ibex_pkg::BaseIsaRV32IorCHERIoT) begin : gen_cheriot_switch
1043+
cheriot_switch u_cheriot_switch (
1044+
.clk_i,
1045+
.rst_ni,
1046+
.ena_i (reg2hw.cheriot_ena.q),
1047+
.lock_i (reg2hw.cheriot_lock.q),
1048+
.lock_access_i(reg2hw.cheriot_lock.qe),
1049+
.ena_o (cheriot_ena),
1050+
.error_o (cheriot_switch_error)
1051+
);
1052+
// For now, tie off all signals
1053+
assign unused_cheriot = ^{cheriot_ena, cheriot_switch_error};
1054+
1055+
end else begin : gen_no_cheriot_switch
1056+
assign cheriot_ena = prim_mubi_pkg::MuBi4False;
1057+
assign cheriot_switch_error = 1'b0;
1058+
assign unused_cheriot = ^{cheriot_ena, cheriot_switch_error};
1059+
end
1060+
10331061
logic unused_reg2hw;
10341062
assign unused_reg2hw = |reg2hw.rnd_data.q;
10351063

@@ -1120,7 +1148,8 @@ module rv_core_ibex
11201148
assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable,
11211149
reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data,
11221150
reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err,
1123-
reg2hw_shadow.mcounteren_writable};
1151+
reg2hw_shadow.mcounteren_writable,
1152+
reg2hw_shadow.cheriot_ena, reg2hw_shadow.cheriot_lock};
11241153

11251154
/////////////////////////////////////////////////////////////////
11261155
// Shadow Core Data Address Translation Unit and TL-UL Adapter //

‎hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex_cfg_reg_top.sv‎

Lines changed: 87 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,9 @@ module rv_core_ibex_cfg_reg_top (
5757

5858
// also check for spurious write enables
5959
logic reg_we_err;
60-
logic [266:0] reg_we_check;
60+
logic [268:0] reg_we_check;
6161
prim_reg_we_check #(
62-
.OneHotWidth(267)
62+
.OneHotWidth(269)
6363
) u_prim_reg_we_check (
6464
.clk_i(clk_i),
6565
.rst_ni(rst_ni),
@@ -973,6 +973,10 @@ module rv_core_ibex_cfg_reg_top (
973973
logic rnd_status_re;
974974
logic rnd_status_rnd_data_valid_qs;
975975
logic rnd_status_rnd_data_fips_qs;
976+
logic cheriot_ena_we;
977+
logic [3:0] cheriot_ena_wd;
978+
logic cheriot_lock_we;
979+
logic [3:0] cheriot_lock_wd;
976980
logic fpga_info_re;
977981
logic [31:0] fpga_info_qs;
978982
logic mcounteren_writable_regwen_we;
@@ -11682,6 +11686,54 @@ module rv_core_ibex_cfg_reg_top (
1168211686
);
1168311687

1168411688

11689+
// R[cheriot_ena]: V(False)
11690+
prim_subreg #(
11691+
.DW (4),
11692+
.SwAccess(prim_subreg_pkg::SwAccessWO),
11693+
.RESVAL (4'h0),
11694+
.Mubi (1'b0)
11695+
) u_cheriot_ena (
11696+
.clk_i (clk_i),
11697+
.rst_ni (rst_ni),
11698+
11699+
// from register interface
11700+
.we (cheriot_ena_we),
11701+
.wd (cheriot_ena_wd),
11702+
11703+
// from internal hardware
11704+
.de (1'b0),
11705+
.d ('0),
11706+
11707+
// to internal hardware
11708+
.qe (),
11709+
.q (reg2hw.cheriot_ena.q),
11710+
.ds (),
11711+
11712+
// to register interface (read)
11713+
.qs ()
11714+
);
11715+
11716+
11717+
// R[cheriot_lock]: V(True)
11718+
logic cheriot_lock_qe;
11719+
logic [0:0] cheriot_lock_flds_we;
11720+
assign cheriot_lock_qe = &cheriot_lock_flds_we;
11721+
prim_subreg_ext #(
11722+
.DW (4)
11723+
) u_cheriot_lock (
11724+
.re (1'b0),
11725+
.we (cheriot_lock_we),
11726+
.wd (cheriot_lock_wd),
11727+
.d ('0),
11728+
.qre (),
11729+
.qe (cheriot_lock_flds_we[0]),
11730+
.q (reg2hw.cheriot_lock.q),
11731+
.ds (),
11732+
.qs ()
11733+
);
11734+
assign reg2hw.cheriot_lock.qe = cheriot_lock_qe;
11735+
11736+
1168511737
// R[fpga_info]: V(True)
1168611738
prim_subreg_ext #(
1168711739
.DW (32)
@@ -11758,7 +11810,7 @@ module rv_core_ibex_cfg_reg_top (
1175811810

1175911811

1176011812

11761-
logic [266:0] addr_hit;
11813+
logic [268:0] addr_hit;
1176211814
always_comb begin
1176311815
addr_hit[ 0] = (reg_addr == RV_CORE_IBEX_ALERT_TEST_OFFSET);
1176411816
addr_hit[ 1] = (reg_addr == RV_CORE_IBEX_SW_RECOV_ERR_OFFSET);
@@ -12024,9 +12076,11 @@ module rv_core_ibex_cfg_reg_top (
1202412076
addr_hit[261] = (reg_addr == RV_CORE_IBEX_ERR_STATUS_OFFSET);
1202512077
addr_hit[262] = (reg_addr == RV_CORE_IBEX_RND_DATA_OFFSET);
1202612078
addr_hit[263] = (reg_addr == RV_CORE_IBEX_RND_STATUS_OFFSET);
12027-
addr_hit[264] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET);
12028-
addr_hit[265] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET);
12029-
addr_hit[266] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET);
12079+
addr_hit[264] = (reg_addr == RV_CORE_IBEX_CHERIOT_ENA_OFFSET);
12080+
addr_hit[265] = (reg_addr == RV_CORE_IBEX_CHERIOT_LOCK_OFFSET);
12081+
addr_hit[266] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET);
12082+
addr_hit[267] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_REGWEN_OFFSET);
12083+
addr_hit[268] = (reg_addr == RV_CORE_IBEX_MCOUNTEREN_WRITABLE_OFFSET);
1203012084
end
1203112085

1203212086
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -12300,7 +12354,9 @@ module rv_core_ibex_cfg_reg_top (
1230012354
(addr_hit[263] & (|(RV_CORE_IBEX_CFG_PERMIT[263] & ~reg_be))) |
1230112355
(addr_hit[264] & (|(RV_CORE_IBEX_CFG_PERMIT[264] & ~reg_be))) |
1230212356
(addr_hit[265] & (|(RV_CORE_IBEX_CFG_PERMIT[265] & ~reg_be))) |
12303-
(addr_hit[266] & (|(RV_CORE_IBEX_CFG_PERMIT[266] & ~reg_be)))));
12357+
(addr_hit[266] & (|(RV_CORE_IBEX_CFG_PERMIT[266] & ~reg_be))) |
12358+
(addr_hit[267] & (|(RV_CORE_IBEX_CFG_PERMIT[267] & ~reg_be))) |
12359+
(addr_hit[268] & (|(RV_CORE_IBEX_CFG_PERMIT[268] & ~reg_be)))));
1230412360
end
1230512361

1230612362
// Generate write-enables
@@ -13108,11 +13164,17 @@ module rv_core_ibex_cfg_reg_top (
1310813164
assign err_status_recov_core_err_wd = reg_wdata[10];
1310913165
assign rnd_data_re = addr_hit[262] & reg_re & !reg_error;
1311013166
assign rnd_status_re = addr_hit[263] & reg_re & !reg_error;
13111-
assign fpga_info_re = addr_hit[264] & reg_re & !reg_error;
13112-
assign mcounteren_writable_regwen_we = addr_hit[265] & reg_we & !reg_error;
13167+
assign cheriot_ena_we = addr_hit[264] & reg_we & !reg_error;
13168+
13169+
assign cheriot_ena_wd = reg_wdata[3:0];
13170+
assign cheriot_lock_we = addr_hit[265] & reg_we & !reg_error;
13171+
13172+
assign cheriot_lock_wd = reg_wdata[3:0];
13173+
assign fpga_info_re = addr_hit[266] & reg_re & !reg_error;
13174+
assign mcounteren_writable_regwen_we = addr_hit[267] & reg_we & !reg_error;
1311313175

1311413176
assign mcounteren_writable_regwen_wd = reg_wdata[0];
13115-
assign mcounteren_writable_we = addr_hit[266] & reg_we & !reg_error;
13177+
assign mcounteren_writable_we = addr_hit[268] & reg_we & !reg_error;
1311613178

1311713179
assign mcounteren_writable_wd = reg_wdata[3:0];
1311813180

@@ -13382,9 +13444,11 @@ module rv_core_ibex_cfg_reg_top (
1338213444
reg_we_check[261] = err_status_we;
1338313445
reg_we_check[262] = 1'b0;
1338413446
reg_we_check[263] = 1'b0;
13385-
reg_we_check[264] = 1'b0;
13386-
reg_we_check[265] = mcounteren_writable_regwen_we;
13387-
reg_we_check[266] = mcounteren_writable_gated_we;
13447+
reg_we_check[264] = cheriot_ena_we;
13448+
reg_we_check[265] = cheriot_lock_we;
13449+
reg_we_check[266] = 1'b0;
13450+
reg_we_check[267] = mcounteren_writable_regwen_we;
13451+
reg_we_check[268] = mcounteren_writable_gated_we;
1338813452
end
1338913453

1339013454
// Read data return
@@ -14457,14 +14521,22 @@ module rv_core_ibex_cfg_reg_top (
1445714521
end
1445814522

1445914523
addr_hit[264]: begin
14460-
reg_rdata_next[31:0] = fpga_info_qs;
14524+
reg_rdata_next[3:0] = '0;
1446114525
end
1446214526

1446314527
addr_hit[265]: begin
14464-
reg_rdata_next[0] = mcounteren_writable_regwen_qs;
14528+
reg_rdata_next[3:0] = '0;
1446514529
end
1446614530

1446714531
addr_hit[266]: begin
14532+
reg_rdata_next[31:0] = fpga_info_qs;
14533+
end
14534+
14535+
addr_hit[267]: begin
14536+
reg_rdata_next[0] = mcounteren_writable_regwen_qs;
14537+
end
14538+
14539+
addr_hit[268]: begin
1446814540
reg_rdata_next[3:0] = mcounteren_writable_qs;
1446914541
end
1447014542

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