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WIP: Update bkdr loader and integrate into CW340
Signed-off-by: Thomas Benz <tbenz@lowrisc.org>
1 parent 3f242f5 commit da6072b

27 files changed

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‎hw/ip/BUILD‎

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@@ -17,6 +17,7 @@ filegroup(
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"//hw/ip/adc_ctrl:rtl_files",
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"//hw/ip/aes:rtl_files",
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"//hw/ip/aon_timer:rtl_files",
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"//hw/ip/bkdr_loader:rtl_files",
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"//hw/ip/csrng:rtl_files",
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"//hw/ip/dma:rtl_files",
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"//hw/ip/edn:rtl_files",

‎hw/ip/README.md‎

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| [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures |
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| [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock |
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| [`ascon`] | Ascon authenticated encryption and decryption engine |
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| [`bkdr_loader`] | Provides indirect programming to RAMs |
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| [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software |
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| [`dma`] | DMA Controller for the integrated OpenTitan. |
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| [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks |
@@ -40,6 +41,7 @@
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[`aes`]: ./aes/README.md
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[`aon_timer`]: ./aon_timer/README.md
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[`ascon`]: ./ascon/README.md
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[`bkdr_loader`]: ./bkdr_loader/README.md
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[`csrng`]: ./csrng/README.md
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[`dma`]: ./dma/README.md
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[`edn`]: ./edn/README.md

‎hw/ip/bkdr_loader/BUILD‎

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@@ -14,14 +14,14 @@ filegroup(
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"README.md",
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],
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) + [
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"//hw/ip/sram_ctrl/data:all_files",
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"//hw/ip/bkdr_loader/data:all_files",
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],
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)
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filegroup(
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name = "doc_files",
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srcs = glob([
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"**/*.md",
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"**/*.svg",
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]) + ["//hw/ip/sram_ctrl/data:doc_files"],
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)
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#filegroup(
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# name = "doc_files",
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# srcs = glob([
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# "**/*.md",
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# "**/*.svg",
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# ]) + ["//hw/ip/bkdr_loader/data:doc_files"],
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#)

‎hw/ip/bkdr_loader/README.md‎

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# SRAM Controller Technical Specification (UPDATE ME FOR BKDR_LOADER!)
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[`sram_ctrl/main`](https://reports.opentitan.org/hw/ip/sram_ctrl_main/dv/latest/report.html):
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/main/test.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/main/passing.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/main/functional.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/main/code.svg)
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[`sram_ctrl/ret`](https://reports.opentitan.org/hw/ip/sram_ctrl_ret/dv/latest/report.html):
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/ret/test.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/ret/passing.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/ret/functional.svg)
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![](https://dashboards.lowrisc.org/badges/dv/sram_ctrl/ret/code.svg)
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# Overview
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This document specifies the functionality of the SRAM memory controller.
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The SRAM controller is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../doc/contributing/hw/comportability/README.md).
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The SRAM controller contains the SRAM data and address scrambling device and provides CSRs for requesting the scrambling keys and triggering the hardware initialization feature.
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## Features
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- [Lightweight scrambling mechanism](../prim/doc/prim_ram_1p_scr.md#custom-substitution-permutation-network) based on the PRINCE cipher.
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- Key request logic for the lightweight memory and address scrambling device.
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- Alert sender and checking logic for detecting bus integrity failures.
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- LFSR-based memory initialization feature.
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- Access controls to allow / disallow code execution from SRAM.
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- Security hardening when integrity error has been detected.
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- Optional memory readback mode for detecting memory integrity errors.
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# FPGA Backdoor Loader IP

‎hw/ip/bkdr_loader/bkdr_loader.core‎

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- lowrisc:prim:all
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- lowrisc:ip:tlul
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files:
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- rtl/bkdr_loader.svh : {is_include_file : true}
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- rtl/bkdr_loader_reg_pkg.sv
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- rtl/bkdr_loader_regs_reg_top.sv
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- rtl/bkdr_loader_pkg.sv

‎hw/ip/bkdr_loader/data/BUILD‎

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srcs = glob(["**"]),
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)
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filegroup(
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name = "doc_files",
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srcs = glob(["*_testplan.hjson"]),
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)
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#filegroup(
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# name = "doc_files",
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# srcs = glob(["*_testplan.hjson"]),
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#)

‎hw/ip/bkdr_loader/data/bkdr_loader.hjson‎

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type: "int unsigned",
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default: "4",
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}
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{ name: "MaxIndexBitsDiv32",
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desc: "Max number of bits in the word index / word address, divided by 32",
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type: "int unsigned",
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default: "1",
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}
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]
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features: [
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////////////////////////
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// Ctrl / Status CSRs //
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////////////////////////
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{ name: "INFO",
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desc: "Information about this backdoor loader.",
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swaccess: "ro",
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hwaccess: "none",
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hwqe: "false",
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{ name: "Status",
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desc: "Status register",
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swaccess: "rc",
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hwaccess: "hwo",
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hwext: "true",
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hwqe: "true",
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fields: [
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{ bits: "2:0"
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name: "MAX_WORD_SIZE"
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{ bits: "0"
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name: "Error"
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swaccess: "ro",
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hwaccess: "hwo",
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desc: '''
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The maximum number of bits supported in a word, encoded as a power of 2.
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Whether an error happened on the last access. Clear on read.
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''',
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resval: "7" // Need templating to derive this value
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}
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{ bits: "13:8"
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name: "MAX_INDEX_BITS"
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{ bits: "15:8"
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name: "IDX"
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desc: '''
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The maximum number of bits supported in a word index (word "address").
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Index of last memory access.
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''',
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resval: "32"
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}
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]
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}
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{ name: "OP",
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desc: "Operation control and status",
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swaccess: "rw",
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{ name: "Control",
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desc: "Control register",
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swaccess: "wo",
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hwaccess: "hro",
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hwqe: "true",
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fields: [
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{ bits: "0"
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name: "ISSUE_WRITE"
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swaccess: "rw1s",
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hwaccess: "hrw",
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name: "DONE"
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swaccess: "wo",
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hwaccess: "hro",
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desc: '''
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Issue a write transaction with the current state of the other CSRs.
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Switch to mission mode.
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''',
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},
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{ bits: "1"
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name: "WRITE_ENA"
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swaccess: "wo",
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hwaccess: "hro",
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desc: '''
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Whether to write or read.
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''',
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}
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{ bits: "15:8"
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name: "MEM_SELECT"
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]
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}
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{ name: "FPGA_INFO",
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desc: "FPGA info register",
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swaccess: "ro",
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hwaccess: "hwo",
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hwext: "true",
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fields: [
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{ bits: "31:0"
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name: "VAL"
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swaccess: "ro",
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hwaccess: "hwo",
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desc: '''
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Binary-encoded memory selector for issuing an operation.
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FGPA information.
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''',
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}
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]
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}
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{ skipto: "0x40" }
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{ multireg: {
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name: "DATA",
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desc: "Value to be written to the RAM",
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name: "READ_DATA",
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desc: "Value to be read from the RAM",
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count: "MaxWordWidthDiv32",
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cname: "VAL",
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swaccess: "rw",
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hwaccess: "hro",
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swaccess: "ro",
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hwaccess: "hwo",
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hwext: "true",
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fields: [
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{ bits: "31:0",
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name: "VAL",
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},
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]
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} },
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{ skipto: "0x80" }
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{ multireg: {
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name: "INDEX",
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desc: "Index of the word to be written",
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count: "MaxIndexBitsDiv32",
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name: "WRITE_DATA",
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desc: "Value to be written to the RAM",
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count: "MaxWordWidthDiv32",
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cname: "VAL",
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swaccess: "rw",
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swaccess: "wo",
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hwaccess: "hro",
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hwqe: "true",
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fields: [
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{ bits: "31:0",
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name: "VAL",
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},
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]
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} },
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{ skipto: "0x120" }
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{ name: "ADDRESS",
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desc: "Byte address of the word to be accessed",
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swaccess: "wo",
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hwaccess: "hro",
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hwqe: "true",
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fields: [
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{ bits: "31:0",
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name: "VAL",
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desc: '''
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''',
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resval: 0x0
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},
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]
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},
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],
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}
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}

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