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[cov] Select some FPGA tests for CI setup validation
This commit adds the `coverage` tag to the `fpga_params` of several smoke and functional tests. This allows these tests to be automatically selected by the CI pipeline to validate the coverage collection setup on FPGA targets. Change-Id: I86d8e28ee885cf683d961dd5e1eaf44a100e8ad2 Signed-off-by: Yi-Hsuan Deng <yhdeng@google.com>
1 parent a103b45 commit ef304ce

6 files changed

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sw/device/lib/crypto/drivers/BUILD

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@@ -179,6 +179,7 @@ opentitan_test(
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name = "entropy_test",
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srcs = ["entropy_test.c"],
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exec_env = EARLGREY_TEST_ENVS,
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fpga = fpga_params(tags = ["coverage"]),
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verilator = verilator_params(
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timeout = "long",
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tags = ["broken"], # TODO #16672 test broken by icache

sw/device/silicon_creator/lib/BUILD

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@@ -66,6 +66,7 @@ cc_test(
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opentitan_test(
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name = "boot_data_functest",
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srcs = ["boot_data_functest.c"],
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fpga = fpga_params(tags = ["coverage"]),
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exec_env = dicts.add(
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dicts.omit(
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EARLGREY_TEST_ENVS,

sw/device/silicon_creator/lib/cert/BUILD

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@@ -9,6 +9,7 @@ load(
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load(
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"//rules/opentitan:defs.bzl",
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"opentitan_test",
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"fpga_params",
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)
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package(default_visibility = ["//visibility:public"])
@@ -215,6 +216,7 @@ opentitan_test(
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"//hw/top_earlgrey:fpga_cw310_rom_ext": None,
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"//hw/top_earlgrey:sim_qemu_rom_ext": None,
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},
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fpga = fpga_params(tags = ["coverage"]),
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deps = [
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":dice_cwt",
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"//hw/top_earlgrey/ip_autogen/flash_ctrl:flash_ctrl_c_regs",

sw/device/silicon_creator/rom/e2e/clkmgr/BUILD

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@@ -52,6 +52,7 @@ JITTER_TESTCASES = [
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"name": "enabled",
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"fpga": fpga_params(
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otp = ":otp_img_jitter_enabled",
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tags = ["coverage"],
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),
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"defines": ["TEST_JITTER_ENABLED"],
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},

sw/device/silicon_creator/rom_ext/e2e/boot_svc/BUILD

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@@ -286,6 +286,7 @@ opentitan_test(
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assemble = "{rom_ext}@{rom_ext_slot_a} {firmware}@{owner_slot_a} {firmware}@{owner_slot_b}",
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exit_failure = "BFV:.*|PASS|FAIL",
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exit_success = "FinalBootLog: 3:AAA\r\n",
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tags = ["coverage"],
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),
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linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_owner_slot_virtual",
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qemu = qemu_params(

sw/device/tests/BUILD

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@@ -4568,6 +4568,7 @@ opentitan_test(
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opentitan_test(
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name = "uart_smoketest",
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srcs = ["uart_smoketest.c"],
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fpga = fpga_params(tags = ["coverage"]),
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exec_env = dicts.add(
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EARLGREY_TEST_ENVS,
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EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,

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