[reggen, systemrdl] Create udp for multibit regwen

One example is fund in mbx.hjson

Author: engdoreis

util/reggen/systemrdl/udp.rdl

@@ -70,6 +70,14 @@ enum MultiBitBool32 {
   False = 0x69696969;
 };
 
+/*
+ * The same as swwe, but supports multibit references.
+ */
+property mubi_swwe {
+  type = ref;
+  component = reg|field;
+};
+
 /**
  * true if hardware uses `re` signal, which is latched signal of software read pulse.
  * The standard SystemRDL property `swacc` cannot be used here because `swacc = hwre | swmod`.

util/reggen/systemrdl_exporter.py

@@ -102,19 +102,22 @@ def _get_mubi_name(self) -> str:
         alignment = 4
         aligned_width = (self.inner.bits.width() + alignment - 1) & ~(alignment - 1)
         return f"MultiBitBool{aligned_width}"
-    
-    def assign_swwe(self, field: systemrdl.component.Field, regwen: str) -> None:
+
+    def assign_swwe(self, field: systemrdl.component.Component, regwen: str | None) -> None:
         if swwe := bool(regwen):
+            property_name = "swwe"
             if reg_ref := self.root.get_child_by_name(str(regwen)):
+                wen_field = reg_ref.children[0]
                 # This is a workaround and shall be fixed when the Issue
                 # https://github.com/SystemRDL/systemrdl-compiler/issues/183 is fixed.
                 swwe = InstRef(
                     self.importer.compiler.env,
                     self.root,
-                    [(str(regwen), [], None), (str(reg_ref.children[0].inst_name), [], None)],
+                    [(str(regwen), [], None), (str(wen_field.inst_name), [], None)],
                 )  # type: ignore
-            self.importer.assign_property(field, "swwe", swwe)
-
+                if wen_field.width > 1:  # type: ignore
+                    property_name = "mubi_swwe"
+            self.importer.assign_property(field, property_name, swwe)
 
     def export(
         self, strip_suffix: bool = False, regwen: str | None = None
@@ -162,6 +165,7 @@ def post_process(self, regwen: str) -> None:
         if field := self.parent.get_child_by_name(self.inner.name.upper()):
             self.assign_swwe(field, regwen)
 
+
 @dataclass
 class Window2Systemrdl:
     inner: Window