Description

Currently the prim_fifo_async_simple ( hw/ip/prim/rtl/prim_fifo_async_simple.sv ) used in the rv_dm and lc_ctrl modules has a tied off flip flop to control the reset behaviour of the handshake signal wready_o.

The intent is ensure to the wready_o signal is low when the module is reset. This prevents the possibility of the module accepting and loosing data when in reset.

Functional this works as intended, however this would result a DFT controllability violation, which would require fixing during scan insertion.

This can be fixed in the RTL by restructuring the logic to remove the tie off, avoiding the need to fix it latter in the flow.