[rtl,fpga] Implement JTAG-based memory preload backdoor

[thommythomaso]

Bkdr Loader

Addresses #28188.
Continues work of @a-will (fpga-bkdr-load).

Overview

This PR introduces a FPGA-only memory backdoor IP called bkdr loader to OpenTitan. We currently still rely on bitstream splicing in CI until the appropriate SW and infrastructure changes are merged. The bkdr loader HW is not fully functional yet: the ROM target cannot be loaded/read.

TODOs:

• Show on the FPGA the bkdr loader works openocd.tcl
• Remove FPGA info register from rv_core_ibex wrapper
• Reduce DMI address width from 32 to 9
• Update README and doc
• Add bkdr IP to hw/Makefile

[gautschimi]

Looks good in general, just a few comments.

Is the idea to merge this as is and then revert the last commit? Or will we wait for the changes and merge this without the last commit?

[thommythomaso]

Looks good in general, just a few comments.

Is the idea to merge this as is and then revert the last commit? Or will we wait for the changes and merge this without the last commit?

I currently would opt to squash the last three commits together cleanly merging the HW. But then we loose some of the work required to get the IP to run in the end.

[thommythomaso]

Looks good in general, just a few comments.

Is the idea to merge this as is and then revert the last commit? Or will we wait for the changes and merge this without the last commit?

Thanks @gautschimi for reviewing the bkdr_loader.

[vogelpi]

CHANGE AUTHORIZED: hw/ip/prim_xilinx/rtl/prim_ram_1p.sv
CHANGE AUTHORIZED: hw/ip/prim_xilinx/rtl/prim_rom.sv
CHANGE AUTHORIZED: hw/ip/prim_xilinx/rtl/prim_xilinx_rom.sv
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw340.sv

FPGA-only changes to implement backdoor memory loading

[andreaskurth]

And I'm wondering which commits you're planning to squash, so that the repo remains functional commit-by-commit after this has been merged, @thommythomaso?

I will squash it before marking it as ready to be merged.

All commits?

Commits 2-4 only introduced the changes required to remove the FPGA_INFO register in Ibex. This change has to be done once the SW and infrastructure is ready. I dropped all commits regarding the removal of the FPGA INFO register and merged the patches required to run the CI into the first commit. I still have the non-squashed state on my private fork for later use.

OK great, thanks