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[rv_core_ibex] Add u-mode performance counters and mcounteren #30135

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Merged
nasahlpa merged 3 commits into from
Jun 17, 2026
Merged

[rv_core_ibex] Add u-mode performance counters and mcounteren #30135

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e36d3a1
[rv_core_ibex] Add `mcounteren_writable` register
SamuelRiedel May 29, 2026
0d45447
Update lowrisc_ibex to lowRISC/ibex@aae4809a
SamuelRiedel Jun 11, 2026
160e316
[sw] Add mcounteren_writable test
SamuelRiedel May 18, 2026
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41 changes: 41 additions & 0 deletions hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -1124,6 +1124,47 @@
]
},

{ name: "MCOUNTEREN_WRITABLE_REGWEN",

@nasahlpa nasahlpa Jun 17, 2026

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As discussed offline, OK for me to have this as a single-bit value and not a mubi. To change the MCOUNTEREN value below, an attacker would need to fault it to be unlocked and also have SW access to write to it.

desc: "Register write-enable for !!MCOUNTEREN_WRITABLE.",
swaccess: "rw0c",
hwaccess: "none",
fields: [
{ bits: "0",
name: "EN",
resval: "1",
desc: "Write enable for !!MCOUNTEREN_WRITABLE. Once set to 0, it can no longer be configured to 1.",
enum: [
{ value: "0",
name: "locked",
desc: "MCOUNTEREN_WRITABLE can no longer be configured until next reset."
},
{ value: "1",
name: "enabled",
desc: "MCOUNTEREN_WRITABLE can still be configured."
},
]
},
],
},

{ name: "MCOUNTEREN_WRITABLE",
desc: "Controls whether Ibex mcounteren CSR is writable by software.",
swaccess: "rw",
hwaccess: "hro",
regwen: "MCOUNTEREN_WRITABLE_REGWEN",
fields: [
{ bits: "3:0",
mubi: true,
name: "EN",
resval: true,
desc: '''
When set to kMultiBitBool4True, the mcounteren CSR is writable by software.
Drives the mcounteren_writable_i input on ibex_top.
'''
},
],
},

// dv simulation window
{ window: {
name: "DV_SIM_WINDOW",
Expand Down
44 changes: 30 additions & 14 deletions hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,8 @@ module ${module_instance_name}
logic [ 3:0] rvfi_mem_wmask;
logic [31:0] rvfi_mem_rdata;
logic [31:0] rvfi_mem_wdata;
logic rvfi_ext_expanded_insn_valid;
logic [15:0] rvfi_ext_expanded_insn;
`endif

import tlul_pkg::tl_h2d_t;
Expand Down Expand Up @@ -433,6 +435,13 @@ module ${module_instance_name}
lc_ctrl_pkg::lc_tx_and_hi(lc_cpu_en[0],
pwrmgr_cpu_en[0]));

prim_mubi_pkg::mubi4_t mcounteren_writable_mubi4;
ibex_pkg::ibex_mubi_t mcounteren_writable_ibex;
assign mcounteren_writable_mubi4 = prim_mubi_pkg::mubi4_t'(reg2hw.mcounteren_writable.q);
// Convert the mubi4 to ibex_mubi. They are both four bit, but with different encodings.
assign mcounteren_writable_ibex = mcounteren_writable_mubi4 == prim_mubi_pkg::MuBi4True ?
ibex_pkg::IbexMuBiOn : ibex_pkg::IbexMuBiOff;

ibex_pkg::crash_dump_t crash_dump;
ibex_top #(
.PMPEnable ( PMPEnable ),
Expand Down Expand Up @@ -560,21 +569,25 @@ module ${module_instance_name}
.rvfi_mem_rdata,
.rvfi_mem_wdata,
// Unused ports from the RVFI interface
.rvfi_ext_pre_mip (),
.rvfi_ext_post_mip (),
.rvfi_ext_nmi (),
.rvfi_ext_nmi_int (),
.rvfi_ext_debug_req (),
.rvfi_ext_debug_mode (),
.rvfi_ext_rf_wr_suppress (),
.rvfi_ext_mcycle (),
.rvfi_ext_mhpmcounters (),
.rvfi_ext_mhpmcountersh (),
.rvfi_ext_ic_scr_key_valid(),
.rvfi_ext_irq_valid (),
.rvfi_ext_pre_mip (),
.rvfi_ext_post_mip (),
.rvfi_ext_nmi (),
.rvfi_ext_nmi_int (),
.rvfi_ext_debug_req (),
.rvfi_ext_debug_mode (),
.rvfi_ext_rf_wr_suppress (),
.rvfi_ext_mcycle (),
.rvfi_ext_mhpmcounters (),
.rvfi_ext_mhpmcountersh (),
.rvfi_ext_ic_scr_key_valid (),
.rvfi_ext_irq_valid (),
.rvfi_ext_expanded_insn_valid(),
.rvfi_ext_expanded_insn (),
.rvfi_ext_expanded_insn_last (),
`endif
// SEC_CM: FETCH.CTRL.LC_GATED
.fetch_enable_i (fetch_enable),
.mcounteren_writable_i (mcounteren_writable_ibex),
.alert_minor_o (alert_minor),
.alert_major_internal_o (alert_major_internal),
.alert_major_bus_o (alert_major_bus),
Expand Down Expand Up @@ -827,7 +840,9 @@ module ${module_instance_name}
.rvfi_mem_rmask,
.rvfi_mem_wmask,
.rvfi_mem_rdata,
.rvfi_mem_wdata
.rvfi_mem_wdata,
.rvfi_ext_expanded_insn_valid,
.rvfi_ext_expanded_insn
Comment thread
marnovandermaas marked this conversation as resolved.
);
`endif

Expand Down Expand Up @@ -1111,7 +1126,8 @@ module ${module_instance_name}

assign unused_reg2hw_shadow = ^{reg2hw_shadow.alert_test, reg2hw_shadow.nmi_enable,
reg2hw_shadow.nmi_state, reg2hw_shadow.rnd_data,
reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err};
reg2hw_shadow.sw_fatal_err, reg2hw_shadow.sw_recov_err,
reg2hw_shadow.mcounteren_writable};

/////////////////////////////////////////////////////////////////
// Shadow Core Data Address Translation Unit and TL-UL Adapter //
Expand Down
41 changes: 41 additions & 0 deletions hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -1098,6 +1098,47 @@
]
},

{ name: "MCOUNTEREN_WRITABLE_REGWEN",
desc: "Register write-enable for !!MCOUNTEREN_WRITABLE.",
swaccess: "rw0c",
hwaccess: "none",
fields: [
{ bits: "0",
name: "EN",
resval: "1",
desc: "Write enable for !!MCOUNTEREN_WRITABLE. Once set to 0, it can no longer be configured to 1.",
enum: [
{ value: "0",
name: "locked",
desc: "MCOUNTEREN_WRITABLE can no longer be configured until next reset."
},
{ value: "1",
name: "enabled",
desc: "MCOUNTEREN_WRITABLE can still be configured."
},
]
},
],
},

{ name: "MCOUNTEREN_WRITABLE",
desc: "Controls whether Ibex mcounteren CSR is writable by software.",
swaccess: "rw",
hwaccess: "hro",
regwen: "MCOUNTEREN_WRITABLE_REGWEN",
fields: [
{ bits: "3:0",
mubi: true,
name: "EN",
resval: true,
desc: '''
When set to kMultiBitBool4True, the mcounteren CSR is writable by software.
Drives the mcounteren_writable_i input on ibex_top.
'''
},
],
},

// dv simulation window
{ window: {
name: "DV_SIM_WINDOW",
Expand Down
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