[cheriot,rtl] Add and integrate CHERIoT switch

hw/ip/BUILD

@@ -18,6 +18,7 @@ filegroup(
         "//hw/ip/aes:rtl_files",
         "//hw/ip/aon_timer:rtl_files",
         "//hw/ip/bkdr_loader:rtl_files",
+        "//hw/ip/cheriot:rtl_files",
         "//hw/ip/csrng:rtl_files",
         "//hw/ip/dma:rtl_files",
         "//hw/ip/edn:rtl_files",

hw/ip/README.md

@@ -9,6 +9,7 @@
 | [`aon_timer`]    | Wakeup and watchdog timers running on a low-power, always-on clock                                                                |
 | [`ascon`]        | Ascon authenticated encryption and decryption engine                                                                              |
 | [`bkdr_loader`]  | Provides FPGA-only indirect programming to RAMs                                                                                   |
+| [`cheriot`]      | CHERIoT-aware memory subsystem                                                                                                    |
 | [`csrng`]        | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software          |
 | [`dma`]          | DMA Controller for the integrated OpenTitan.                                                                                      |
 | [`edn`]          | Distributes random numbers produced by CSRNG to hardware blocks                                                                   |
@@ -44,6 +45,7 @@
 [`aon_timer`]: ./aon_timer/README.md
 [`ascon`]: ./ascon/README.md
 [`bkdr_loader`]: ./bkdr_loader/README.md
+[`cheriot`]: ./cheriot/README.md
 [`csrng`]: ./csrng/README.md
 [`dma`]: ./dma/README.md
 [`edn`]: ./edn/README.md

hw/ip/cheriot/BUILD

@@ -0,0 +1,30 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "rtl_files",
+    srcs = glob(
+        ["**"],
+        exclude = [
+            "dv/**",
+            "doc/**",
+            "README.md",
+        ],
+    ) + [
+        "//hw/ip/cheriot/data:all_files",
+    ],
+)
+
+filegroup(
+    name = "doc_files",
+    srcs = glob(
+        [
+            "**/*.md",
+            "**/*.svg",
+        ],
+        allow_empty = True,
+    ) + ["//hw/ip/cheriot/data:doc_files"],
+)

hw/ip/cheriot/README.md

@@ -0,0 +1 @@
+# CHERIoT

hw/ip/cheriot/cheriot.core

@@ -0,0 +1,26 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:cheriot:0.1"
+description: "CHERIoT IPs"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:all
+      - lowrisc:ip:tlul
+      - pulp-platform:common_cells:common_cells
+    files:
+      - rtl/cheriot_pkg.sv
+      - rtl/cheriot_switch.sv
+      - rtl/cheriot_rmw_filter.sv
+      - rtl/cheriot_tag_filter.sv
+      - rtl/cheriot_access_check.sv
+      - rtl/cheriot.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl

hw/ip/cheriot/data/BUILD

@@ -0,0 +1,18 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)
+
+filegroup(
+    name = "doc_files",
+    srcs = glob(
+        ["*_testplan.hjson"],
+        allow_empty = True,
+    ),
+)

hw/ip/cheriot/data/cheriot.hjson

@@ -0,0 +1,166 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name:               "cheriot",
+  human_name:         "CHERIoT Memory Subsystem",
+  one_line_desc:      "CHERIoT-aware memory subsystem",
+  one_paragraph_desc: '''
+    The CHERIoT memory subsystem sits between a CHERIoT-capable Ibex core and the system
+    interconnect.  It enforces capability tag semantics on data-memory accesses, transparently
+    remapping capability accesses and revocation bitmap reads into a dedicated meta SRAM.
+  '''
+  // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool.
+  cip_id:             "47",
+  version:            "1.0.0",
+  life_stage:         "L1",
+  design_stage:       "D1",
+  verification_stage: "V0",
+
+  clocking: [
+    {clock: "clk_i", reset: "rst_ni", primary: true}
+  ],
+
+  bus_interfaces: [
+    {protocol: "tlul", direction: "device", name: "revbm"},
+    {protocol: "tlul", direction: "host", name: "cored"}
+  ],
+
+  ///////////////////////////
+  // Interrupts and Alerts //
+  ///////////////////////////
+
+  alert_list: [
+  ],
+
+  ////////////////
+  // Parameters //
+  ////////////////
+
+  param_list: [
+
+    /////////////////////
+    // Address map     //
+    /////////////////////
+
+    { name:    "MainSramBaseAddr",
+      desc:    "Base address of the main SRAM region (inclusive)",
+      type:    "logic [top_pkg::TL_AW-1:0]",
+      default: "32'h1000_0000",
+      local:   "false",
+      expose:  "true"
+    },
+    { name:    "MainSramTopAddr",
+      desc:    "Top address of the main SRAM region (exclusive).",
+      type:    "logic [top_pkg::TL_AW-1:0]",
+      default: "32'h1002_0000",
+      local:   "false",
+      expose:  "true"
+    },
+    { name:    "NvmBaseAddr",
+      desc:    "Base address of the NVM region (inclusive).",
+      type:    "logic [top_pkg::TL_AW-1:0]",
+      default: "32'h2000_0000",
+      local:   "false",
+      expose:  "true"
+    },
+    { name:    "NvmTopAddr",
+      desc:    "Top address of the NVM region (exclusive).",
+      type:    "logic [top_pkg::TL_AW-1:0]",
+      default: "32'h2020_0000",
+      local:   "false",
+      expose:  "true"
+    },
+    { name:    "MetaSramBaseAddr",
+      desc:    '''
+               Base address of the CHERIoT meta SRAM region.
+               ''',
+      type:    "logic [top_pkg::TL_AW-1:0]",
+      default: "32'h0000_0000",
+      local:   "false",
+      expose:  "true"
+    },
+  ],
+
+  //////////////
+  // Features //
+  //////////////
+
+  features: [
+  ],
+
+  /////////////////////////////
+  // Intermodule Connections //
+  /////////////////////////////
+
+  inter_signal_list: [
+    // CHERIoT mode enable
+    { struct:  "mubi4",
+      type:    "uni",
+      name:    "cheriot_ena",
+      act:     "rcv",
+      package: "prim_mubi_pkg",
+      default: "prim_mubi_pkg::MuBi4False",
+      desc:    "CHERIoT mode enable."
+    },
+    // Data TL-UL interface from the core
+    { struct:  "tl",
+      type:    "req_rsp",
+      name:    "cored_tl_d",
+      act:     "rsp",
+      package: "tlul_pkg",
+      desc:    "Data port from the core."
+    },
+    // Capability tag sideband - write direction (from core to subsystem)
+    { struct:  "logic",
+      type:    "uni",
+      name:    "cored_tag_h2d",
+      act:     "rcv",
+      width:   "1",
+      package: "",
+      default: "1'b0",
+      desc:    "CHERIoT capability tag carried with the A-channel of cored_h."
+    },
+    // Capability tag sideband - read response direction (from subsystem to core)
+    { struct:  "logic",
+      type:    "uni",
+      name:    "cored_tag_d2h",
+      act:     "req",
+      width:   "1",
+      package: "",
+      default: "1'b0",
+      desc:    "Capability tag returned on the D-channel of cored_h."
+    },
+    // TRVK revocation bitmap TL-UL host port
+    { struct:  "tl",
+      type:    "req_rsp",
+      name:    "corerevbm_tl",
+      act:     "rsp",
+      package: "tlul_pkg",
+      desc:    "TRVK (tag revocation) revocation bitmap port from the core."
+    },
+    // Meta SRAM host TL-UL port (to external sram_ctrl RAM interface)
+    { struct:  "tl",
+      type:    "req_rsp",
+      name:    "meta_sram_tl",
+      act:     "req",
+      package: "tlul_pkg",
+      desc:    "Host TL-UL port to the external meta SRAM controller's RAM interface."
+    },
+  ],
+
+  /////////////////////
+  // Countermeasures //
+  /////////////////////
+
+  countermeasures: [
+  ],
+
+  ///////////
+  // Memory //
+  ///////////
+
+  memory: {
+    revbm: {}
+  }
+}

hw/ip/cheriot/defs.bzl

@@ -0,0 +1,9 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+load("//rules/opentitan:hw.bzl", "opentitan_ip")
+
+CHERIOT = opentitan_ip(
+    name = "cheriot",
+    hjson = "//hw/ip/cheriot/data:cheriot.hjson",
+)