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[top,all] Drop _aon suffix from IP names #30563

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5e74af0
[top,rtl] Generalize SRAM configuration interfaces
thommythomaso Jun 25, 2026
c355db1
[top] Rename toplevel HDL modules of default power domain
glaserf Jun 12, 2026
e325fc1
[topgen/ralgen] Take power domain of IPs into account
glaserf Jun 23, 2026
ce70e49
[util/topgen] Allow renamed feedthroughs in port maps
glaserf Jun 22, 2026
5643f8c
[earlgrey,topgen] Add new hierarchy level which wraps all "core" logic
glaserf Jun 14, 2026
3ec2704
AUTOGEN [earlgrey] Re(generate) top_earlgrey and chip_earlgrey for al…
glaserf Jun 14, 2026
31bcace
[englishbreakfast] Add new hierarchy level which wraps all "core" logic
glaserf Jun 22, 2026
258fe7e
AUTOGEN [englishbreakfast] Generate all-logic top_englishbreakfast le…
glaserf Jun 22, 2026
78b7dc5
[darjeeling] Add new hierarchy level which wraps all "core" logic
glaserf Jul 7, 2026
a59eb3b
AUTOGEN [darjeeling] Generate all-logic top_darjeeling level of hiera…
glaserf Jun 25, 2026
a7991ba
[earlgrey/fpga] Update constraints for additional toplevel hierarchy
glaserf Jun 23, 2026
cd82cdf
[earlgrey/syn] Update paths in syn flow for new top-level wrapper
glaserf Jun 25, 2026
484334f
[earlgrey/dv] Update env and tb to take new hierarchy into account
glaserf Jun 15, 2026
6c91825
[darjeeling/dv] Update env and tb to take new hierarchy into account
glaserf Jun 25, 2026
1e49381
[lint] Update AscentLint waiver files for new hierarchy
glaserf Jul 7, 2026
1e03edc
[dv/conn] Update CSV paths for new top-level wrapper hierarchy
glaserf Jun 25, 2026
b71b39b
[dv/cov] Update coverage cfg paths for new top-level wrapper
glaserf Jun 25, 2026
ad8a1ae
[earlgrey,ip_templates] Drop _aon suffix from all affected IPs
glaserf Jun 29, 2026
96897b6
[englishbreakfast] Drop _aon IP suffix from all affected IPs
glaserf Jul 1, 2026
5c65249
[darjeeling] Drop _aon IP suffix from all affected IPs
glaserf Jul 1, 2026
fb72ac2
[earlgrey/all] Regenerate top with dropped _aon IP suffix
glaserf Jun 30, 2026
881f18b
[englishbreakfast/all] Regenerate top with dropped _aon IP suffix
glaserf Jul 1, 2026
a2a3ced
[darjeeling/all] Regenerate top with dropped _aon suffix
glaserf Jul 1, 2026
0bb211b
[earlgrey/dv] Update env and tb to account for dropped _aon suffix
glaserf Jun 15, 2026
a440231
[darjeeling/dv] Update env and tb to account for dropped _aon suffix
glaserf Jul 1, 2026
1afe360
[fpga] Update constraints to account for dropped _aon suffix
glaserf Jun 23, 2026
9650a71
[earlgrey/syn] Update paths in syn flow to account for dropped _aon s…
glaserf Jun 25, 2026
7a4b202
[earlgrey,darjeeling] Drop _aon suffixes from testplans
glaserf Jun 30, 2026
a21e0f1
[lint] Update AscentLint waiver files to account for dropped _aon suffix
glaserf Jun 25, 2026
cc930c8
[dv/conn] Update CSV paths to account for dropped _aon suffix
glaserf Jun 25, 2026
54a7677
[dv/cov] Update coverage cfg paths to account for dropped _aon suffix
glaserf Jun 25, 2026
52718bc
[sw] Adapt all references to previously _aon/Aon suffixed objects
glaserf Jun 30, 2026
3fb950a
[sw/host] Drop aon IP suffix
glaserf Jul 1, 2026
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4 changes: 2 additions & 2 deletions hw/dv/sv/sim_sram/sim_sram.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -98,8 +98,8 @@ module sim_sram #(
) u_sram (
.clk_i,
.rst_ni,
.cfg_i ('0),
.cfg_rsp_o (),
.cfg_i (prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT),
.cfg_o (),
.req_i (sram_req),
.write_i (sram_we),
.addr_i (sram_addr),
Expand Down
4 changes: 2 additions & 2 deletions hw/formal/tools/jaspergold/conn.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,9 @@ if {$env(DUT_TOP) == "chip_earlgrey_asic"} {
stopat -env POR_N
reset -expr {POR_N}
# Add this assumption to avoid a false functional loop.
assume -env {top_earlgrey.u_pinmux_aon.reg2hw.mio_pad_sleep_status == '1}
assume -env {top_earlgrey.u_pinmux.reg2hw.mio_pad_sleep_status == '1}
# Add this assumption to avoid signal inversion in the pad wrappers.
assume -env {top_earlgrey.u_pinmux_aon.dio_pad_attr_q == '0}
assume -env {top_earlgrey.u_pinmux.dio_pad_attr_q == '0}

# run additional assume commands for foundry implementation if needed
if {[info exists ::env(PARTNER_TCL)]} {
Expand Down
48 changes: 24 additions & 24 deletions hw/ip/bkdr_loader/rtl/bkdr_loader.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -6,31 +6,31 @@
`define BKDR_LOADER_SVH

`define BKDR_LOADER_CONNECT_REQS \
assign top_earlgrey_pd_aon.u_sram_ctrl_ret_aon.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrAon]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I2]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I1]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I0]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I2]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I1]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I0]; \
assign top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0]; \
assign top_earlgrey.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSram]; \
assign top_earlgrey.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRom]; \
assign top_earlgrey.u_otp_macro.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrOtp];
assign top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrAon]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I2]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I1]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1I0]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB1]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I2]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I1]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0I0]; \
assign top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrFlashB0]; \
assign top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrSram]; \
assign top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrRom]; \
assign top_earlgrey.earlgrey_pd_main.u_otp_macro.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_req = bkdr_req[bkdr_loader_pkg::BkdrOtp];

`define BKDR_LOADER_CONNECT_RSPS \
assign bkdr_rsp[bkdr_loader_pkg::BkdrAon] = top_earlgrey_pd_aon.u_sram_ctrl_ret_aon.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I2] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I1] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I0] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I2] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I1] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I0] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0] = top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrSram] = top_earlgrey.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrRom] = top_earlgrey.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrOtp] = top_earlgrey.u_otp_macro.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp;
assign bkdr_rsp[bkdr_loader_pkg::BkdrAon] = top_earlgrey.earlgrey_pd_aon.u_sram_ctrl_ret.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I2] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1I0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I2] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I1] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0I0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrFlashB0] = top_earlgrey.earlgrey_pd_main.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrSram] = top_earlgrey.earlgrey_pd_main.u_sram_ctrl_main.u_prim_ram_1p_scr.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrRom] = top_earlgrey.earlgrey_pd_main.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.bkdr_rsp; \
assign bkdr_rsp[bkdr_loader_pkg::BkdrOtp] = top_earlgrey.earlgrey_pd_main.u_otp_macro.u_prim_ram_1p_adv.gen_ram_inst[0].u_mem.bkdr_rsp;

`endif
10 changes: 2 additions & 8 deletions hw/ip/i2c/data/i2c.hjson
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Expand Up @@ -111,15 +111,9 @@
// RAM configuration
{ struct: "ram_1p_cfg"
package: "prim_ram_1p_pkg"
type: "uni"
type: "req_rsp"
name: "ram_cfg"
act: "rcv"
}
{ struct: "ram_1p_cfg_rsp"
package: "prim_ram_1p_pkg"
type: "uni"
name: "ram_cfg_rsp"
act: "req"
act: "rsp"
}
{ struct: "logic"
type: "uni"
Expand Down
15 changes: 7 additions & 8 deletions hw/ip/i2c/doc/interfaces.md
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Expand Up @@ -16,14 +16,13 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:--------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:--------------|:------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | req_rsp | rsp | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

Expand Down
4 changes: 2 additions & 2 deletions hw/ip/i2c/dv/tb/tb.sv
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Expand Up @@ -79,8 +79,8 @@ module tb;
i2c dut (
.clk_i (clk ),
.rst_ni (rst_n ),
.ram_cfg_i (prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT),
.ram_cfg_rsp_o ( ),
.ram_cfg_i (prim_ram_1p_pkg::RAM_1P_CFG_REQ_DEFAULT),
.ram_cfg_o ( ),

.tl_i (tl_if.h2d ),
.tl_o (tl_if.d2h ),
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/i2c/rtl/i2c.sv
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Expand Up @@ -19,8 +19,8 @@ module i2c
) (
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,
input prim_ram_1p_pkg::ram_1p_cfg_req_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_o,

// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
Expand Down Expand Up @@ -115,7 +115,7 @@ module i2c
.clk_i,
.rst_ni,
.ram_cfg_i,
.ram_cfg_rsp_o,
.ram_cfg_o,

.reg2hw,
.hw2reg,
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/i2c/rtl/i2c_core.sv
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Expand Up @@ -12,8 +12,8 @@ module i2c_core import i2c_pkg::*;
) (
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,
input prim_ram_1p_pkg::ram_1p_cfg_req_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_o,

input i2c_reg_pkg::i2c_reg2hw_t reg2hw,
output i2c_reg_pkg::i2c_hw2reg_t hw2reg,
Expand Down Expand Up @@ -377,7 +377,7 @@ module i2c_core import i2c_pkg::*;
.clk_i,
.rst_ni,
.ram_cfg_i,
.ram_cfg_rsp_o,
.ram_cfg_o,

.fmt_fifo_clr_i (i2c_fifo_fmtrst),
.fmt_fifo_depth_o (fmt_fifo_depth),
Expand Down
6 changes: 3 additions & 3 deletions hw/ip/i2c/rtl/i2c_fifos.sv
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Expand Up @@ -14,8 +14,8 @@ import i2c_reg_pkg::AcqFifoDepth;
) (
input logic clk_i,
input logic rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,
input prim_ram_1p_pkg::ram_1p_cfg_req_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_o,

input logic fmt_fifo_clr_i,
output logic [FifoDepthW-1:0] fmt_fifo_depth_o,
Expand Down Expand Up @@ -300,7 +300,7 @@ import i2c_reg_pkg::AcqFifoDepth;
.rvalid_o (ram_rvalid),
.rerror_o (/* unused */),
.cfg_i (ram_cfg_i),
.cfg_rsp_o(ram_cfg_rsp_o),
.cfg_o (ram_cfg_o),
.alert_o (/* unused */)
);
assign {ram_write, ram_addr, ram_wdata} = ram_arb_oup_data;
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20 changes: 4 additions & 16 deletions hw/ip/otbn/data/otbn.hjson
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Expand Up @@ -201,27 +201,15 @@
// ram configuration
{ struct: "ram_1p_cfg",
package: "prim_ram_1p_pkg",
type: "uni",
type: "req_rsp",
name: "ram_cfg_imem",
act: "rcv"
act: "rsp"
},
{ struct: "ram_1p_cfg",
package: "prim_ram_1p_pkg",
type: "uni",
type: "req_rsp",
name: "ram_cfg_dmem",
act: "rcv"
},
{ struct: "ram_1p_cfg_rsp",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg_rsp_imem",
act: "req"
},
{ struct: "ram_1p_cfg_rsp",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg_rsp_dmem",
act: "req"
act: "rsp"
},

// Lifecycle escalation
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30 changes: 14 additions & 16 deletions hw/ip/otbn/doc/interfaces.md
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Expand Up @@ -10,22 +10,20 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:-----------------|:--------------------------------|:--------|:------|--------:|:--------------|
| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | req | 1 | |
| edn_rnd | edn_pkg::edn | req_rsp | req | 1 | |
| edn_urnd | edn_pkg::edn | req_rsp | req | 1 | |
| idle | prim_mubi_pkg::mubi4 | uni | req | 1 | |
| ram_cfg_imem | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_dmem | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp_imem | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| ram_cfg_rsp_dmem | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
| keymgr_key | keymgr_pkg::otbn_key_req | uni | rcv | 1 | |
| kmac_data | kmac_pkg::app | req_rsp | req | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------|:----------------------------|:--------|:------|--------:|:--------------|
| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | req | 1 | |
| edn_rnd | edn_pkg::edn | req_rsp | req | 1 | |
| edn_urnd | edn_pkg::edn | req_rsp | req | 1 | |
| idle | prim_mubi_pkg::mubi4 | uni | req | 1 | |
| ram_cfg_imem | prim_ram_1p_pkg::ram_1p_cfg | req_rsp | rsp | 1 | |
| ram_cfg_dmem | prim_ram_1p_pkg::ram_1p_cfg | req_rsp | rsp | 1 | |
| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
| keymgr_key | keymgr_pkg::otbn_key_req | uni | rcv | 1 | |
| kmac_data | kmac_pkg::app | req_rsp | req | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

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