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[update] Update yaml files
Update the yaml files to version v1.0.3 of OpenTitan's pentest framework. Signed-off-by: Siemen Dhooghe <sdhooghe@google.com>
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Lines changed: 10592 additions & 2965 deletions

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‎capture/configs/aes_sca_chip.yaml‎

Lines changed: 34 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,17 @@
11
target:
22
target_type: chip
33
fw_bin: "../objs/sca_ujson_chip_signed.img"
4+
opentitantool: "../objs/opentitantool"
45
target_clk_mult: 1
56
target_freq: 100000000
67
baudrate: 115200
7-
output_len_bytes: 16
8-
protocol: "ujson"
9-
port: "/dev/ttyUSB1"
8+
# You can specify the port or leave it empty to find it automatically.
109
# Trigger source.
1110
# hw: Precise, hardware-generated trigger - FPGA only.
1211
# sw: Fully software-controlled trigger.
1312
trigger: "sw"
1413
waverunner:
1514
waverunner_ip: 192.168.33.128
16-
num_segments: 20
1715
# num_samples: 6000
1816
# offset_samples: 0
1917
# cycles will only be used if not given in samples
@@ -24,22 +22,22 @@ waverunner:
2422
channel: C1
2523
sparsing: 0
2624
capture:
27-
scope_select: waverunner
25+
# scope_select: husky, waverunner, none
26+
scope_select: none
2827
num_traces: 1000
29-
show_plot: True
28+
num_segments: 20
29+
show_plot: False
3030
plot_traces: 100
31+
# trace_db: cw
3132
trace_db: ot_trace_library
3233
trace_threshold: 10000
33-
# trace_db: cw
3434
test:
35-
which_test: aes_random_batch
35+
which_test: daisy_chain
36+
# which_test: single
37+
# which_test: daisy_chain
3638
# which_test: aes_random
3739
# which_test: aes_fvsr_key
38-
# which_test: aes_fvsr_key_batch
3940
# which_test: aes_fvsr_data
40-
# which_test: aes_fvsr_data_batch
41-
key_len_bytes: 16
42-
text_len_bytes: 16
4341
# These initial values are used only for random capture but not fixed-vs-random.
4442
key_fixed: [0x81, 0x1E, 0x37, 0x31, 0xB0, 0x12, 0x0A, 0x78, 0x42, 0x78, 0x1E, 0x22, 0xB2, 0x5C, 0xDD, 0xF9]
4543
text_fixed: [0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA]
@@ -49,11 +47,27 @@ test:
4947
# 32-bit seed for masking on device. To switch off the masking, use 0 as LFSR seed.
5048
# lfsr_seed: 0x00000000
5149
lfsr_seed: 0xdeadbeef
52-
# When True, the instruction cache is enabled.
53-
enable_icache: True
54-
# When True, the dummy instructions are enabled.
55-
enable_dummy_instr: False
56-
# When True, enable the jittery clock.
57-
enable_jittery_clock: False
58-
# When True, enable the SRAM readback feature.
59-
sram_readback_enable: False
50+
core_config: {
51+
"enable_icache": True,
52+
"enable_dummy_instr": True,
53+
"dummy_instr_count": 3,
54+
"enable_jittery_clock": True,
55+
"enable_sram_readback": True,
56+
"enable_data_ind_timing": True,
57+
}
58+
sensor_config: {
59+
"sensor_ctrl_enable": True,
60+
"sensor_ctrl_en_fatal": [
61+
False,
62+
False,
63+
False,
64+
False,
65+
False,
66+
False,
67+
False,
68+
False,
69+
False,
70+
False,
71+
False,
72+
],
73+
}

‎capture/configs/aes_sca_cw305.yaml‎

Lines changed: 0 additions & 67 deletions
This file was deleted.

‎capture/configs/aes_sca_cw310.yaml‎

Lines changed: 32 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3,26 +3,23 @@ target:
33
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1_aes.bit"
44
force_program_bitstream: True
55
fw_bin: "../objs/sca_aes_ujson_fpga_cw310.bin"
6+
opentitantool: "../objs/opentitantool"
7+
# You can specify the port or leave it empty to find it automatically.
68
# target_clk_mult is a hardcoded value in the bitstream. Do not change.
79
target_clk_mult: 0.10
810
target_freq: 10000000
911
baudrate: 115200
10-
output_len_bytes: 16
11-
protocol: "ujson"
12-
port: "/dev/opentitan/cw310_1_tty_03"
1312
# Trigger source.
1413
# hw: Precise, hardware-generated trigger - FPGA only.
1514
# sw: Fully software-controlled trigger.
1615
trigger: "hw"
1716
husky:
1817
sampling_rate: 200000000
19-
num_segments: 20
2018
num_cycles: 60
2119
offset_cycles: -2
2220
scope_gain: 38
2321
waverunner:
2422
waverunner_ip: 100.107.71.10
25-
num_segments: 20
2623
# num_samples: 6000
2724
# offset_samples: 0
2825
# cycles will only be used if not given in samples
@@ -33,23 +30,22 @@ waverunner:
3330
channel: C1
3431
sparsing: 0
3532
capture:
33+
# scope_select: husky, waverunner, none
3634
scope_select: husky
37-
# scope_select: waverunner
35+
num_segments: 20
3836
num_traces: 1000
3937
show_plot: True
4038
plot_traces: 100
39+
# trace_db: cw
4140
trace_db: ot_trace_library
4241
trace_threshold: 10000
43-
# trace_db: cw
4442
test:
45-
#which_test: aes_random_batch
43+
which_test: single
44+
# which_test: single
45+
# which_test: daisy_chain
4646
# which_test: aes_random
4747
# which_test: aes_fvsr_key
48-
# which_test: aes_fvsr_key_batch
4948
# which_test: aes_fvsr_data
50-
which_test: aes_fvsr_data_batch
51-
key_len_bytes: 16
52-
text_len_bytes: 16
5349
# These initial values are used only for random capture but not fixed-vs-random.
5450
key_fixed: [0x81, 0x1E, 0x37, 0x31, 0xB0, 0x12, 0x0A, 0x78, 0x42, 0x78, 0x1E, 0x22, 0xB2, 0x5C, 0xDD, 0xF9]
5551
text_fixed: [0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA]
@@ -59,11 +55,27 @@ test:
5955
# 32-bit seed for masking on device. To switch off the masking, use 0 as LFSR seed.
6056
# lfsr_seed: 0x00000000
6157
lfsr_seed: 0xdeadbeef
62-
# When True, the instruction cache is enabled.
63-
enable_icache: True
64-
# When True, the dummy instructions are enabled.
65-
enable_dummy_instr: False
66-
# When True, enable the jittery clock.
67-
enable_jittery_clock: False
68-
# When True, enable the SRAM readback feature.
69-
sram_readback_enable: False
58+
core_config: {
59+
"enable_icache": True,
60+
"enable_dummy_instr": True,
61+
"dummy_instr_count": 3,
62+
"enable_jittery_clock": True,
63+
"enable_sram_readback": True,
64+
"enable_data_ind_timing": True,
65+
}
66+
sensor_config: {
67+
"sensor_ctrl_enable": True,
68+
"sensor_ctrl_en_fatal": [
69+
False,
70+
False,
71+
False,
72+
False,
73+
False,
74+
False,
75+
False,
76+
False,
77+
False,
78+
False,
79+
False,
80+
],
81+
}

‎capture/configs/capture_ecdsa256_cw310.yaml‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@ device:
22
fpga_bitstream: objs/lowrisc_systems_chip_earlgrey_cw310_0.1_ecdsa.bit
33
force_program_bitstream: True
44
fw_bin: objs/ecc256_serial_fpga_cw310.bin
5+
opentitantool: "../objs/opentitantool"
6+
# You can specify the port or leave it empty to find it automatically.
57
# The clock frequency of the target block is equal to
68
# pll_frequency * target_clk_mult. pll_frequency is controllable via
79
# ChipWhisperer API, whereas target_clk_mult is baked into the FPGA
@@ -15,10 +17,6 @@ device:
1517
target_clk_mult: 0.1
1618
baudrate: 115200
1719
capture:
18-
# Only ECDSA-256 (32) and ECDSA-384 (48) are supported at this moment.
19-
key_len_bytes: 32
20-
plain_text_len_bytes: 32
21-
output_len_bytes: 32
2220
# With pll_frequency = 20 MHz and target_clk_mult = 0.1, 2000
2321
# target clock cycles correspond to 200000 scope samples on Husky
2422
# (100x oversampling).

‎capture/configs/capture_ecdsa384_cw310.yaml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@ device:
22
fpga_bitstream: objs/lowrisc_systems_chip_earlgrey_cw310_0.1_ecdsa.bit
33
force_program_bitstream: False
44
fw_bin: objs/ecc384_serial_fpga_cw310.bin
5+
opentitantool: "../objs/opentitantool"
6+
# You can specify the port or leave it empty to find it automatically.
57
# The clock frequency of the target block is equal to
68
# pll_frequency * target_clk_mult. pll_frequency is controllable via
79
# ChipWhisperer API, whereas target_clk_mult is baked into the FPGA

‎capture/configs/hmac_sca_chip.yaml‎

Lines changed: 38 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,13 @@
11
target:
22
target_type: chip
33
fw_bin: "../objs/sca_ujson_chip_signed.img"
4+
opentitantool: "../objs/opentitantool"
5+
# You can specify the port or leave it empty to find it automatically.
46
target_clk_mult: 1
57
target_freq: 100000000
68
baudrate: 115200
7-
output_len_bytes: 16
8-
protocol: "ujson"
9-
port: "/dev/ttyUSB1"
109
waverunner:
1110
waverunner_ip: 192.168.33.128
12-
num_segments: 20
1311
# cycles will only be used if not given in samples
1412
num_cycles: 160
1513
offset_cycles: 115
@@ -18,37 +16,52 @@ waverunner:
1816
channel: C1
1917
sparsing: 0
2018
capture:
21-
scope_select: waverunner
22-
num_traces: 60
19+
# scope_select: husky, waverunner, none
20+
scope_select: none
21+
num_segments: 20
22+
num_traces: 500
2323
show_plot: True
2424
plot_traces: 10
25+
# trace_db: cw
2526
trace_db: ot_trace_library
2627
trace_threshold: 10000
27-
# trace_db: cw
2828
test:
29-
# which_test: hmac_batch_random
30-
# which_test: hmac_batch_fvsr
31-
# which_test: hmac_random
32-
which_test: hmac_fvsr
33-
key_len_bytes: 32
29+
# which_test: single
30+
# which_test: random
31+
# which_test: data_fvsr
32+
# which_test: daisy_chain
33+
which_test: single
3434
key_fixed: [0x81, 0x1E, 0x37, 0x31, 0xB0, 0x12, 0x0A, 0x78, 0x42, 0x78, 0x1E,
3535
0x22, 0xB2, 0x5C, 0xDD, 0xF9, 0x81, 0x1E, 0x37, 0x31, 0xB0, 0x12,
3636
0x0A, 0x78, 0x42, 0x78, 0x1E, 0x22, 0xB2, 0x5C, 0xDD, 0xF9]
37-
msg_len_bytes: 16
3837
text_fixed: [0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA]
3938
# seed for PRNG to generate sequence of messages, and keys; Python random
4039
# class on host, Mersenne twister implementation on OT SW.
4140
batch_prng_seed: 0
4241
# Trigger configuration.
43-
start_trigger: False
44-
msg_trigger: False
45-
process_trigger: True
46-
finish_trigger: False
47-
# When True, the instruction cache is enabled.
48-
enable_icache: True
49-
# When True, the dummy instructions are enabled.
50-
enable_dummy_instr: False
51-
# When True, enable the jittery clock.
52-
enable_jittery_clock: False
53-
# When True, enable the SRAM readback feature.
54-
sram_readback_enable: False
42+
# 0 = start_trigger, 1 = msg_trigger, 2 = process_trigger, 3 = finish_trigger
43+
trigger: 0
44+
core_config: {
45+
"enable_icache": True,
46+
"enable_dummy_instr": True,
47+
"dummy_instr_count": 3,
48+
"enable_jittery_clock": True,
49+
"enable_sram_readback": True,
50+
"enable_data_ind_timing": True,
51+
}
52+
sensor_config: {
53+
"sensor_ctrl_enable": True,
54+
"sensor_ctrl_en_fatal": [
55+
False,
56+
False,
57+
False,
58+
False,
59+
False,
60+
False,
61+
False,
62+
False,
63+
False,
64+
False,
65+
False,
66+
],
67+
}

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