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[fi] Add OTBN command handlers
This commit adds command handlers for the following tests: - otbn_key_sideload - otbn_load_integrity The device code is located in lowRISC/opentitan#21917. The binary was created from lowRISC/opentitan@55091e7 with ./bazelisk.sh build //sw/device/tests/crypto/cryptotest/firmware:firmware_fpga_cw310_test_rom Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
1 parent 7c38c87 commit 679d99f

5 files changed

Lines changed: 120 additions & 7 deletions

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ci/cfg/ci_otbn_fi_vcc_dummy_cw310.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ target:
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target_freq: 24000000
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baudrate: 115200
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protocol: "ujson"
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port: "/dev/ttyACM1"
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port: "/dev/ttyACM_CW310_1"
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# Trigger source.
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# hw: Precise, hardware-generated trigger - FPGA only.
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# sw: Fully software-controlled trigger.
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@@ -0,0 +1,38 @@
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target:
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target_type: cw310
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fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
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force_program_bitstream: False
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fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
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output_len_bytes: 16
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target_clk_mult: 0.24
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target_freq: 24000000
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baudrate: 115200
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protocol: "ujson"
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port: "/dev/ttyACM1"
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fisetup:
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fi_gear: "husky"
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fi_type: "voltage_glitch"
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# Voltage glitch width in cycles.
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glitch_width_min: 5
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glitch_width_max: 150
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glitch_width_step: 3
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# Range for trigger delay in cycles.
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trigger_delay_min: 0
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trigger_delay_max: 500
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trigger_step: 10
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# Number of iterations for the parameter sweep.
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num_iterations: 10000
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fiproject:
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# Project database type and memory threshold.
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project_db: "ot_fi_project"
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project_mem_threshold: 10000
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# Store FI plot.
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show_plot: True
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num_plots: 100
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plot_x_axis: "trigger_delay"
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plot_x_axis_legend: "[cycles]"
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plot_y_axis: "glitch_width"
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plot_y_axis_legend: "[cycles]"
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test:
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which_test: "otbn_key_sideload"
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expected_result: '{"result":0,"err_status":0}'
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@@ -0,0 +1,38 @@
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target:
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target_type: cw310
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fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
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force_program_bitstream: False
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fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
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output_len_bytes: 16
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target_clk_mult: 0.24
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target_freq: 24000000
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baudrate: 115200
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protocol: "ujson"
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port: "/dev/ttyACM1"
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fisetup:
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fi_gear: "husky"
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fi_type: "voltage_glitch"
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# Voltage glitch width in cycles.
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glitch_width_min: 5
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glitch_width_max: 150
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glitch_width_step: 3
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# Range for trigger delay in cycles.
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trigger_delay_min: 0
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trigger_delay_max: 500
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trigger_step: 10
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# Number of iterations for the parameter sweep.
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num_iterations: 10000
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fiproject:
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# Project database type and memory threshold.
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project_db: "ot_fi_project"
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project_mem_threshold: 10000
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# Store FI plot.
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show_plot: True
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num_plots: 100
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plot_x_axis: "trigger_delay"
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plot_x_axis_legend: "[cycles]"
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plot_y_axis: "glitch_width"
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plot_y_axis_legend: "[cycles]"
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test:
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which_test: "otbn_load_integrity"
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expected_result: '{"result":0,"err_status":0}'

fault_injection/fi_otbn.py

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,8 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
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project: The project to store the results.
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ot_communication: The OpenTitan OTBN FI communication interface.
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"""
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# Setup key manager if needed by test.
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ot_communication.init_keymgr(cfg["test"]["which_test"])
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# Configure the trigger.
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ot_communication.init_trigger()
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# Start the parameter sweep.
@@ -87,15 +89,13 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
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while remaining_iterations > 0:
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# Get fault parameters (e.g., trigger delay, glitch voltage).
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fault_parameters = fi_gear.generate_fi_parameters()
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# Arm the FI gear.
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fi_gear.arm_trigger(fault_parameters)
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# Start test on OpenTitan.
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ot_communication.start_test(cfg)
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# Read response.
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response = ot_communication.read_response()
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response = ot_communication.read_response(max_tries=20)
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# Compare response.
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# Check if result is expected result (FI failed), unexpected result
@@ -111,6 +111,8 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
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ot_communication = target.reset_target(com_reset = True)
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# Re-establish UART connection.
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ot_communication = OTFIOtbn(target)
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# Setup key manager if needed by test.
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ot_communication.init_keymgr(cfg["test"]["which_test"])
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# Configure the trigger.
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ot_communication.init_trigger()
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# Reset FIGear if necessary.

target/communication/fi_otbn_commands.py

Lines changed: 38 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,11 +54,46 @@ def otbn_char_hardware_dmem_op_loop(self) -> None:
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time.sleep(0.01)
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self.target.write(json.dumps("CharHardwareDmemOpLoop").encode("ascii"))
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def init_trigger(self) -> None:
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""" Initialize the FI trigger on the chip.
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def otbn_key_sideload(self) -> None:
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""" Starts the otbn.fi.key_sideload test.
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"""
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# OtbnFi command.
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self._ujson_otbn_fi_cmd()
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# KeySideload command.
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time.sleep(0.01)
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self.target.write(json.dumps("KeySideload").encode("ascii"))
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def otbn_load_integrity(self) -> None:
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""" Starts the otbn.fi.load_integrity test.
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"""
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# OtbnFi command.
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self._ujson_otbn_fi_cmd()
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# LoadIntegrity command.
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time.sleep(0.01)
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self.target.write(json.dumps("LoadIntegrity").encode("ascii"))
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def init_keymgr(self, test: str) -> None:
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""" Initialize the key manager on the chip.
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Args:
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cfg: Config dict containing the selected test.
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test: Name of the test. Used to determine if key manager init is
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needed.
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"""
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if "key_sideload" in test:
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# OtbnFi command.
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self._ujson_otbn_fi_cmd()
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# InitTrigger command.
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time.sleep(0.01)
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self.target.write(json.dumps("InitKeyMgr").encode("ascii"))
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# As the init resets the chip, we need to call it again to complete
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# the initialization of the key manager.
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time.sleep(2)
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self._ujson_otbn_fi_cmd()
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time.sleep(0.01)
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self.target.write(json.dumps("InitKeyMgr").encode("ascii"))
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time.sleep(2)
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95+
def init_trigger(self) -> None:
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""" Initialize the FI trigger on the chip.
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"""
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# OtbnFi command.
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self._ujson_otbn_fi_cmd()

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