|
| 1 | +target: |
| 2 | + target_type: chip |
| 3 | + # fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" |
| 4 | + force_program_bitstream: False |
| 5 | + fw_bin: "../objs/fi_ujson_fpga_cw310.bin" |
| 6 | + opentitantool: "../objs/opentitantool" |
| 7 | + target_clk_mult: 0.24 |
| 8 | + target_freq: 24000000 |
| 9 | + baudrate: 115200 |
| 10 | +fisetup: |
| 11 | + # dummy, husky, chipshouter |
| 12 | + fi_gear: "dummy" |
| 13 | + # voltage_glitch, clock_glitch, lfi, emfi |
| 14 | + fi_type: "voltage_glitch" |
| 15 | + parameter_generation: "random" |
| 16 | + # Voltage glitch width in cycles. |
| 17 | + glitch_voltage_min: 150 |
| 18 | + glitch_voltage_max: 150 |
| 19 | + glitch_voltage_step: 10 |
| 20 | + glitch_width_min: 5 |
| 21 | + glitch_width_max: 150 |
| 22 | + glitch_width_step: 3 |
| 23 | + # Range for trigger delay in cycles. |
| 24 | + trigger_delay_min: 0 |
| 25 | + trigger_delay_max: 500 |
| 26 | + trigger_step: 10 |
| 27 | + # Number of iterations for the parameter sweep. |
| 28 | + num_iterations: 100 |
| 29 | +fiproject: |
| 30 | + # Project database type and memory threshold. |
| 31 | + project_db: "ot_fi_project" |
| 32 | + project_mem_threshold: 10000 |
| 33 | + # Store FI plot. |
| 34 | + show_plot: True |
| 35 | + num_plots: 10 |
| 36 | + plot_x_axis: "trigger_delay" |
| 37 | + plot_x_axis_legend: "[cycles]" |
| 38 | + plot_y_axis: "glitch_width" |
| 39 | + plot_y_axis_legend: "[cycles]" |
| 40 | +test: |
| 41 | + # which_test: "crypto_aes_key" |
| 42 | + # which_test: "crypto_aes_plaintext" |
| 43 | + which_test: "crypto_aes_encrypt" |
| 44 | + # which_test: "crypto_fi_aes_ciphertext" |
| 45 | + plaintext: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] |
| 46 | + key: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] |
| 47 | + # Set to true if the test should ignore alerts returned by the test. As the |
| 48 | + # alert handler on the device could sometime fire alerts that are not |
| 49 | + # related to the FI, ignoring is by default set to true. A manual analysis |
| 50 | + # still can be performed as the alerts are stored in the database. |
| 51 | + ignore_alerts: True |
| 52 | + core_config: { |
| 53 | + "enable_icache": True, |
| 54 | + "enable_dummy_instr": True, |
| 55 | + "dummy_instr_count": 3, |
| 56 | + "enable_jittery_clock": True, |
| 57 | + "enable_sram_readback": True, |
| 58 | + "enable_data_ind_timing": True, |
| 59 | + } |
| 60 | + sensor_config: { |
| 61 | + "sensor_ctrl_enable": True, |
| 62 | + "sensor_ctrl_en_fatal": [ |
| 63 | + False, |
| 64 | + False, |
| 65 | + False, |
| 66 | + False, |
| 67 | + False, |
| 68 | + False, |
| 69 | + False, |
| 70 | + False, |
| 71 | + False, |
| 72 | + False, |
| 73 | + False, |
| 74 | + ], |
| 75 | + } |
| 76 | + alert_config: { |
| 77 | + "alert_classes": [ |
| 78 | + 2, # "uart0_fatal_fault", |
| 79 | + 2, # "uart1_fatal_fault", |
| 80 | + 2, # "uart2_fatal_fault", |
| 81 | + 2, # "uart3_fatal_fault", |
| 82 | + 0, # "gpio_fatal_fault", |
| 83 | + 0, # "spi_device_fatal_fault", |
| 84 | + 2, # "i2c0_fatal_fault", |
| 85 | + 2, # "i2c1_fatal_fault", |
| 86 | + 2, # "i2c2_fatal_fault", |
| 87 | + 2, # "pattgen_fatal_fault", |
| 88 | + 0, # "rv_timer_fatal_fault", |
| 89 | + 0, # "otp_ctrl_fatal_macro_error", |
| 90 | + 0, # "otp_ctrl_fatal_check_error", |
| 91 | + 0, # "otp_ctrl_fatal_bus_integ_error", |
| 92 | + 0, # "otp_ctrl_fatal_prim_otp_alert", |
| 93 | + 1, # "otp_ctrl_recov_prim_otp_alert", |
| 94 | + 0, # "lc_ctrl_fatal_prog_error", |
| 95 | + 0, # "lc_ctrl_fatal_state_error", |
| 96 | + 0, # "lc_ctrl_fatal_bus_integ_error", |
| 97 | + 2, # "spi_host0_fatal_fault", |
| 98 | + 2, # "spi_host1_fatal_fault", |
| 99 | + 2, # "usbdev_fatal_fault", |
| 100 | + 0, # "pwrmgr_aon_fatal_fault", |
| 101 | + 0, # "rstmgr_aon_fatal_fault", |
| 102 | + 0, # "rstmgr_aon_fatal_cnsty_fault", |
| 103 | + 1, # "clkmgr_aon_recov_fault", |
| 104 | + 0, # "clkmgr_aon_fatal_fault", |
| 105 | + 2, # "sysrst_ctrl_aon_fatal_fault", |
| 106 | + 2, # "adc_ctrl_aon_fatal_fault", |
| 107 | + 2, # "pwm_aon_fatal_fault", |
| 108 | + 2, # "pinmux_aon_fatal_fault", |
| 109 | + 0, # "aon_timer_aon_fatal_fault", |
| 110 | + 1, # "sensor_ctrl_recov_alert", |
| 111 | + 0, # "sensor_ctrl_fatal_alert", |
| 112 | + 0, # "sram_ctrl_ret_aon_fatal_error", |
| 113 | + 1, # "flash_ctrl_recov_err", |
| 114 | + 0, # "flash_ctrl_fatal_std_err", |
| 115 | + 0, # "flash_ctrl_fatal_err", |
| 116 | + 0, # "flash_ctrl_fatal_prim_flash_alert", |
| 117 | + 1, # "flash_ctrl_recov_prim_flash_alert", |
| 118 | + 0, # "rv_dm_fatal_fault", |
| 119 | + 0, # "rv_plic_fatal_fault", |
| 120 | + 1, # "aes_recov_ctrl_update_err", |
| 121 | + 0, # "aes_fatal_fault", |
| 122 | + 0, # "hmac_fatal_fault", |
| 123 | + 1, # "kmac_recov_operation_err", |
| 124 | + 0, # "kmac_fatal_fault_err", |
| 125 | + 0, # "otbn_fatal", |
| 126 | + 1, # "otbn_recov", |
| 127 | + 1, # "keymgr_recov_operation_err", |
| 128 | + 0, # "keymgr_fatal_fault_err", |
| 129 | + 1, # "csrng_recov_alert", |
| 130 | + 0, # "csrng_fatal_alert", |
| 131 | + 1, # "entropy_src_recov_alert", |
| 132 | + 0, # "entropy_src_fatal_alert", |
| 133 | + 1, # "edn0_recov_alert", |
| 134 | + 0, # "edn0_fatal_alert", |
| 135 | + 1, # "edn1_recov_alert", |
| 136 | + 0, # "edn1_fatal_alert", |
| 137 | + 0, # "sram_ctrl_main_fatal_error", |
| 138 | + 0, # "rom_ctrl_fatal", |
| 139 | + 0, # "rv_core_ibex_fatal_sw_err", |
| 140 | + 1, # "rv_core_ibex_recov_sw_err", |
| 141 | + 0, # "rv_core_ibex_fatal_hw_err", |
| 142 | + 1, # "rv_core_ibex_recov_hw_err" |
| 143 | + ], |
| 144 | + "enable_alerts": [ |
| 145 | + True, # "uart0_fatal_fault", |
| 146 | + True, # "uart1_fatal_fault", |
| 147 | + True, # "uart2_fatal_fault", |
| 148 | + True, # "uart3_fatal_fault", |
| 149 | + True, # "gpio_fatal_fault", |
| 150 | + True, # "spi_device_fatal_fault", |
| 151 | + True, # "i2c0_fatal_fault", |
| 152 | + True, # "i2c1_fatal_fault", |
| 153 | + True, # "i2c2_fatal_fault", |
| 154 | + True, # "pattgen_fatal_fault", |
| 155 | + True, # "rv_timer_fatal_fault", |
| 156 | + True, # "otp_ctrl_fatal_macro_error", |
| 157 | + True, # "otp_ctrl_fatal_check_error", |
| 158 | + True, # "otp_ctrl_fatal_bus_integ_error", |
| 159 | + True, # "otp_ctrl_fatal_prim_otp_alert", |
| 160 | + True, # "otp_ctrl_recov_prim_otp_alert", |
| 161 | + True, # "lc_ctrl_fatal_prog_error", |
| 162 | + True, # "lc_ctrl_fatal_state_error", |
| 163 | + True, # "lc_ctrl_fatal_bus_integ_error", |
| 164 | + True, # "spi_host0_fatal_fault", |
| 165 | + True, # "spi_host1_fatal_fault", |
| 166 | + True, # "usbdev_fatal_fault", |
| 167 | + True, # "pwrmgr_aon_fatal_fault", |
| 168 | + True, # "rstmgr_aon_fatal_fault", |
| 169 | + True, # "rstmgr_aon_fatal_cnsty_fault", |
| 170 | + True, # "clkmgr_aon_recov_fault", |
| 171 | + True, # "clkmgr_aon_fatal_fault", |
| 172 | + True, # "sysrst_ctrl_aon_fatal_fault", |
| 173 | + True, # "adc_ctrl_aon_fatal_fault", |
| 174 | + True, # "pwm_aon_fatal_fault", |
| 175 | + True, # "pinmux_aon_fatal_fault", |
| 176 | + True, # "aon_timer_aon_fatal_fault", |
| 177 | + True, # "sensor_ctrl_recov_alert", |
| 178 | + True, # "sensor_ctrl_fatal_alert", |
| 179 | + True, # "sram_ctrl_ret_aon_fatal_error", |
| 180 | + True, # "flash_ctrl_recov_err", |
| 181 | + True, # "flash_ctrl_fatal_std_err", |
| 182 | + True, # "flash_ctrl_fatal_err", |
| 183 | + False, # "flash_ctrl_fatal_prim_flash_alert", |
| 184 | + True, # "flash_ctrl_recov_prim_flash_alert", |
| 185 | + True, # "rv_dm_fatal_fault", |
| 186 | + True, # "rv_plic_fatal_fault", |
| 187 | + True, # "aes_recov_ctrl_update_err", |
| 188 | + True, # "aes_fatal_fault", |
| 189 | + True, # "hmac_fatal_fault", |
| 190 | + True, # "kmac_recov_operation_err", |
| 191 | + True, # "kmac_fatal_fault_err", |
| 192 | + True, # "otbn_fatal", |
| 193 | + True, # "otbn_recov", |
| 194 | + True, # "keymgr_recov_operation_err", |
| 195 | + True, # "keymgr_fatal_fault_err", |
| 196 | + True, # "csrng_recov_alert", |
| 197 | + True, # "csrng_fatal_alert", |
| 198 | + True, # "entropy_src_recov_alert", |
| 199 | + True, # "entropy_src_fatal_alert", |
| 200 | + True, # "edn0_recov_alert", |
| 201 | + True, # "edn0_fatal_alert", |
| 202 | + True, # "edn1_recov_alert", |
| 203 | + True, # "edn1_fatal_alert", |
| 204 | + True, # "sram_ctrl_main_fatal_error", |
| 205 | + True, # "rom_ctrl_fatal", |
| 206 | + True, # "rv_core_ibex_fatal_sw_err", |
| 207 | + True, # "rv_core_ibex_recov_sw_err", |
| 208 | + True, # "rv_core_ibex_fatal_hw_err", |
| 209 | + True, # "rv_core_ibex_recov_hw_err" |
| 210 | + ], |
| 211 | + "enable_classes": [True, True, False, False], |
| 212 | + "accumulation_thresholds": [2, 2, 2, 2], |
| 213 | + "signals": [4294967295, 0, 2, 3], |
| 214 | + "duration_cycles": [0, 7200, 48, 48], |
| 215 | + "ping_timeout": 1200, |
| 216 | + } |
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