Skip to content

Commit 5da8bd4

Browse files
rivos-eblotjwnrt
rivos-eblot
authored and
jwnrt
committed
target/riscv: add unratified RISC-V Zbr0p93 ext
This extension was not ratified with the Zb[abcs] bitmanip extensions. This is the latest draft version (0.93) as implemented by the Ibex core. These instructions are in the reserved encoding space but have not been ratified and could conflict with future ratified instructions. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
1 parent 6d89325 commit 5da8bd4

9 files changed

Lines changed: 142 additions & 1 deletion

File tree

‎target/riscv/bitmanip_helper.c‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@
2323
#include "exec/target_long.h"
2424
#include "exec/helper-proto.h"
2525
#include "tcg/tcg.h"
26+
#include "qemu/crc32.h"
27+
#include "qemu/crc32c.h"
2628

2729
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
2830
{
@@ -129,3 +131,21 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
129131
{
130132
return do_xperm(rs1, rs2, 3);
131133
}
134+
135+
target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)
136+
{
137+
for (target_ulong i = 0; i < sz; i++) {
138+
rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);
139+
}
140+
141+
return rs1;
142+
}
143+
144+
target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)
145+
{
146+
for (target_ulong i = 0; i < sz; i++) {
147+
rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);
148+
}
149+
150+
return rs1;
151+
}

‎target/riscv/cpu.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1377,6 +1377,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
13771377
/* These are experimental so mark with 'x-' */
13781378
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
13791379
MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
1380+
MULTI_EXT_CFG_BOOL("x-zbr", ext_zbr, false),
13801381

13811382
{ },
13821383
};
@@ -3056,7 +3057,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
30563057
.cfg.ext_zba = true,
30573058
.cfg.ext_zbb = true,
30583059
.cfg.ext_zbc = true,
3059-
.cfg.ext_zbs = true
3060+
.cfg.ext_zbs = true,
3061+
.cfg.ext_zbr = true
30603062
),
30613063

30623064
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,

‎target/riscv/cpu_cfg.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,4 +70,7 @@ MATERIALISE_EXT_PREDICATE(xtheadmempair)
7070
MATERIALISE_EXT_PREDICATE(xtheadsync)
7171
MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
7272

73+
/* Extensions that are not yet upstream */
74+
MATERIALISE_EXT_PREDICATE(zbr);
75+
7376
#endif

‎target/riscv/cpu_cfg_fields.h.inc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ BOOL_FIELD(ext_zbc)
1111
BOOL_FIELD(ext_zbkb)
1212
BOOL_FIELD(ext_zbkc)
1313
BOOL_FIELD(ext_zbkx)
14+
BOOL_FIELD(ext_zbr)
1415
BOOL_FIELD(ext_zbs)
1516
BOOL_FIELD(ext_zca)
1617
BOOL_FIELD(ext_zcb)

‎target/riscv/helper.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
8484
DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
8585
DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
8686
DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
87+
DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl)
88+
DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl)
8789

8890
/* Floating Point - Half Precision */
8991
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)

‎target/riscv/insn32.decode‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -847,6 +847,18 @@ binvi 01101. ........... 001 ..... 0010011 @sh
847847
bset 0010100 .......... 001 ..... 0110011 @r
848848
bseti 00101. ........... 001 ..... 0010011 @sh
849849

850+
# *** RV32 Zbr Experimental Extension ***
851+
crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2
852+
crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2
853+
crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2
854+
crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2
855+
crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2
856+
crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2
857+
858+
# *** RV64 Zbr Experimental Extension (in addition to RV32 Zbr) ***
859+
crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2
860+
crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2
861+
850862
# *** Zfa Standard Extension ***
851863
fli_s 1111000 00001 ..... 000 ..... 1010011 @r2
852864
fli_d 1111001 00001 ..... 000 ..... 1010011 @r2

‎target/riscv/insn_trans/trans_rvb.c.inc‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,12 @@
3636
} \
3737
} while (0)
3838

39+
#define REQUIRE_ZBR(ctx) do { \
40+
if (!ctx->cfg_ptr->ext_zbr) { \
41+
return false; \
42+
} \
43+
} while (0)
44+
3945
#define REQUIRE_ZBS(ctx) do { \
4046
if (!ctx->cfg_ptr->ext_zbs) { \
4147
return false; \
@@ -569,3 +575,34 @@ static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
569575
REQUIRE_ZBKX(ctx);
570576
return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
571577
}
578+
579+
static bool gen_crc(DisasContext *ctx, arg_r2 *a,
580+
void (*func)(TCGv, TCGv, TCGv), TCGv tsz)
581+
{
582+
REQUIRE_ZBR(ctx);
583+
TCGv dest = dest_gpr(ctx, a->rd);
584+
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
585+
586+
func(dest, src1, tsz);
587+
gen_set_gpr(ctx, a->rd, dest);
588+
589+
return true;
590+
}
591+
592+
#define TRANS_CRC32(NAME, SIZE) \
593+
static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \
594+
{ if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
595+
return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); }
596+
#define TRANS_CRC32C(NAME, SIZE) \
597+
static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \
598+
{ if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
599+
return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); }
600+
601+
TRANS_CRC32(b, 1);
602+
TRANS_CRC32(h, 2);
603+
TRANS_CRC32(w, 4);
604+
TRANS_CRC32(d, 8);
605+
TRANS_CRC32C(b, 1);
606+
TRANS_CRC32C(h, 2);
607+
TRANS_CRC32C(w, 4);
608+
TRANS_CRC32C(d, 8);

‎tests/tcg/riscv64/Makefile.softmmu-target‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,5 +36,10 @@ run-plugin-interruptedmemory: interruptedmemory
3636
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
3737
$(QEMU_OPTS)$<)
3838

39+
EXTRA_RUNS += run-test-crc32
40+
comma:= ,
41+
run-test-crc32: test-crc32
42+
$(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-zbr=true $(QEMU_OPTS)$<)
43+
3944
# We don't currently support the multiarch system tests
4045
undefine MULTIARCH_TESTS

‎tests/tcg/riscv64/test-crc32.S‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
#define crc32(op, rd, rs1) .insn r 19, 1, 48, rd, rs1, x##op
2+
3+
#define crc32_b(rd, rs1) crc32(16, rd, rs1)
4+
#define crc32_h(rd, rs1) crc32(17, rd, rs1)
5+
#define crc32_w(rd, rs1) crc32(18, rd, rs1)
6+
#define crc32_d(rd, rs1) crc32(19, rd, rs1)
7+
#define crc32c_b(rd, rs1) crc32(24, rd, rs1)
8+
#define crc32c_h(rd, rs1) crc32(25, rd, rs1)
9+
#define crc32c_w(rd, rs1) crc32(26, rd, rs1)
10+
#define crc32c_d(rd, rs1) crc32(27, rd, rs1)
11+
12+
.option norvc
13+
14+
.text
15+
.globl _start
16+
_start:
17+
lla t0, trap
18+
csrw mtvec, t0
19+
20+
li t0, 0x34e24a2cd65650d4
21+
22+
crc32_b (t0, t0)
23+
crc32_h (t0, t0)
24+
crc32_w (t0, t0)
25+
crc32_d (t0, t0)
26+
crc32c_b (t0, t0)
27+
crc32c_h (t0, t0)
28+
crc32c_w (t0, t0)
29+
crc32c_d (t0, t0)
30+
31+
li t1, 0x68167e78
32+
33+
li a0, 0
34+
beq t0, t1, _exit
35+
fail:
36+
li a0, 1
37+
_exit:
38+
lla a1, semiargs
39+
li t0, 0x20026 # ADP_Stopped_ApplicationExit
40+
sd t0, 0(a1)
41+
sd a0, 8(a1)
42+
li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED
43+
44+
# Semihosting call sequence
45+
.balign 16
46+
slli zero, zero, 0x1f
47+
ebreak
48+
srai zero, zero, 0x7
49+
j .
50+
51+
.data
52+
.balign 16
53+
semiargs:
54+
.space 16
55+
56+
trap:
57+
csrr t0, mepc
58+
addi t0, t0, 4
59+
mret

0 commit comments

Comments
 (0)