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target/riscv: add draft RISC-V Zbr ext as xbr0p93
This extension was not ratified with the Zb[abcs] bitmanip extensions. This is the latest draft version (0.93) as implemented by the Ibex core. These instructions are in the reserved encoding space but have not been ratified and could conflict with future ratified instructions. For this reason they are added as a vendor extension to support Ibex's impl. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org>
1 parent 6d89325 commit b6efb21

11 files changed

Lines changed: 197 additions & 1 deletion

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‎target/riscv/bitmanip_helper.c‎

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@@ -23,6 +23,8 @@
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#include "exec/target_long.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg.h"
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#include "qemu/crc32.h"
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#include "qemu/crc32c.h"
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target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
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{
@@ -129,3 +131,21 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
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{
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return do_xperm(rs1, rs2, 3);
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}
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target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)
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{
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for (target_ulong i = 0; i < sz; i++) {
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rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);
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}
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return rs1;
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}
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target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)
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{
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for (target_ulong i = 0; i < sz; i++) {
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rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);
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}
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return rs1;
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}

‎target/riscv/cpu.c‎

Lines changed: 3 additions & 1 deletion
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@@ -1370,6 +1370,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
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MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
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MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
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MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false),
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MULTI_EXT_CFG_BOOL("xbr0p93", ext_xbr0p93, false),
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13741375
{ },
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};
@@ -3056,7 +3057,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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.cfg.ext_zba = true,
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.cfg.ext_zbb = true,
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.cfg.ext_zbc = true,
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.cfg.ext_zbs = true
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.cfg.ext_zbs = true,
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.cfg.ext_xbr0p93 = true
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),
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,

‎target/riscv/cpu_cfg.h‎

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@@ -69,5 +69,6 @@ MATERIALISE_EXT_PREDICATE(xtheadmemidx)
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MATERIALISE_EXT_PREDICATE(xtheadmempair)
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MATERIALISE_EXT_PREDICATE(xtheadsync)
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MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
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MATERIALISE_EXT_PREDICATE(xbr0p93);
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#endif

‎target/riscv/cpu_cfg_fields.h.inc‎

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Original file line numberDiff line numberDiff line change
@@ -153,6 +153,7 @@ BOOL_FIELD(ext_XVentanaCondOps)
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BOOL_FIELD(ext_xmipscbop)
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BOOL_FIELD(ext_xmipscmov)
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BOOL_FIELD(ext_xmipslsp)
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BOOL_FIELD(ext_xbr0p93)
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BOOL_FIELD(mmu)
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BOOL_FIELD(pmp)

‎target/riscv/helper.h‎

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@@ -84,6 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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/* Floating Point - Half Precision */
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DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)

‎target/riscv/insn_trans/trans_xbr0p93.c.inc‎

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@@ -0,0 +1,55 @@
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/*
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* RISC-V translation routines for xbr0p93 matching the unratified Zbr CRC32
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* bitmanip extension v0.93.
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*
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* Copyright (c) 2026 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_XBR0P93(ctx) do { \
21+
if (!ctx->cfg_ptr->ext_xbr0p93) { \
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return false; \
23+
} \
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} while (0)
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static bool gen_crc(DisasContext *ctx, arg_r2 *a,
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void (*func)(TCGv, TCGv, TCGv), TCGv tsz)
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{
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REQUIRE_XBR0P93(ctx);
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
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func(dest, src1, tsz);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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#define TRANS_CRC32(NAME, SIZE) \
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static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \
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{ if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
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return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); }
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#define TRANS_CRC32C(NAME, SIZE) \
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static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \
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{ if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \
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return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); }
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TRANS_CRC32(b, 1);
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TRANS_CRC32(h, 2);
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TRANS_CRC32(w, 4);
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TRANS_CRC32(d, 8);
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TRANS_CRC32C(b, 1);
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TRANS_CRC32C(h, 2);
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TRANS_CRC32C(w, 4);
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TRANS_CRC32C(d, 8);

‎target/riscv/meson.build‎

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@@ -5,6 +5,7 @@ gen = [
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decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
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decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
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decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),
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decodetree.process('xbr0p93.decode', extra_args: '--static-decode=decode_xbr0p93'),
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]
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riscv_ss = ss.source_set()

‎target/riscv/translate.c‎

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@@ -1213,9 +1213,11 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
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#include "insn_trans/trans_rvbf16.c.inc"
12141214
#include "decode-xthead.c.inc"
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#include "decode-xmips.c.inc"
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#include "decode-xbr0p93.c.inc"
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#include "insn_trans/trans_xthead.c.inc"
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#include "insn_trans/trans_xventanacondops.c.inc"
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#include "insn_trans/trans_xmips.c.inc"
1220+
#include "insn_trans/trans_xbr0p93.c.inc"
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12201222
/* Include the auto-generated decoder for 16 bit insn */
12211223
#include "decode-insn16.c.inc"
@@ -1235,6 +1237,7 @@ const RISCVDecoder decoder_table[] = {
12351237
{ has_xmips_p, decode_xmips},
12361238
{ has_xthead_p, decode_xthead},
12371239
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps},
1240+
{ has_xbr0p93_p, decode_xbr0p93},
12381241
};
12391242

12401243
const size_t decoder_table_size = ARRAY_SIZE(decoder_table);

‎target/riscv/xbr0p93.decode‎

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@@ -0,0 +1,42 @@
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#
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# Translation routines for the instructions of the xbr0p93 ISA extension
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# (matching the draft encodings in the standard reserved encoding space for the
4+
# unratified Zbr CRC32 bitmanip extension version 0.93).
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#
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# Copyright (c) 2026 Rivos Inc.
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# This program is free software; you can redistribute it and/or modify it
11+
# under the terms and conditions of the GNU General Public License,
12+
# version 2 or later, as published by the Free Software Foundation.
13+
#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16+
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
18+
#
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# You should have received a copy of the GNU General Public License along with
20+
# this program. If not, see <http://www.gnu.org/licenses/>.
21+
22+
# Fields:
23+
%rs1 15:5
24+
%rd 7:5
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# Argument sets:
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&r2 rd rs1 !extern
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# Formats 32:
30+
@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
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32+
# *** RV32 xbr0p93 extension ***
33+
crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2
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crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2
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crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2
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crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2
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crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2
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crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2
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40+
# *** RV64 xbr0p93 extension (in addition to RV32) ***
41+
crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2
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crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2

‎tests/tcg/riscv64/Makefile.softmmu-target‎

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@@ -36,5 +36,10 @@ run-plugin-interruptedmemory: interruptedmemory
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$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
3737
$(QEMU_OPTS)$<)
3838

39+
EXTRA_RUNS += run-test-crc32
40+
comma:= ,
41+
run-test-crc32: test-crc32
42+
$(call run-test, $<, $(QEMU) -cpu rv64$(comma)xbr0p93=true $(QEMU_OPTS)$<)
43+
3944
# We don't currently support the multiarch system tests
4045
undefine MULTIARCH_TESTS

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