sonata.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:sonata:system"
description: "Sonata System"
filesets:
  files_rtl:
    depend:
      - lowrisc:sonata:design

  files_sonata:
    depend:
      - lowrisc:ibex:fpga_xilinx_shared
    files:
      - rtl/fpga/padring.sv
      - rtl/fpga/top_sonata.sv
      - rtl/fpga/clkgen_sonata.sv
      - rtl/fpga/rst_ctrl.sv
      - rtl/system/rs485_ctrl.sv
    file_type: systemVerilogSource

  files_verilator:
    depend:
      - lowrisc:ibex:sim_shared
      - lowrisc:dv_verilator:memutil_verilator
      - lowrisc:dv_verilator:simutil_verilator
      - lowrisc:dv_verilator:ibex_pcounts
      - lowrisc:dv_dpi_c:jtagdpi:0.1
      - lowrisc:dv_dpi_sv:jtagdpi:0.1
      - lowrisc:dv_dpi_c:uartdpi:0.1
      - lowrisc:dv_dpi_sv:uartdpi:0.1
      - lowrisc:dv_dpi_c:usbdpi:0.1
      - lowrisc:dv_dpi_sv:usbdpi:0.1
      - lowrisc:sonata:i2cdpi
      - lowrisc:sonata:spidevicedpi
    files:
      - rtl/system/rs485_ctrl.sv: { file_type: systemVerilogSource }
      - dv/models/hyperram/rtl/hyperram_W956.sv: { file_type: systemVerilogSource }
      - dv/models/fpga/rtl/DNA_PORT.v: { file_type: systemVerilogSource }
      - dv/models/fpga/rtl/IOBUF.v: { file_type: systemVerilogSource }
      - dv/models/fpga/rtl/ISERDESE2.v: { file_type: systemVerilogSource }
      - dv/models/fpga/rtl/OBUF.v: { file_type: systemVerilogSource }
      - dv/models/fpga/rtl/ODDR.v: { file_type: systemVerilogSource }
      - dv/verilator/top_verilator.sv: { file_type: systemVerilogSource }
      - dv/verilator/sonata_system.cc: { file_type: cppSource }
      - dv/verilator/sonata_system.hh:  { file_type: cppSource, is_include_file: true }
      - dv/verilator/sonata_system_main.cc: { file_type: cppSource }
      - dv/verilator/sonata_verilator_lint.vlt:  { file_type: vlt }

  files_constraints_sonata:
    files:
      # Per AMD advice (UG949):
      #   1 file for physical + 1 file for timing (synthesis) + 1 file for timing (implementation)
      # Complicated by the differences between Sonata One and Sonata XL
      - target_synth    ? (data/pins_sonata.xdc)
      - target_synth_xl ? (data/pins_sonata_xl.xdc)
      -                    data/synth_timing_common.xdc
      - target_synth    ? (data/synth_timing.xdc)
      - target_synth_xl ? (data/synth_timing_xl.xdc)
      -                    data/impl_timing.xdc
    file_type: xdc

  files_tcl:
    files:
      - flow/vivado_setup.tcl : { file_type: tclSource }
      - flow/vivado_hook_opt_design_pre.tcl : { file_type: user, copyto: vivado_hook_opt_design_pre.tcl }
      - flow/vivado_hook_route_design_pre.tcl : { file_type: user, copyto: vivado_hook_route_design_pre.tcl }

parameters:
  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
  # --SRAMInitFile=$PWD/sw/led/led.vmem
  # XXX: The VMEM file should be added to the sources of the Vivado project to
  # make the Vivado dependency tracking work. However this requires changes to
  # fusesoc first.
  SRAMInitFile:
    datatype: str
    description: SRAM initialization file in vmem hex format
    default: "../../../../../sw/cheri/build/boot/boot_loader.vmem"
    # Alternative boot stub for legacy mode.
    #default: "../../../../../sw/legacy/build/boot/boot.vmem"
    paramtype: vlogparam

  USE_SEPARATED_CLOCKS:
    datatype: bool
    paramtype: vlogdefine
    description: Use separate clocks for a more accurate, but slower, simulation.

  # For value definition, please see ip/prim/rtl/prim_pkg.sv
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".

  USE_HYPERRAM_SRAM_MODEL:
    datatype: bool
    paramtype: vlogdefine
    description: Use an SRAM implementation rather than the real HyperRAM controller

  TARGET_XL_BOARD:
    datatype: bool
    paramtype: vlogdefine
    description: Targeting the Sonata XL board rather than the Sonata One board.

targets:
  default: &default_target
    filesets:
      - files_rtl

  synth:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_sonata
      - files_constraints_sonata
      - files_tcl
    toplevel: top_sonata
    tools:
      vivado:
        part: "xc7a50tcsg324-2" # Artix-7 50T
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx

  synth_xl:
    <<: *default_target
    default_tool: vivado
    filesets_append:
      - files_sonata
      - files_constraints_sonata
      - files_tcl
    toplevel: top_sonata
    tools:
      vivado:
        part: "xc7a200tfbg676-2" # Artix-7 200T
    parameters:
      - SRAMInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
      - USE_HYPERRAM_SRAM_MODEL=true
      - TARGET_XL_BOARD=true

  sim:
    <<: *default_target
    default_tool: verilator
    filesets_append:
      - files_verilator
    toplevel: top_verilator
    tools:
      verilator:
        mode: cc
        verilator_options:
          # Disabling tracing reduces compile times but doesn't have a
          # huge influence on runtime performance.
          - '--trace'
          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          # For a faster simulation using the SRAM model:
          - '-CFLAGS "-Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator -DUSE_HYPERRAM_SRAM_MODEL"'
          # For a more accurate simulation using the HyperBus controller itself or correct USB frequency:
          # - '-CFLAGS "-Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=top_verilator -DUSE_SEPARATED_CLOCKS"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"
          - "-Wwarn-IMPERFECTSCH"
          # RAM primitives wider than 64bit (required for ECC) fail to build in
          # Verilator without increasing the unroll count (see Verilator#1266)
          - "--unroll-count 72"
    parameters:
      # Comment out the following line when simulating with the HyperBus controller.
      - USE_HYPERRAM_SRAM_MODEL=true
      # Set the following line to true for HyperBus controller or correct USB frequency;
      # use false for the SRAM model.
      - USE_SEPARATED_CLOCKS=false
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric

  lint:
    <<: *default_target
    default_tool: verilator
    filesets_append:
      - files_verilator
    toplevel: top_verilator
    tools:
      verilator:
        mode: lint-only
    parameters:
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
      # TODO: Introduce some blackboxes for the Xilinx IP used in the hyperram
      # controller so we can lint it, for now just exclude it from the lint run.
      - USE_HYPERRAM_SRAM_MODEL=true