[doc] Update PLIC interrupt mapping

These were out of date for the newer releases which combined multiple
interrupt sources into a single shared interrupt line per
block/instance, and which also added more interrupt sources (GPIO, USB
device, hardware revoker).

Signed-off-by: Alex Jones <alex.jones@lowrisc.org>

Author: AlexJones0

doc/ip/plic.md

@@ -7,33 +7,27 @@ Not all of these registers are mapped, most importantly we only have one core, s
 
 The following table shows the current list of interrupts that are fed through the PLIC.
 For more detailed descriptions of what each interrupt means, please refer to the documentation of each individual hardware IP block.
-More interrupts may be added to this table in the future.
-
-| Number | Block     | Interrupt description |
-|--------|-----------|-----------------------|
-|  0     | None      | Tied to zero
-|  1,  9 | UART 0, 1 | Transmit watermark
-|  2, 10 | UART 0, 1 | Receive watermark
-|  3, 11 | UART 0, 1 | Transmit empty
-|  4, 12 | UART 0, 1 | Receive overflow
-|  5, 13 | UART 0, 1 | Receive frame error
-|  6, 14 | UART 0, 1 | Receive break error
-|  7, 15 | UART 0, 1 | Receive timeout
-|  8, 16 | UART 0, 1 | Receive parity error
-| 17, 32 | I2C 0, 1  | Format FIFO threshold
-| 18, 33 | I2C 0, 1  | Receive FIFO threshold
-| 19, 34 | I2C 0, 1  | Acquire FIFO threshold
-| 20, 35 | I2C 0, 1  | Receive FIFO overflow
-| 21, 36 | I2C 0, 1  | Received NACK
-| 22, 37 | I2C 0, 1  | SCL interference
-| 23, 38 | I2C 0, 1  | SDA interference
-| 24, 39 | I2C 0, 1  | Stretch timeout
-| 25, 40 | I2C 0, 1  | SDA unstable
-| 26, 41 | I2C 0, 1  | Command complete
-| 27, 42 | I2C 0, 1  | Transmit stretch
-| 28, 43 | I2C 0, 1  | Transmit threshold
-| 29, 44 | I2C 0, 1  | Acquire FIFO full
-| 30, 45 | I2C 0, 1  | Unexpected stop
-| 31, 46 | I2C 0, 1  | Host timeout
-| 47     | Ethernet  | Interrupt from external SPI ethernet chip (KSZ8851SNLI-TR). Check the interrupt status register for details.
+For most blocks, interrupts are multiplexed - all hardware interrupt sources are presented as a single interrupt to the PLIC.
+The relevant software `INTR_STATE` registers should be queried by software to determine the interrupt cause.
 
+| Number | Block      | Interrupt description |
+|--------|------------|-----------------------|
+| 0      | None       | Tied to zero
+| 1      | Revoker    | Hardware revoker sweep complete
+| 2      | Ethernet   | Interrupt from external SPI ethernet chip (KSZ8851SNLI-TR)
+| 3      | USB Dev    | Shared USB Device interrupt
+| 4      | GPIO       | Shared GPIO interrupt
+| 5-7    | None       | Reserved
+| 8      | UART 0     | Shared interrupt for UART0
+| 9      | UART 1     | Shared interrupt for UART1
+| 10     | UART 2     | Shared interrupt for UART2
+| 11-15  | None       | Reserved
+| 16     | I2C 0      | Shared interrupt for I2C0
+| 17     | I2C 1      | Shared interrupt for I2C1
+| 18-23  | None       | Reserved
+| 24     | SPI LCD    | Shared interrupt for the LCD SPI
+| 25     | SPI Ethmac | Shared interrupt for the Ethernet SPI
+| 26     | SPI 0      | Shared interrupt for SPI0
+| 27     | SPI 1      | Shared interrupt for SPI1
+| 28     | SPI 2      | Shared interrupt for SPI2
+| 29-31  | None       | Reserved