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[DPI] Create .core file for i2cdpi to help reuse
Having a .core file specifically for the I^2C DPI module makes it easier to use in other projects.
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dv/dpi/i2cdpi/i2cdpi.core

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CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:sonata:i2cdpi"
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description: "I^2C DPI model"
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filesets:
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files_rtl:
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files:
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- i2cdpi.sv: { file_type: systemVerilogSource }
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files_c:
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files:
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- i2c_lsm9ds1.cc: { file_type: cppSource }
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- i2c_lsm9ds1.hh: { file_type: cppSource, is_include_file: true }
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- i2c_as621x.cc: { file_type: cppSource }
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- i2c_as621x.hh: { file_type: cppSource, is_include_file: true }
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- i2c_hat_id.cc: { file_type: cppSource }
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- i2c_hat_id.hh: { file_type: cppSource, is_include_file: true }
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- i2cdevice.cc: { file_type: cppSource }
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- i2cdevice.hh: { file_type: cppSource, is_include_file: true }
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- i2cdpi.cc: { file_type: cppSource }
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- i2cdpi.hh: { file_type: cppSource, is_include_file: true }
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targets:
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default:
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filesets:
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- files_rtl
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- files_c
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sonata.core

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- lowrisc:dv_dpi_sv:uartdpi:0.1
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- lowrisc:dv_dpi_c:usbdpi:0.1
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- lowrisc:dv_dpi_sv:usbdpi:0.1
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- lowrisc:sonata:i2cdpi
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- lowrisc:sonata:spidevicedpi
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files:
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- rtl/system/rs485_ctrl.sv: { file_type: systemVerilogSource }
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- dv/dpi/i2cdpi/i2c_lsm9ds1.cc: { file_type: cppSource }
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- dv/dpi/i2cdpi/i2c_lsm9ds1.hh: { file_type: cppSource, is_include_file: true }
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- dv/dpi/i2cdpi/i2c_as621x.cc: { file_type: cppSource }
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- dv/dpi/i2cdpi/i2c_as621x.hh: { file_type: cppSource, is_include_file: true }
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- dv/dpi/i2cdpi/i2c_hat_id.cc: { file_type: cppSource }
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- dv/dpi/i2cdpi/i2c_hat_id.hh: { file_type: cppSource, is_include_file: true }
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- dv/dpi/i2cdpi/i2cdevice.cc: { file_type: cppSource }
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- dv/dpi/i2cdpi/i2cdevice.hh: { file_type: cppSource, is_include_file: true }
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- dv/dpi/i2cdpi/i2cdpi.sv: { file_type: systemVerilogSource }
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- dv/dpi/i2cdpi/i2cdpi.cc: { file_type: cppSource }
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- dv/dpi/i2cdpi/i2cdpi.hh: { file_type: cppSource, is_include_file: true }
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- dv/models/hyperram/rtl/hyperram_W956.sv: { file_type: systemVerilogSource }
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- dv/models/fpga/rtl/DNA_PORT.v: { file_type: systemVerilogSource }
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- dv/models/fpga/rtl/IOBUF.v: { file_type: systemVerilogSource }

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