[SystemRDL] Create a sonata top level description

Signed-off-by: Douglas Reis <doreis@lowrisc.org>

Author: engdoreis

data/top.rdl

@@ -0,0 +1,30 @@
+`include "udp.rdl"
+`include "../rtl/ip/system_info/data/system_info.rdl"
+`include "../rtl/ip/spi/data/spi.rdl"
+`include "../rtl/ip/rgbled_ctrl/data/rgbled_ctrl.rdl"
+`include "../rtl/ip/pwm/data/pwm.rdl"
+`include "../rtl/ip/gpio/data/gpio.rdl"
+`include "../rtl/ip/usbdev/data/usbdev.rdl"
+`include "../rtl/ip/i2c/data/i2c.rdl"
+`include "../rtl/ip/uart/data/uart.rdl"
+`include "../rtl/system/autogen/rv_plic/data/rv_plic.rdl"
+
+addrmap top_sonata {
+  gpio GPIO @ 0x80000000;
+  gpio GPIO_RPI @ 0x80000040;
+  gpio GPIO_ARDUINO @ 0x80000080;
+  gpio GPIO_PMOD[2] @ 0x800000C0 += 0x40;
+  gpio GPIO_PMODC @ 0x80000140;
+  pwm PWM[6] @ 0x80001000 += 0x08;
+  pwm PWM_LCD;
+  rgbled_ctrl RGBLED_CTRL @ 0x80009000;
+  system_info SYSTEM_INFO @ 0x8000C000;
+  uart uart[3] @ 0x80100000 += 0x1000;
+  i2c I2C[2] @ 0x80200000 += 0x1000;
+  spi SPI_LCD @ 0x80300000;
+  spi SPI_ETHMAC @ 0x80301000;
+  spi SPI[3]  @ 0x80302000 += 0x1000;
+  usbdev USBDEV @ 0x80400000;
+  rv_plic RV_PLIC @ 0x88000000;
+};
+  

data/udp.rdl

@@ -0,0 +1,105 @@
+/* Copyright lowRISC contributors (OpenTitan project).
+* Licensed under the Apache License, Version 2.0; see LICENSE for details.
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+/**
+ * 4-bits boolean values
+ */
+enum MultiBitBool4 {
+  True = 0x6;
+  False = 0x9;
+};
+
+/**
+ * 8-bits boolean values
+ */
+enum MultiBitBool8 {
+  True = 0x96;
+  False = 0x69;
+};
+
+/**
+ * 12-bits boolean values
+ */
+enum MultiBitBool12 {
+  True = 0x696;
+  False = 0x969;
+};
+
+/**
+ * 16-bits boolean values
+ */
+enum MultiBitBool16 {
+  True = 0x9696;
+  False = 0x6969;
+};
+
+/**
+ * 20-bits boolean values
+ */
+enum MultiBitBool20 {
+  True = 0x69696;
+  False = 0x96969;
+};
+
+/**
+ * 24-bits boolean values
+ */
+enum MultiBitBool24 {
+  True = 0x969696;
+  False = 0x696969;
+};
+
+/**
+ * 28-bits boolean values
+ */
+enum MultiBitBool28 {
+  True = 0x6969696;
+  False = 0x9696969;
+};
+
+/**
+ * 32-bits boolean values
+ */
+enum MultiBitBool32 {
+  True = 0x96969696;
+  False = 0x69696969;
+};
+
+/**
+ * true if hardware uses `re` signal, which is latched signal of software read pulse.
+ * The standard SystemRDL property `swacc` cannot be used here because `swacc = hwre | swmod`.
+ */
+property hwre {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/* If it is true, the register will be implemented using the prim_subreg_shadow module.
+ * Shadow registers are a mechanism to guard sensitive registers against this specific
+ * type of attack. They come at a cost of increased area, and a modified SW interaction.
+ */
+property shadowed {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/* Indicates the register must cross to a different clock domain before use.
+ * The value shown here should correspond to one of the module’s clocks.
+ */
+property async_clk {
+  type = boolean;
+  component = reg;
+  default = false;
+};
+
+/* If true, integrity bits are passed through directly from the memory.
+ */
+property integrity_bypass {
+  type = boolean;
+  component = mem;
+  default = false;
+};

rtl/ip/gpio/data/gpio.rdl

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+addrmap gpio {
+  reg {
+    field {
+      sw=w;
+      reset = 0;
+      desc = "Pins.";
+    } PINS[32] = 0;
+  } OUT @0x0000;
+
+  reg {
+    field {
+      sw=r;
+      reset = 0;
+      desc = "Pins.";
+    } PINS[32] = 0;
+  } IN @0x0004;
+
+  reg {
+    field {
+      sw=r;
+      reset = 0;
+      desc = "DBNC.";
+    } PINS[32] = 0;
+  } IN_DBNC @0x0008;
+
+  reg  {
+    field {
+      sw=rw;
+      reset = 0;
+      desc = "val";
+    } PINS[32] = 0;
+  } OUTPUT_ENABLE @0x000c;
+
+};