[doc] Minor I2C/UART doc updates to point to the locked OT revision

Make sure that the linked documentation actually reflects the state of
the registers, even if it isn't on the rendered OpenTitan site. Also
make a couple of grammatical fixes and correct a typo.

Signed-off-by: Alex Jones <alex.jones@lowrisc.org>

Author: AlexJones0

doc/ip/i2c.md

@@ -1,13 +1,15 @@
 # Inter-integrated circuit (I2C) host
 
-For the I2C block in Sonata, we use the [OpenTitan IP](https://opentitan.org/book/hw/ip/i2c/index.html).
-We hardcode this block to be in host mode, so you can ignore the target functionality, including register `ovrd`, `val`, `target_id`, `acqdata` and `txdata`.
-Other than those you can find the [register definitions here](https://opentitan.org/book/hw/ip/i2c/doc/registers.html).
+For the I2C block in Sonata, we use the OpenTitan IP.
+The version of the IP that is vendored in has documentation that you can find [here](https://github.com/lowRISC/opentitan/tree/a78922f14a8cc20c7ee569f322a04626f2ac6127/hw/ip/i2c/doc).
+Another useful reference is the [existing driver](https://github.com/microsoft/cheriot-rtos/blob/main/sdk/include/platform/sunburst/platform-i2c.hh) for this block in the CHERIoT RTOS repository.
+We hardcode this block to be in host mode, so you can ignore the target functionality, including the following registers: `ovrd`, `val`, `target_id`, `acqdata` and `txdata`.
+Other than those, you can find the [register definitions here](https://github.com/lowRISC/opentitan/blob/a78922f14a8cc20c7ee569f322a04626f2ac6127/hw/ip/i2c/doc/registers.md).
 The registers `0x00` - `0x10` are also not accessible.
 The control register is just hardwired to be in host mode.
 
 For Sonata, we include two I2C blocks.
-The registers of the second I2C block can be accessed with and additional `0x1000` offset.
+The registers of the second I2C block can be accessed with an additional `0x1000` offset.
 These can be connected to any of these I2C targets:
 - Two for the QWIIC connectors.
 - One for the mikroBUS.

doc/ip/uart.md

@@ -1,7 +1,8 @@
 # Universal asynchronous receiver/transmitter (UART)
 
-The Sonata system uses [the OpenTitan UART](https://opentitan.org/book/hw/ip/uart/index.html).
-You can find [the register definitions here](https://opentitan.org/book/hw/ip/uart/doc/registers.html).
+The Sonata system uses the OpenTitan UART.
+The version of the IP that is vendored in has documentation that you can find [here](https://github.com/lowRISC/opentitan/tree/a78922f14a8cc20c7ee569f322a04626f2ac6127/hw/ip/uart/doc).
+You can find [the register definitions here](https://github.com/lowRISC/opentitan/blob/a78922f14a8cc20c7ee569f322a04626f2ac6127/hw/ip/uart/doc/registers.md).
 
 There are multiple UART instances in Sonata to connect to any of the following targets:
 - USB