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add integer MaxPool1D for Generic platform and add tests for both int and float MaxPool1D
1 parent f792722 commit 07cdb42

26 files changed

Lines changed: 87 additions & 54 deletions

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‎.github/workflows/ci-deeploy.yml‎

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python testTilerExtension.py -p Siracusa -t ./Tests/Models/CNN_Linear2
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python testTilerExtension.py -p Siracusa -t ./Tests/Models/CNN_Linear1
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MatMul/Regular
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool/Regular_2D
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python testTilerExtension.py -p Siracusa -t ./Tests/Models/CNN_Linear2 --l1 2000 --shouldFail
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python testTilerExtension.py -p Siracusa -t ./Tests/Models/CNN_Linear1 --l1 2000 --shouldFail
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MatMul/Regular --l1 2000 --shouldFail
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool --l1 2000 --shouldFail
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool/Regular_2D --l1 2000 --shouldFail
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deeploy-memory-allocation-extension:
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needs: select-env
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python testTilerExtension.py -p Siracusa -t ./Tests/Models/miniMobileNet
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python testTilerExtension.py -p Siracusa -t ./Tests/Models/miniMobileNetv2
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MatMul/Regular
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool
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python testTilerExtension.py -p Siracusa -t ./Tests/Kernels/Integer/MaxPool/Regular_2D
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deeploy-typing:
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needs: select-env

‎.github/workflows/ci-platform-cortexm.yml‎

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Kernels/Integer/Pad/Regular_2D
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Kernels/Integer/MatMul/Regular
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Kernels/Integer/MatMul/Add
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Kernels/Integer/MaxPool
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Kernels/Integer/MaxPool/Regular_2D
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Kernels/Integer/Conv/Regular_2D_RQ
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Kernels/Integer/ReduceSum
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Kernels/Integer/ReduceMean

‎.github/workflows/ci-platform-generic.yml‎

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Kernels/FP32/Div
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Kernels/FP32/GEMM/Regular
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Kernels/FP32/MatMul
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Kernels/FP32/MaxPool
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Kernels/FP32/MaxPool/Regular_2D
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Kernels/FP32/Mul
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Kernels/FP32/LayerNorm
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Kernels/Integer/MatMul/Add
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Kernels/Integer/MatMul/Regular
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Kernels/Integer/MaxPool
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Kernels/Integer/MaxPool/Regular_2D
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Kernels/Integer/Pad/Regular_1D
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Kernels/Integer/Pad/Regular_2D

‎.github/workflows/ci-platform-mempool.yml‎

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Kernels/Integer/MatMul/Add
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Kernels/Integer/MatMul/Regular
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Kernels/Integer/MaxPool
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Kernels/Integer/MaxPool/Regular_2D
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Kernels/Integer/Pad/Regular_1D
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Kernels/Integer/Pad/Regular_2D

‎.github/workflows/ci-platform-siracusa-tiled.yml‎

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{"name":"Kernels/FP32/GEMM/Regular","L1":[8000]},
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{"name":"Kernels/FP32/MatMul","L1":[2000]},
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{"name":"Kernels/FP32/MaxPool","L1":[2000]},
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{"name":"Kernels/FP32/MaxPool/Regular_2D","L1":[2000]},
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{"name":"Kernels/FP32/Mul","L1":[2000]},
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{"name":"Kernels/FP32/LayerNorm","L1":[2000]},
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{"name":"Kernels/FP32/GEMM/Regular","L1":[8000]},
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{"name":"Kernels/FP32/MatMul","L1":[5000]},
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{"name":"Kernels/FP32/MaxPool","L1":[5000]},
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{"name":"Kernels/FP32/MaxPool/Regular_2D","L1":[5000]},
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{"name":"Kernels/FP32/Mul","L1":[2000]},
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{"name":"Kernels/FP32/LayerNorm","L1":[2000]},
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‎.github/workflows/ci-platform-siracusa.yml‎

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Kernels/FP32/GEMM/Regular
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Kernels/FP32/MatMul
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Kernels/FP32/MaxPool
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Kernels/FP32/MaxPool/Regular_2D
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Kernels/FP32/Mul
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Kernels/FP32/LayerNorm
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‎Deeploy/Targets/Generic/Bindings.py‎

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]
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BasicMaxPool1DBindings = [
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NodeBinding(MaxPoolChecker([PointerClass(int8_t)], [PointerClass(int8_t)]), MaxPoolTemplate.reference1DTemplate,
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BasicTransformer)
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] + [
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NodeBinding(MaxPoolChecker([PointerClass(type)], [PointerClass(type)]), FloatMaxPoolTemplate.reference1DTemplate,
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BasicTransformer) for type in FloatDataTypes
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]

‎Deeploy/Targets/Generic/Templates/MaxPoolTemplate.py‎

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from Deeploy.DeeployTypes import NetworkContext, NodeTemplate, OperatorRepresentation
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class _MaxPool2DTemplate(NodeTemplate):
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class _MaxPoolTemplate(NodeTemplate):
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def __init__(self, templateStr):
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super().__init__(templateStr)
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return ctxt, operatorRepresentation, []
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referenceTemplate = _MaxPool2DTemplate("""
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referenceTemplate = _MaxPoolTemplate("""
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<%
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batchOffsetIn = ch_im_in * dim_im_in_x * dim_im_in_y
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batchOffsetOut = ch_im_out * dim_im_out_x * dim_im_out_y
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}
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END_SINGLE_CORE
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""")
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reference1DTemplate = _MaxPoolTemplate("""
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<%
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batchOffsetIn = ch_im_in * dim_im_in_y
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batchOffsetOut = ch_im_out * dim_im_out_y
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%>
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// 1D MaxPool (Name: ${nodeName}, Op: ${nodeOp})
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BEGIN_SINGLE_CORE
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${data_in_type.typeName} ref_${data_out}_${data_in} = ${data_in};
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${data_out_type.typeName} ref_${data_out}_${data_out} = ${data_out};
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for (uint32_t n=0; n<${batch}; ++n) {
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MaxPool1d_s${data_in_type.referencedType.typeWidth}_s${data_out_type.referencedType.typeWidth}(
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ref_${data_out}_${data_in}, ${ch_im_in}, ${dim_im_in_y},
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${dim_kernel_y}, ${stride_y},
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ref_${data_out}_${data_out}, ${input_offset}, ${output_offset}
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);
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ref_${data_out}_${data_in} += ${batchOffsetIn};
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ref_${data_out}_${data_out} += ${batchOffsetOut};
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}
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END_SINGLE_CORE
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""")

‎DeeployTest/Tests/Kernels/FP32/MaxPool/Regular_1D/inputs.npz‎

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‎DeeployTest/Tests/Kernels/FP32/MaxPool/Regular_1D/network.onnx‎

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